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Configuration structure for one direction (TX or RX) of the SAI module. More...

#include <sai.h>

Public Attributes

bool enable {false}
 
uint8_t startDly {1}
 
startCond_t startCond {START_FRAME_EDGE}
 
clkGate_t clkGate {CLK_GATE_CONTINUOUS}
 
clkOut_t clkOut {CLK_OUT_CONTINUOUS}
 
clkSrc_t clkSrc {CLK_SRC_MCK}
 
clkCh_t clkCh {CLK_CH_CH}
 
clkPol_t clkPol {CLK_ACTIVE_HIGH}
 
uint8_t syncLen {0}
 
frameEdge_t syncEdge {FRAME_SYNC_FALLING}
 
frameSyncOut_t syncOut {FRAME_SYNC_INPUT}
 
frameSyncCh_t syncCh {SYNC_CH_CH}
 
uint8_t wordsPerFrame {2}
 
dataPacking_t dataPacking {BUFFER_WORD32_RIGHT}
 
bool unifyDataStream {false}
 
bitOrder_t bitOrder {MOST_SIG_FIRST}
 
bool lineIdleState {1}
 
uint8_t bitsPerWord {24}
 
uint32_t wordMask {0}
 
bufferDepletionBehavior_t depletionBehavior {DEPLETED_PAUSE}
 

Detailed Description

Configuration structure for one direction (TX or RX) of the SAI module.

This structure contains all parameters needed to configure either the transmit or receive channel of the SAI peripheral. The same structure type is used for both directions, with appropriate defaults provided by predefined configurations.

Timing Configuration

The SAI operates on a frame-based model where:

  • A frame consists of multiple words
  • Each word consists of multiple bits
  • Frame sync marks the start of each frame
  • Bit clock times each bit transfer

Example Configuration

SAI_rxtx_cfg_t txConfig;
txConfig.enable = true;
txConfig.startDly = 1; // Standard I2S: 1 bit delay
txConfig.clkOut = CLK_OUT_INPUT; // Slave mode
txConfig.clkSrc = CLK_SRC_EXT; // External clock
txConfig.wordsPerFrame = 2; // Stereo
txConfig.bitsPerWord = 24; // 24-bit samples
@ CLK_SRC_EXT
Definition sai.h:223
@ BUFFER_WORD32_RIGHT
Definition sai.h:358
@ CLK_OUT_INPUT
Definition sai.h:322
@ START_FRAME_EDGE
Definition sai.h:282
Configuration structure for one direction (TX or RX) of the SAI module.
Definition sai.h:439
dataPacking_t dataPacking
Definition sai.h:494
bool enable
Definition sai.h:441
clkSrc_t clkSrc
Definition sai.h:461
uint8_t startDly
Definition sai.h:449
uint8_t wordsPerFrame
Definition sai.h:491
uint8_t bitsPerWord
Definition sai.h:516
clkOut_t clkOut
Definition sai.h:458
startCond_t startCond
Definition sai.h:452

Member Data Documentation

◆ bitOrder

bitOrder_t SAI_rxtx_cfg_t::bitOrder {MOST_SIG_FIRST}

Bit transmission order (MSB first is standard)

◆ bitsPerWord

uint8_t SAI_rxtx_cfg_t::bitsPerWord {24}

Number of bits per word (valid audio sample size). Common values: 8, 16, 24, 32

◆ clkCh

clkCh_t SAI_rxtx_cfg_t::clkCh {CLK_CH_CH}

Clock channel selection (default/RX/TX)

◆ clkGate

clkGate_t SAI_rxtx_cfg_t::clkGate {CLK_GATE_CONTINUOUS}

Clock gating mode for power management

◆ clkOut

clkOut_t SAI_rxtx_cfg_t::clkOut {CLK_OUT_CONTINUOUS}

Clock output mode (input/continuous output/gated output)

◆ clkPol

clkPol_t SAI_rxtx_cfg_t::clkPol {CLK_ACTIVE_HIGH}

Clock polarity (active high/low)

◆ clkSrc

clkSrc_t SAI_rxtx_cfg_t::clkSrc {CLK_SRC_MCK}

Clock source selection (master clock or external)

◆ dataPacking

dataPacking_t SAI_rxtx_cfg_t::dataPacking {BUFFER_WORD32_RIGHT}

Buffer word format and data justification

◆ depletionBehavior

bufferDepletionBehavior_t SAI_rxtx_cfg_t::depletionBehavior {DEPLETED_PAUSE}

DMA behavior when buffer queue is exhausted

◆ enable

bool SAI_rxtx_cfg_t::enable {false}

Enable this channel (true = enabled, false = disabled)

◆ lineIdleState

bool SAI_rxtx_cfg_t::lineIdleState {1}

Logic level to drive on data line when idle (between words).

  • true: Drive high when idle
  • false: Drive low when idle

◆ startCond

startCond_t SAI_rxtx_cfg_t::startCond {START_FRAME_EDGE}

Starting condition that triggers data transfer

◆ startDly

uint8_t SAI_rxtx_cfg_t::startDly {1}

Data delay in bit clocks from frame sync to first data bit.

  • I2S standard: 1 bit delay
  • Left-justified: 0 bit delay
  • Right-justified: varies based on word size

◆ syncCh

frameSyncCh_t SAI_rxtx_cfg_t::syncCh {SYNC_CH_CH}

Frame sync channel selection (default/RX/TX)

◆ syncEdge

frameEdge_t SAI_rxtx_cfg_t::syncEdge {FRAME_SYNC_FALLING}

Frame sync edge defining frame boundary

◆ syncLen

uint8_t SAI_rxtx_cfg_t::syncLen {0}

Frame sync pulse width in bit clocks.

  • 0: Single bit clock wide (typical for I2S)
  • >0: Specified number of bit clocks

◆ syncOut

frameSyncOut_t SAI_rxtx_cfg_t::syncOut {FRAME_SYNC_INPUT}

Frame sync output mode (input/negative pulse/positive pulse)

◆ unifyDataStream

bool SAI_rxtx_cfg_t::unifyDataStream {false}

Unify data stream across multiple SAI data lines. When true, treats multiple data lines as a single stream.

◆ wordMask

uint32_t SAI_rxtx_cfg_t::wordMask {0}

Word slot mask for frames with multiple words. Each bit represents a word slot:

  • 0 = word slot active (transmitted/received)
  • 1 = word slot masked (skipped)

Example for stereo with left channel only: 0x00000002

◆ wordsPerFrame

uint8_t SAI_rxtx_cfg_t::wordsPerFrame {2}

Number of words contained in each frame.

  • Mono: 1 word per frame
  • Stereo: 2 words per frame
  • Multi-channel: N words per frame

The documentation for this struct was generated from the following file: