SAI Configuration Enumerations

Enumerations
enum	clkSrc_t { CLK_SRC_MCK , CLK_SRC_EXT }
	Clock source selection for SAI bit clock generation. More...
enum	clkCh_t { CLK_CH_CH , CLK_CH_RK , CLK_CH_TK }
	Clock channel selection for determining which clock signal to use. More...
enum	clkPol_t { CLK_ACTIVE_HIGH , CLK_ACTIVE_LOW }
	Clock polarity configuration. More...
enum	frameSyncCh_t { SYNC_CH_CH , SYNC_CH_RX , SYNC_CH_TX }
	Frame synchronization channel selection. More...
enum	startCond_t {   START_CONTINUOUS , START_SYNC_RX_TX , START_FRAME_LOW , START_FRAME_HIGH ,   START_FRAME_FALLING , START_FRAME_RISING , START_FRAME_LEVEL , START_FRAME_EDGE ,   START_CMP_0 }
	Starting conditions that trigger SAI data transfers. More...
enum	clkGate_t { CLK_GATE_CONTINUOUS , CLK_GATE_FRAME_LOW , CLK_GATE_FRAME_HIGH }
	Clock gating mode for power optimization. More...
enum	frameEdge_t { FRAME_SYNC_RISING , FRAME_SYNC_FALLING }
	Frame sync edge that indicates the start of a new frame. More...
enum	clkOut_t { CLK_OUT_INPUT , CLK_OUT_CONTINUOUS , CLK_OUT_TRANSFER }
	Bit clock output mode configuration. More...
enum	frameSyncOut_t { FRAME_SYNC_INPUT , FRAME_SYNC_NEGATIVE , FRAME_SYNC_POSITIVE }
	Frame synchronization signal output mode. More...
enum	dataPacking_t {   BUFFER_WORD8 , BUFFER_WORD16_LEFT , BUFFER_WORD16_RIGHT , BUFFER_WORD32_LEFT ,   BUFFER_WORD32_RIGHT }
	Buffer word format and data justification. More...
enum	bitOrder_t { LEAST_SIG_FIRST , MOST_SIG_FIRST }
	Bit transmission order within each word. More...
enum	bufferDepletionBehavior_t { DEPLETED_PAUSE , DEPLETED_REPEAT_LAST }
	DMA behavior when all queued buffers are exhausted. More...
enum	rxTxSync_t { RXTX_ASYNC , RXTX_SYNC_RX , RXTX_SYNC_TX }
	Synchronization mode between RX and TX channels. More...

Detailed Description

Enumeration Type Documentation

bitOrder_t

enum bitOrder_t

#include <sai.h>

Bit transmission order within each word.

Determines whether the least significant bit or most significant bit is transmitted first on the data line.

Enumerator
LEAST_SIG_FIRST	LSB transmitted first (uncommon for audio)
MOST_SIG_FIRST	MSB transmitted first (standard for I2S and most audio protocols)

bufferDepletionBehavior_t

enum bufferDepletionBehavior_t

#include <sai.h>

DMA behavior when all queued buffers are exhausted.

Defines what the DMA channel should do when it runs out of buffers to process. This is critical for preventing underruns/overruns.

Enumerator
DEPLETED_PAUSE	Pause transfers when buffers depleted (recommended for most uses)
DEPLETED_REPEAT_LAST	Continuously repeat the last buffer in the chain (useful for streaming)

clkCh_t

enum clkCh_t

#include <sai.h>

Clock channel selection for determining which clock signal to use.

Allows selection between transmit clock, receive clock, or channel default. Used for clock sharing between TX and RX channels.

Enumerator
CLK_CH_CH	Use the channel's default clock source
CLK_CH_RK	Use the receive clock (BCLK_RX) for this channel
CLK_CH_TK	Use the transmit clock (BCLK_TX) for this channel

clkGate_t

enum clkGate_t

#include <sai.h>

Clock gating mode for power optimization.

Controls when the bit clock is actively driven to reduce power consumption and EMI when no data transfer is occurring.

Enumerator
CLK_GATE_CONTINUOUS	Clock runs continuously (always enabled)
CLK_GATE_FRAME_LOW	Clock enabled only when frame sync is low
CLK_GATE_FRAME_HIGH	Clock enabled only when frame sync is high

clkOut_t

enum clkOut_t

#include <sai.h>

Bit clock output mode configuration.

Controls whether the bit clock is driven as an output (master mode) or used as an input (slave mode), and when it is active.

Enumerator
CLK_OUT_INPUT	Clock is an input; output driver is disabled (slave mode)
CLK_OUT_CONTINUOUS	Clock is continuously driven as output (master mode)
CLK_OUT_TRANSFER	Clock is driven only during active transfers (master mode with gating)

clkPol_t

enum clkPol_t

#include <sai.h>

Clock polarity configuration.

Determines the active edge of the bit clock for data sampling and driving.

Enumerator
CLK_ACTIVE_HIGH	Clock is active high: drive data on rising edge, sample on falling edge
CLK_ACTIVE_LOW	Clock is active low: drive data on falling edge, sample on rising edge

clkSrc_t

enum clkSrc_t

#include <sai.h>

Clock source selection for SAI bit clock generation.

The SAI can generate its bit clock from different sources depending on whether the device is operating as a master or slave.

Enumerator
CLK_SRC_MCK	Clock source is the divided peripheral master clock (for master mode)
CLK_SRC_EXT	Clock source is an external clock input (for slave mode or clock sharing)

dataPacking_t

enum dataPacking_t

#include <sai.h>

Buffer word format and data justification.

Defines how data is packed in memory buffers and whether it is left-justified or right-justified within the word. This affects how the DMA interprets the buffer data when moving it to/from the SAI FIFO.

Note

Left-justified packs MSBs at the upper bits of the word. Right-justified packs LSBs at the lower bits of the word.

Enumerator
BUFFER_WORD8	Each sample is 8 bits (1 byte per sample)
BUFFER_WORD16_LEFT	Each sample is 16 bits, left-justified in the word
BUFFER_WORD16_RIGHT	Each sample is 16 bits, right-justified in the word
BUFFER_WORD32_LEFT	Each sample is 32 bits, left-justified in the word
BUFFER_WORD32_RIGHT	Each sample is 32 bits, right-justified in the word

frameEdge_t

enum frameEdge_t

#include <sai.h>

Frame sync edge that indicates the start of a new frame.

Determines whether a rising or falling edge of the frame sync signal marks the beginning of a data frame.

Enumerator
FRAME_SYNC_RISING	New frame begins on rising edge of frame sync
FRAME_SYNC_FALLING	New frame begins on falling edge of frame sync

frameSyncCh_t

enum frameSyncCh_t

#include <sai.h>

Frame synchronization channel selection.

Determines which frame sync signal is used for synchronizing frame boundaries. Allows sharing of frame sync between TX and RX channels.

Enumerator
SYNC_CH_CH	Use the channel's default frame sync signal
SYNC_CH_RX	Use the receive frame sync (FRAME_SYNC_RX) for this channel
SYNC_CH_TX	Use the transmit frame sync (FRAME_SYNC_TX) for this channel

frameSyncOut_t

enum frameSyncOut_t

#include <sai.h>

Frame synchronization signal output mode.

Configures whether the frame sync is an input or output, and the polarity of the pulse when operating as an output.

Enumerator
FRAME_SYNC_INPUT	Frame sync is an input; output driver disabled (slave mode)
FRAME_SYNC_NEGATIVE	Frame sync driven with negative pulse at frame start (active low)
FRAME_SYNC_POSITIVE	Frame sync driven with positive pulse at frame start (active high)

rxTxSync_t

enum rxTxSync_t

#include <sai.h>

Synchronization mode between RX and TX channels.

Determines whether the receive and transmit channels operate independently or share clock and frame sync signals.

Enumerator
RXTX_ASYNC	RX and TX are completely independent (separate clocks and frame sync)
RXTX_SYNC_RX	TX synchronized to RX (both use RX clock and frame sync)
RXTX_SYNC_TX	RX synchronized to TX (both use TX clock and frame sync)

startCond_t

enum startCond_t

#include <sai.h>

Starting conditions that trigger SAI data transfers.

Defines when the SAI peripheral should begin transferring data. Different conditions are appropriate for different protocols and operating modes.

Enumerator
START_CONTINUOUS	Continuous operation: transfers start immediately when previous ends
START_SYNC_RX_TX	Synchronous start: transfers begin when opposite channel starts
START_FRAME_LOW	Start when frame sync signal is low
START_FRAME_HIGH	Start when frame sync signal is high
START_FRAME_FALLING	Start on falling edge of frame sync
START_FRAME_RISING	Start on rising edge of frame sync
START_FRAME_LEVEL	Start on any level change of frame sync
START_FRAME_EDGE	Start on any edge (rising or falling) of frame sync
START_CMP_0	Start when received data matches Compare 0 register value (RX only)