semc_utils.h

 
#ifndef SEMC_UTILS_H
#define SEMC_UTILS_H
 
#include <semc.h>
#include <stdint.h>
 
// ============================================================================
// TIMING CALCULATION MACROS
// ============================================================================

#define NS_TO_CYCLES_CLK(ns, clk_mhz) (((ns) * (clk_mhz) + 999) / 1000)

#define CYCLES_TO_N_PLUS_1_VAL(cycles) ((cycles) > 0 ? (cycles) - 1 : 0)

#define PS_TO_CYCLES(ps, clk_mhz) (((ps) * (clk_mhz) + 999999) / 1000000)

#define CYCLES_TO_NS(cycles, clk_mhz) (((cycles) * 1000) / (clk_mhz))

#define TIMING_OK(configured_cycles, required_ns, clk_mhz) \
    (CYCLES_TO_NS(configured_cycles, clk_mhz) >= (required_ns))
 
// ============================================================================
// CONFIGURATION VALIDATION MACROS
// ============================================================================

#define IS_ALIGNED(addr, size) (((addr) & ((size) - 1)) == 0)

#define IS_POWER_OF_2(size) (((size) != 0) && (((size) & ((size) - 1)) == 0))

#define IS_SEMC_ADDR(addr) ((addr) >= 0x80000000 && (addr) < 0xA0000000)
 
// ============================================================================
// COMMON SRAM DEVICE TIMING PRESETS
// ============================================================================

typedef struct {
    uint32_t address_access_time_ns;    
    uint32_t chip_enable_access_ns;     
    uint32_t output_enable_access_ns;   
    uint32_t write_cycle_time_ns;       
    uint32_t read_cycle_time_ns;        
    uint32_t address_setup_time_ns;     
    uint32_t address_hold_time_ns;      
    uint32_t chip_select_setup_ns;      
    uint32_t write_pulse_width_ns;      
    uint32_t output_hold_time_ns;       
} SRAM_Timing_Spec_t;

static const SRAM_Timing_Spec_t SRAM_10NS = {
    .address_access_time_ns = 10,
    .chip_enable_access_ns = 10,
    .output_enable_access_ns = 5,
    .write_cycle_time_ns = 10,
    .read_cycle_time_ns = 10,
    .address_setup_time_ns = 0,
    .address_hold_time_ns = 3,
    .chip_select_setup_ns = 0,
    .write_pulse_width_ns = 8,
    .output_hold_time_ns = 3
};

static const SRAM_Timing_Spec_t SRAM_55NS = {
    .address_access_time_ns = 55,
    .chip_enable_access_ns = 55,
    .output_enable_access_ns = 25,
    .write_cycle_time_ns = 55,
    .read_cycle_time_ns = 55,
    .address_setup_time_ns = 0,
    .address_hold_time_ns = 5,
    .chip_select_setup_ns = 0,
    .write_pulse_width_ns = 45,
    .output_hold_time_ns = 5
};

static const SRAM_Timing_Spec_t SRAM_70NS = {
    .address_access_time_ns = 70,
    .chip_enable_access_ns = 70,
    .output_enable_access_ns = 30,
    .write_cycle_time_ns = 70,
    .read_cycle_time_ns = 70,
    .address_setup_time_ns = 0,
    .address_hold_time_ns = 5,
    .chip_select_setup_ns = 10,
    .write_pulse_width_ns = 55,
    .output_hold_time_ns = 5
};
 
// ============================================================================
// HELPER FUNCTIONS FOR SEMC CONFIGURATION
// ============================================================================

inline SEMC_cfg_t CreateSEMCConfigFromSpec(
    const SRAM_Timing_Spec_t &spec,
    uint32_t clk_mhz,
    uint8_t bus_width,
    uint8_t margin_percent,
    PinIO clk_pin,
    PinIO cs_pin)
{
    SEMC_cfg_t cfg = {};
    
    // Apply margin to all timing values
    float margin = 1.0f + (margin_percent / 100.0f);
    
    // Basic configuration
    cfg.busWidth = (bus_width == 16) ? SEMC_BusWidth_t::Width_16 : SEMC_BusWidth_t::Width_8;
    cfg.clkMode = SEMC_ClkMode_t::Async;
    cfg.burstLen = SEMC_Burst_t::Burst_1;
    cfg.muxMode = SEMC_AddrMux_t::Mux;
    cfg.colAddrWidth = SEMC_ColAddrWidth_t::Width_0;
    cfg.advPol = false;
    cfg.advHoldLvl = false;
    
    // Calculate timing parameters with margin
    cfg.cs_setup = CYCLES_TO_N_PLUS_1_VAL(
        NS_TO_CYCLES_CLK(spec.chip_select_setup_ns * margin, clk_mhz)
    );
    
    cfg.cs_hold_min = CYCLES_TO_N_PLUS_1_VAL(
        NS_TO_CYCLES_CLK(10 * margin, clk_mhz)  // Minimum 10ns
    );
    
    cfg.addr_setup = CYCLES_TO_N_PLUS_1_VAL(
        NS_TO_CYCLES_CLK(spec.address_setup_time_ns * margin, clk_mhz)
    );
    
    cfg.addr_hold = CYCLES_TO_N_PLUS_1_VAL(
        NS_TO_CYCLES_CLK(spec.address_hold_time_ns * margin, clk_mhz)
    );
    
    cfg.wr_en_lo = CYCLES_TO_N_PLUS_1_VAL(
        NS_TO_CYCLES_CLK(spec.write_pulse_width_ns * margin, clk_mhz)
    );
    
    cfg.wr_en_hi = CYCLES_TO_N_PLUS_1_VAL(
        NS_TO_CYCLES_CLK((spec.write_cycle_time_ns - spec.write_pulse_width_ns) * margin, clk_mhz)
    );
    
    cfg.rd_en_lo = CYCLES_TO_N_PLUS_1_VAL(
        NS_TO_CYCLES_CLK(spec.output_enable_access_ns * margin, clk_mhz)
    );
    
    cfg.rd_en_hi = CYCLES_TO_N_PLUS_1_VAL(
        NS_TO_CYCLES_CLK(spec.address_access_time_ns * margin, clk_mhz)
    );
    
    cfg.addr_wr_hold = CYCLES_TO_N_PLUS_1_VAL(
        NS_TO_CYCLES_CLK(spec.address_hold_time_ns * margin, clk_mhz)
    );
    
    cfg.turnaround = 2;  // 2 cycle turnaround
    
    cfg.cs_min_intv = CYCLES_TO_N_PLUS_1_VAL(2);
    
    // Pin assignments
    cfg.clkPin = clk_pin;
    cfg.csPin = cs_pin;
    
    return cfg;
}

inline void PrintSEMCConfig(const SEMC_cfg_t &cfg, uint32_t clk_mhz)
{
    printf("SEMC Configuration Details:\n");
    printf("==========================\n");
    
    // Basic settings
    printf("Bus Width: %s\n", cfg.busWidth == SEMC_BusWidth_t::Width_16 ? "16-bit" : "8-bit");
    printf("Clock Mode: %s\n", cfg.clkMode == SEMC_ClkMode_t::Async ? "Async" : "Sync");
    printf("Mux Mode: ");
    switch (cfg.muxMode) {
        case SEMC_AddrMux_t::Mux: printf("Multiplexed\n"); break;
        case SEMC_AddrMux_t::AdvMux: printf("Advanced Mux\n"); break;
        case SEMC_AddrMux_t::Bus: printf("Non-multiplexed\n"); break;
    }
 
    // Timing parameters
    printf("\nTiming Parameters (Async Mode):\n");
    printf("  CS Setup: %u cycles (%u ns)\n",
           cfg.cs_setup + 1, CYCLES_TO_NS(cfg.cs_setup + 1, clk_mhz));
    printf("  CS Hold: %u cycles (%u ns)\n",
           cfg.cs_hold_min + 1, CYCLES_TO_NS(cfg.cs_hold_min + 1, clk_mhz));
    printf("  Address Setup: %u cycles (%u ns)\n",
           cfg.addr_setup + 1, CYCLES_TO_NS(cfg.addr_setup + 1, clk_mhz));
    printf("  Address Hold: %u cycles (%u ns)\n",
           cfg.addr_hold + 1, CYCLES_TO_NS(cfg.addr_hold + 1, clk_mhz));
    printf("  Write Enable Low: %u cycles (%u ns)\n",
           cfg.wr_en_lo + 1, CYCLES_TO_NS(cfg.wr_en_lo + 1, clk_mhz));
    printf("  Write Enable High: %u cycles (%u ns)\n",
           cfg.wr_en_hi + 1, CYCLES_TO_NS(cfg.wr_en_hi + 1, clk_mhz));
    printf("  Read Enable Low: %u cycles (%u ns)\n",
           cfg.rd_en_lo + 1, CYCLES_TO_NS(cfg.rd_en_lo + 1, clk_mhz));
    printf("  Read Enable High: %u cycles (%u ns)\n",
           cfg.rd_en_hi + 1, CYCLES_TO_NS(cfg.rd_en_hi + 1, clk_mhz));
    printf("  Address Write Hold: %u cycles (%u ns)\n",
           cfg.addr_wr_hold + 1, CYCLES_TO_NS(cfg.addr_wr_hold + 1, clk_mhz));
    printf("  Turnaround: %u cycles (%u ns)\n",
           cfg.turnaround, CYCLES_TO_NS(cfg.turnaround, clk_mhz));
    printf("  CS Min Interval: %u cycles (%u ns)\n",
           cfg.cs_min_intv + 1, CYCLES_TO_NS(cfg.cs_min_intv + 1, clk_mhz));
 
    // Calculated cycle times
    uint32_t write_cycle = (cfg.wr_en_lo + 1) + (cfg.wr_en_hi + 1);
    uint32_t read_cycle = (cfg.rd_en_lo + 1) + (cfg.rd_en_hi + 1);
    
    printf("\nCalculated Timing:\n");
    printf("  Write Cycle: %u cycles (%u ns)\n",
           write_cycle, CYCLES_TO_NS(write_cycle, clk_mhz));
    printf("  Read Cycle: %u cycles (%u ns)\n",
           read_cycle, CYCLES_TO_NS(read_cycle, clk_mhz));
    printf("==========================\n\n");
}

inline bool ValidateSEMCConfig(const SEMC_cfg_t &cfg, uint32_t base_addr, uint32_t size)
{
    bool valid = true;
    
    printf("Validating SEMC Configuration...\n");
    
    // Check address alignment
    if (!IS_ALIGNED(base_addr, size)) {
        printf("  ERROR: Base address 0x%08X not aligned to size 0x%08X\n",
               base_addr, size);
        valid = false;
    }
    
    // Check size is power of 2
    if (!IS_POWER_OF_2(size)) {
        printf("  ERROR: Size 0x%08X is not a power of 2\n", size);
        valid = false;
    }
    
    // Check address range
    if (!IS_SEMC_ADDR(base_addr)) {
        printf("  ERROR: Base address 0x%08X not in valid SEMC range (0x80000000-0x9FFFFFFF)\n",
               base_addr);
        valid = false;
    }
    
    // Check for potential timing issues
    if (cfg.cs_setup == 0) {
        printf("  WARNING: CS setup is 0 - consider adding margin\n");
    }
    
    if (cfg.rd_en_hi < 3) {
        printf("  WARNING: Read enable high is very short - may not meet timing\n");
    }
    
    if (cfg.wr_en_hi < 3) {
        printf("  WARNING: Write enable high is very short - may not meet timing\n");
    }
    
    if (valid) {
        printf("  Configuration validation PASSED\n");
    } else {
        printf("  Configuration validation FAILED\n");
    }
    
    return valid;
}
 
#endif // SEMC_UTILS_H