SEMC_cfg_t Struct Reference

Configuration structure for SEMC (Smart External Memory Controller) interface. More...

#include <semc.h>

Public Attributes
union {
uint32_t   CR0
};
	Control Register 0 - Basic Interface Configuration.
union {
uint32_t   CR1
};
	Control Register 1 - Primary Timing Configuration.
union {
uint32_t   CR2
};
	Control Register 2 - Extended Timing Configuration.
PinIO	clkPin
PinIO	csPin

Detailed Description

Configuration structure for SEMC (Smart External Memory Controller) interface.

This structure configures the timing and control parameters for SEMC chip selects, supporting both synchronous and asynchronous memory devices. The SEMC interface allows connection to external SRAM, PSRAM, NOR Flash, and other parallel memory devices.

The configuration is divided into three control registers (CR0, CR1, CR2) that can be accessed either as structured bit fields or as complete 32-bit values for direct register programming.

Note

• All timing parameters marked as "n+1" mean the actual bus timing will be the configured value plus one clock cycle. For example, cs_setup = 2 results in 3 clock cycles on the bus.
• Parameters marked "async mode only" are ignored in synchronous/burst mode and vice versa. Refer to the clkMode field to determine which mode is active.

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Expand for Example Usage

Examples

Asynchronous SRAM Configuration (8-bit)

SEMC_cfg_t asyncSRAM = {};
 
// CR0 - Basic configuration
asyncSRAM.busWidth = SEMC_BUS_WIDTH_8BIT;
asyncSRAM.clkMode = SEMC_CLK_ASYNC;
asyncSRAM.muxMode = SEMC_MUX_A8;
 
// CR1 - Async timing parameters
asyncSRAM.cs_setup = 1;      // 2 cycles (1+1)
asyncSRAM.cs_hold_min = 1;   // 2 cycles (1+1)
asyncSRAM.addr_setup = 1;    // 2 cycles (1+1)
asyncSRAM.addr_hold = 1;     // 2 cycles (1+1)
asyncSRAM.wr_en_lo = 2;      // 3 cycles (2+1)
asyncSRAM.wr_en_hi = 2;      // 3 cycles (2+1)
asyncSRAM.rd_en_lo = 2;      // 3 cycles (2+1)
asyncSRAM.rd_en_hi = 2;      // 3 cycles (2+1)
 
// CR2 - Additional async parameters
asyncSRAM.addr_wr_hold = 1;  // 2 cycles (1+1)
asyncSRAM.turnaround = 2;    // 2 cycles (n, no +1)
asyncSRAM.cs_min_intv = 1;   // 2 cycles (1+1)
 
// Pin assignments
asyncSRAM.csPin = Pins[10];

Synchronous Burst PSRAM Configuration (16-bit)

SEMC_cfg_t syncPSRAM = {};
 
// CR0 - Synchronous burst configuration
syncPSRAM.busWidth = SEMC_BUS_WIDTH_16BIT;
syncPSRAM.clkMode = SEMC_CLK_SYNC;
syncPSRAM.burstLen = SEMC_BURST_8;
syncPSRAM.muxMode = SEMC_MUX_A8;
syncPSRAM.colAddrWidth = SEMC_COL_ADDR_10BIT;
 
// CR1 - Basic timing
syncPSRAM.cs_setup = 0;      // 1 cycle (0+1)
syncPSRAM.cs_hold_min = 0;   // 1 cycle (0+1)
syncPSRAM.addr_setup = 0;    // 1 cycle (0+1)
syncPSRAM.addr_hold = 1;     // 1 cycle (n, no +1 in sync mode)
 
// CR2 - Synchronous/burst timing
syncPSRAM.wr_dat_setup = 1;  // 2 cycles (1+1)
syncPSRAM.wr_dat_hold = 1;   // 1 cycle (n, no +1)
syncPSRAM.latency = 3;       // 3 cycle latency (n, no +1)
syncPSRAM.rd_cycle = 3;      // 4 cycles (3+1)
syncPSRAM.rd_hold = 1;       // 1 cycle (n, no +1)
syncPSRAM.cs_min_intv = 1;   // 2 cycles (1+1)
 
// Pin assignments
syncPSRAM.clkPin = Pins[15];
syncPSRAM.csPin = Pins[16];

Fast NOR Flash Configuration (Async Mode)

SEMC_cfg_t norFlash = {};
 
// CR0 - 16-bit async configuration
norFlash.busWidth = SEMC_BUS_WIDTH_16BIT;
norFlash.clkMode = SEMC_CLK_ASYNC;
norFlash.muxMode = SEMC_MUX_A8;
 
// CR1 - Fast async timing for modern NOR Flash
norFlash.cs_setup = 0;       // 1 cycle (0+1)
norFlash.cs_hold_min = 0;    // 1 cycle (0+1)
norFlash.addr_setup = 0;     // 1 cycle (0+1)
norFlash.addr_hold = 0;      // 1 cycle (0+1)
norFlash.wr_en_lo = 3;       // 4 cycles (3+1)
norFlash.wr_en_hi = 3;       // 4 cycles (3+1)
norFlash.rd_en_lo = 4;       // 5 cycles (4+1) - longer for read
norFlash.rd_en_hi = 4;       // 5 cycles (4+1)
 
// CR2 - Turnaround time for bus release
norFlash.addr_wr_hold = 1;   // 2 cycles (1+1)
norFlash.turnaround = 3;     // 3 cycles (n, no +1)
norFlash.cs_min_intv = 2;    // 3 cycles (2+1)
 
// Pin assignment
norFlash.csPin = Pins[20];

Direct Register Programming

SEMC_cfg_t directConfig = {};
 
// Set entire control registers at once
directConfig.CR0 = 0x00000091;  // Pre-calculated register value
directConfig.CR1 = 0x22222222;  // Pre-calculated timing
directConfig.CR2 = 0x11111111;  // Pre-calculated timing
 
// Pin assignments
directConfig.csPin = Pins[12];

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Member Data Documentation

[union]

union { ... } SEMC_cfg_t

Control Register 0 - Basic Interface Configuration.

Contains fundamental interface parameters including bus width, clock mode, burst length, multiplexing mode, and column address width. Can be accessed as individual bit fields or as a complete 32-bit register value.

[union]

union { ... } SEMC_cfg_t

Control Register 1 - Primary Timing Configuration.

Defines setup, hold, and enable timing for chip select, address, write enable, and read enable signals. Parameters apply differently depending on clock mode (async vs sync). Most values are "n+1" meaning actual cycles = configured + 1.

[union]

union { ... } SEMC_cfg_t

Control Register 2 - Extended Timing Configuration.

Contains additional timing parameters for both synchronous and asynchronous modes. Includes write data timing, latency, read cycle length, turnaround, and minimum chip select interval. Parameters are mode-specific.

addr_hold

uint32_t SEMC_cfg_t::addr_hold

Address hold time: Async=(n+1), Sync=(n) cycles

addr_setup

uint32_t SEMC_cfg_t::addr_setup

Address setup time before control signal (n+1 cycles)

addr_wr_hold

uint32_t SEMC_cfg_t::addr_wr_hold

Address to write hold time (n+1 cycles, async only)

advHoldLvl

bool SEMC_cfg_t::advHoldLvl

ADV signal hold level

advPol

bool SEMC_cfg_t::advPol

Address valid (ADV) signal polarity

burstLen

SEMC_Burst_t SEMC_cfg_t::burstLen

Burst transfer length for synchronous mode

busWidth

SEMC_BusWidth_t SEMC_cfg_t::busWidth

Data bus width (8-bit or 16-bit)

clkMode

SEMC_ClkMode_t SEMC_cfg_t::clkMode

Clock mode (asynchronous or synchronous)

clkPin

PinIO SEMC_cfg_t::clkPin

Clock output pin assignment (synchronous mode only)

colAddrWidth

SEMC_ColAddrWidth_t SEMC_cfg_t::colAddrWidth

Column address bit width (synchronous mode)

CR0

uint32_t SEMC_cfg_t::CR0

Direct access to complete Control Register 0

CR1

uint32_t SEMC_cfg_t::CR1

Direct access to complete Control Register 1

CR2

uint32_t SEMC_cfg_t::CR2

Direct access to complete Control Register 2

cs_hold_min

uint32_t SEMC_cfg_t::cs_hold_min

Minimum chip select hold time after cycle end (n+1 cycles)

cs_min_intv

uint32_t SEMC_cfg_t::cs_min_intv

Minimum interval between chip select assertions (n+1 cycles)

cs_setup

uint32_t SEMC_cfg_t::cs_setup

Chip select setup time before address valid (n+1 cycles)

csPin

PinIO SEMC_cfg_t::csPin

Chip select output pin assignment

latency

uint32_t SEMC_cfg_t::latency

Read data latency cycles (n cycles, sync/burst only)

muxMode

SEMC_AddrMux_t SEMC_cfg_t::muxMode

Address/data multiplexing mode

rd_cycle

uint32_t SEMC_cfg_t::rd_cycle

Total read cycle length (n+1 cycles, sync/burst only)

rd_en_hi

uint32_t SEMC_cfg_t::rd_en_hi

Read enable high period (n+1 cycles, async only)

rd_en_lo

uint32_t SEMC_cfg_t::rd_en_lo

Read enable low pulse width (n+1 cycles, async only)

rd_hold

uint32_t SEMC_cfg_t::rd_hold

Read data hold time (n cycles, sync/burst only)

RESERVED0

uint8_t SEMC_cfg_t::RESERVED0

Reserved bits, must be 0

RESERVED1

uint8_t SEMC_cfg_t::RESERVED1

Reserved bit, must be 0

turnaround

uint32_t SEMC_cfg_t::turnaround

Bus turnaround time between transfers (n cycles, async only)

wr_dat_hold

uint32_t SEMC_cfg_t::wr_dat_hold

Write data hold time (n cycles, sync/burst only)

wr_dat_setup

uint32_t SEMC_cfg_t::wr_dat_setup

Write data setup time (n+1 cycles, sync/burst only)

wr_en_hi

uint32_t SEMC_cfg_t::wr_en_hi

Write enable high period (n+1 cycles, async only)

wr_en_lo

uint32_t SEMC_cfg_t::wr_en_lo

Write enable low pulse width (n+1 cycles, async only)

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The documentation for this struct was generated from the following file:

• semc.h