SEMC_cfg_t Struct Reference

Configuration structure for SEMC (Smart External Memory Controller) interface. More...

#include <semc.h>

Classes
union	[union].__unnamed0__
	Control Register 0 - Basic Interface Configuration. More...
union	[union].__unnamed1__
	Control Register 1 - Primary Timing Configuration. More...
union	[union].__unnamed2__
	Control Register 2 - Extended Timing Configuration. More...

Public Attributes
PinIO	clkPin
PinIO	csPin

Detailed Description

Configuration structure for SEMC (Smart External Memory Controller) interface.

This structure configures the timing and control parameters for SEMC chip selects, supporting both synchronous and asynchronous memory devices. The SEMC interface allows connection to external SRAM, PSRAM, NOR Flash, and other parallel memory devices.

The configuration is divided into three control registers (CR0, CR1, CR2) that can be accessed either as structured bit fields or as complete 32-bit values for direct register programming.

Note

• All timing parameters marked as "n+1" mean the actual bus timing will be the configured value plus one clock cycle. For example, cs_setup = 2 results in 3 clock cycles on the bus.
• Parameters marked "async mode only" are ignored in synchronous/burst mode and vice versa. Refer to the clkMode field to determine which mode is active.

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Expand for Example Usage

Examples

Asynchronous SRAM Configuration (8-bit)

SEMC_cfg_t asyncSRAM = {};
 
// CR0 - Basic configuration
asyncSRAM.busWidth = SEMC_BUS_WIDTH_8BIT;
asyncSRAM.clkMode = SEMC_CLK_ASYNC;
asyncSRAM.muxMode = SEMC_MUX_A8;
 
// CR1 - Async timing parameters
asyncSRAM.cs_setup = 1;      // 2 cycles (1+1)
asyncSRAM.cs_hold_min = 1;   // 2 cycles (1+1)
asyncSRAM.addr_setup = 1;    // 2 cycles (1+1)
asyncSRAM.addr_hold = 1;     // 2 cycles (1+1)
asyncSRAM.wr_en_lo = 2;      // 3 cycles (2+1)
asyncSRAM.wr_en_hi = 2;      // 3 cycles (2+1)
asyncSRAM.rd_en_lo = 2;      // 3 cycles (2+1)
asyncSRAM.rd_en_hi = 2;      // 3 cycles (2+1)
 
// CR2 - Additional async parameters
asyncSRAM.addr_wr_hold = 1;  // 2 cycles (1+1)
asyncSRAM.turnaround = 2;    // 2 cycles (n, no +1)
asyncSRAM.cs_min_intv = 1;   // 2 cycles (1+1)
 
// Pin assignments
asyncSRAM.csPin = Pins[10];

Synchronous Burst PSRAM Configuration (16-bit)

SEMC_cfg_t syncPSRAM = {};
 
// CR0 - Synchronous burst configuration
syncPSRAM.busWidth = SEMC_BUS_WIDTH_16BIT;
syncPSRAM.clkMode = SEMC_CLK_SYNC;
syncPSRAM.burstLen = SEMC_BURST_8;
syncPSRAM.muxMode = SEMC_MUX_A8;
syncPSRAM.colAddrWidth = SEMC_COL_ADDR_10BIT;
 
// CR1 - Basic timing
syncPSRAM.cs_setup = 0;      // 1 cycle (0+1)
syncPSRAM.cs_hold_min = 0;   // 1 cycle (0+1)
syncPSRAM.addr_setup = 0;    // 1 cycle (0+1)
syncPSRAM.addr_hold = 1;     // 1 cycle (n, no +1 in sync mode)
 
// CR2 - Synchronous/burst timing
syncPSRAM.wr_dat_setup = 1;  // 2 cycles (1+1)
syncPSRAM.wr_dat_hold = 1;   // 1 cycle (n, no +1)
syncPSRAM.latency = 3;       // 3 cycle latency (n, no +1)
syncPSRAM.rd_cycle = 3;      // 4 cycles (3+1)
syncPSRAM.rd_hold = 1;       // 1 cycle (n, no +1)
syncPSRAM.cs_min_intv = 1;   // 2 cycles (1+1)
 
// Pin assignments
syncPSRAM.clkPin = Pins[15];
syncPSRAM.csPin = Pins[16];

Fast NOR Flash Configuration (Async Mode)

SEMC_cfg_t norFlash = {};
 
// CR0 - 16-bit async configuration
norFlash.busWidth = SEMC_BUS_WIDTH_16BIT;
norFlash.clkMode = SEMC_CLK_ASYNC;
norFlash.muxMode = SEMC_MUX_A8;
 
// CR1 - Fast async timing for modern NOR Flash
norFlash.cs_setup = 0;       // 1 cycle (0+1)
norFlash.cs_hold_min = 0;    // 1 cycle (0+1)
norFlash.addr_setup = 0;     // 1 cycle (0+1)
norFlash.addr_hold = 0;      // 1 cycle (0+1)
norFlash.wr_en_lo = 3;       // 4 cycles (3+1)
norFlash.wr_en_hi = 3;       // 4 cycles (3+1)
norFlash.rd_en_lo = 4;       // 5 cycles (4+1) - longer for read
norFlash.rd_en_hi = 4;       // 5 cycles (4+1)
 
// CR2 - Turnaround time for bus release
norFlash.addr_wr_hold = 1;   // 2 cycles (1+1)
norFlash.turnaround = 3;     // 3 cycles (n, no +1)
norFlash.cs_min_intv = 2;    // 3 cycles (2+1)
 
// Pin assignment
norFlash.csPin = Pins[20];

Direct Register Programming

SEMC_cfg_t directConfig = {};
 
// Set entire control registers at once
directConfig.CR0 = 0x00000091;  // Pre-calculated register value
directConfig.CR1 = 0x22222222;  // Pre-calculated timing
directConfig.CR2 = 0x11111111;  // Pre-calculated timing
 
// Pin assignments
directConfig.csPin = Pins[12];

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Member Data Documentation

clkPin

PinIO SEMC_cfg_t::clkPin

Clock output pin assignment (synchronous mode only)

csPin

PinIO SEMC_cfg_t::csPin

Chip select output pin assignment

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The documentation for this struct was generated from the following files:

• MIMXRT10xx/include/semc.h
• MIMXRT11xx/include/semc.h