Timing specifications for common SRAM speeds. More...

#include <semc_utils.h>

Public Attributes
uint32_t	address_access_time_ns
	tAA - Address to data valid
uint32_t	chip_enable_access_ns
	tACE - CE to data valid
uint32_t	output_enable_access_ns
	tOE - OE to data valid
uint32_t	write_cycle_time_ns
	tWC - Write cycle time
uint32_t	read_cycle_time_ns
	tRC - Read cycle time
uint32_t	address_setup_time_ns
	tAS - Address setup to WE
uint32_t	address_hold_time_ns
	tAH - Address hold from WE
uint32_t	chip_select_setup_ns
	tCS - CS setup time
uint32_t	write_pulse_width_ns
	tWP - WE pulse width
uint32_t	output_hold_time_ns
	tOH - Data hold after OE high

Detailed Description

Timing specifications for common SRAM speeds.

These structures contain typical timing values for different speed grades of asynchronous SRAM devices. Use these as starting points and adjust based on your specific device datasheet.

The documentation for this struct was generated from the following file:

semc_utils.h

Public Attributes

Detailed Description