DSPI for MCF5441x (MOD5441x, NANO, SB800EX) More...

Classes
struct	dspiDMAStruct
	DSPI DMA structure. More...

struct	dspiDriverStruct
	Major variables/configurations used for a DSPI transfer. More...

class	DSPIModule
	DSPIModule is a SPI communications driver. It is an object based driver, which allows for low overhead multiplexing between peripherals with different bus configurations. More...

Macros
#define	DEFAULT_DSPI_MODULE 1

#define	DSPI_MODULE_COUNT 4

Enumerations
enum	csReturnType { DEASSERT_NEVER = 0 , DEASSERT_AFTER_LAST = 1 , DEASSERT_EVERY_TRANSFER = 2 }
	Chip select return types. More...

enum	spiChipSelect { CHIP_SELECT_0 = 0xFE , CHIP_SELECT_1 = 0xFD , CHIP_SELECT_2 = 0xFB , CHIP_SELECT_3 = 0xF7 , CHIP_SELECT_DISABLED = 0xFF }
	Chip select number. More...

enum	spiChipSelectPolarity { CS_ASSERT_LOW = 0x00 , CS_ASSERT_HIGH = 0xFF }
	Chip select polarity. More...

Functions
uint8_t	DSPIInit (uint8_t SPIModule=DEFAULT_DSPI_MODULE, uint32_t Baudrate=2000000, uint8_t QueueBitSize=8, uint8_t CS=0x00, uint8_t CSPol=0x0F, uint8_t ClkPolarity=0, uint8_t ClkPhase=1, BOOL DoutHiz=TRUE, uint8_t QCD=0, uint8_t DTL=0)
	Initialize a DSPI module.

uint8_t	DSPIStart (uint8_t SPIModule, puint8_t transmitBufferPtr, volatile uint8_t receiveBufferPtr, uint32_t byteCount, OS_SEM finishedSem=NULL, uint8_t enableDMA=TRUE, int csReturnToInactive=DEASSERT_AFTER_LAST)
	Start DSPI Data Transfer.

BOOL	DSPIdone (uint8_t SPIModule=DEFAULT_DSPI_MODULE)
	Check current DSPI Data Transfer.

uint8_t	QSPIInit (uint32_t baudRateInBps=2000000, uint8_t transferSizeInBits=8, uint8_t peripheralChipSelects=0x0F, uint8_t chipSelectPolarity=1, uint8_t clockPolarity=0, uint8_t clockPhase=1, BOOL doutHiz=TRUE, uint8_t csToClockDelay=0, uint8_t delayAfterTransfer=0)
	Initialize Queued Serial Peripheral Interface (QSPI)

uint8_t	QSPIStart (puint8_t transmitBufferPtr, volatile uint8_t receiveBufferPtr, uint32_t byteCount, OS_SEM finishedSem=NULL)
	Start QSPI Data Transfer.

BOOL	QSPIdone ()
	Can be called after QSPIStart(). Returns TRUE when transfer is complete. This is an alternative to using a semaphore.

DSPI state

#define	DSPI_OK (0)

#define	DSPI_BUSY (1)

#define	DSPI_ERROR (2)

MCR Register masks
#define	MCR_MASTER_INIT 0x80000C01

#define	MCR_HALT_BIT 0x00000001

#define	MCR_DIS_TXF 0x00002000

#define	MCR_DIS_RXF 0x00001000

#define	MCR_CLR_FIFOS 0x00000C00

CTAR Register masks
#define	CTAR_CLOCK_POLARITY 0x04000000

#define	CTAR_CLOCK_PHASE 0x02000000

#define	CTAR_FRAME_16BIT 0x78000000

#define	CTAR_FRAME_4BIT 0x18000000

SR Register masks
#define	SR_EOQF_MASK 0x10000000

#define	SR_CLR_FLAGS 0x8A0A0000

RSER (Interrupt/DMA enable) Register masks
#define	RSER_EOQF_IRQ_ONLY ~0x8B0B0000

#define	RSER_DMA_IRQ_ONLY 0x03030000

PUSHR (command) Register masks
#define	PUSHR_CONT_BIT 0x80000000

#define	PUSHR_EOQ_BIT 0x08000000

DMA CHANNEL NUMBERS
#define	DMA_CH_DSPI_0_RX 0x0C
	(12)

#define	DMA_CH_DSPI_0_TX 0x0D
	(13)

#define	DMA_CH_DSPI_1_RX 0x0E
	(14)

#define	DMA_CH_DSPI_1_TX 0x0F
	(15)

#define	DMA_CH_DSPI_2_RX 0x1C
	(28)

#define	DMA_CH_DSPI_2_TX 0x1D
	(29)

#define	DMA_CH_DSPI_3_RX 0x2C
	(44)

#define	DMA_CH_DSPI_3_TX 0x2D
	(45)

EDMA CR Register masks
#define	CR_CLEAR_NON_GRP_PRIO ~0x000300FF

#define	CR_SET_RR_CH_ARB 0x00000004

EDMA TCD masks
#define	TCD_ATTR_8BIT_TRANS 0x0000

#define	TCD_ATTR_16BIT_TRANS 0x0101

#define	TCD_XOFF_0uint8_t 0x0000

#define	TCD_XOFF_1uint8_t 0x0001

#define	TCD_XOFF_2uint8_t 0x0002

#define	TCD_XITER_CNT_MASK 0x7FFF

#define	TCD_CSR_DONE_BIT 0x0080

#define	TCD_CSR_DISABLE_REQ 0xC008

#define	TCD_CSR_DREQ_INT_MAJOR 0xC00A

Detailed Description

DSPI for MCF5441x (MOD5441x, NANO, SB800EX)

Supported platforms:

MOD54415
MOD54417
NANO54415
SB800EX

The DMA serial peripheral interface (DSPI) interfaces (up to 3 depending on your platform) provide a synchronous serial bus for communication between the processor and an external peripheral device. DSPI interface modules are numbered from 0 to 3. DSPI 0 is reserved for system use. The DSPI supports up to 32 queued SPI transfers (16 receive and 16 transmit) in the DSPI resident FIFOs eliminating CPU intervention between transfers.

The DSPI specification allows for sharing the SPI bus with multiple devices. However, when designing your system, you must consider what devices are connected and the desired throughput. For example, if you are using the Embedded Flash File System (EFFS) with external Flash cards, or the WiFi module, they will require exclusive use of the DSPI interface.

The DSPI uses the following hardware signals:

SCLK Serial clock output from master.
MOSI Master data output (transmit), slave data input (receive).
MISO Master data input (receive), slave data output (transmit).
QSPI_CSn Optional QSPI chip selects. Note that you can also use GPIO signals and control them manually for the chip select functionality. In some cases, there are advantages to doinig it this way.

DSPI Configuration and Initialization
Use of the DSPI requires:

Identify which pins on your NetBurner device provide primary or secondary QSPI functionality. Use the NetBurner Pins class functions to configure these pins for QSPI operation.
Single task applications: you can choose to call the DSPIdone() function to determine when the DSPI transfer is complete, or use a semaphore and pend for completion.
Multi-task applications: If your application has more than one task that will access the same DSPI, you must create a semaphore to control access to the DSPI resource, just as you would with any shared resource.
Initialize the DSPI with the DSPIInit() function.
When you have data to send, or want to read data from the DSPI slave device, call the QSPIStart() function to initiate the data transfer.
The semaphore will post when the data transfer is complete.

Macro Definition Documentation

◆ CR_CLEAR_NON_GRP_PRIO

#define CR_CLEAR_NON_GRP_PRIO ~0x000300FF

#include <dspi.h>

◆ CR_SET_RR_CH_ARB

#define CR_SET_RR_CH_ARB 0x00000004

#include <dspi.h>

◆ CTAR_CLOCK_PHASE

#define CTAR_CLOCK_PHASE 0x02000000

#include <dspi.h>

◆ CTAR_CLOCK_POLARITY

#define CTAR_CLOCK_POLARITY 0x04000000

#include <dspi.h>

◆ CTAR_FRAME_16BIT

#define CTAR_FRAME_16BIT 0x78000000

#include <dspi.h>

◆ CTAR_FRAME_4BIT

#define CTAR_FRAME_4BIT 0x18000000

#include <dspi.h>

◆ DEFAULT_DSPI_MODULE

#define DEFAULT_DSPI_MODULE 1

#include <dspi.h>

◆ DSPI_BUSY

#define DSPI_BUSY (1)

#include <dspi.h>

◆ DSPI_ERROR

#define DSPI_ERROR (2)

#include <dspi.h>

◆ DSPI_MODULE_COUNT

#define DSPI_MODULE_COUNT 4

#include <dspi.h>

◆ DSPI_OK

#define DSPI_OK (0)

#include <dspi.h>

◆ MCR_CLR_FIFOS

#define MCR_CLR_FIFOS 0x00000C00

#include <dspi.h>

◆ MCR_DIS_RXF

#define MCR_DIS_RXF 0x00001000

#include <dspi.h>

◆ MCR_DIS_TXF

#define MCR_DIS_TXF 0x00002000

#include <dspi.h>

◆ MCR_HALT_BIT

#define MCR_HALT_BIT 0x00000001

#include <dspi.h>

◆ MCR_MASTER_INIT

#define MCR_MASTER_INIT 0x80000C01

#include <dspi.h>

◆ PUSHR_CONT_BIT

#define PUSHR_CONT_BIT 0x80000000

#include <dspi.h>

◆ PUSHR_EOQ_BIT

#define PUSHR_EOQ_BIT 0x08000000

#include <dspi.h>

◆ RSER_DMA_IRQ_ONLY

#define RSER_DMA_IRQ_ONLY 0x03030000

#include <dspi.h>

◆ RSER_EOQF_IRQ_ONLY

#define RSER_EOQF_IRQ_ONLY ~0x8B0B0000

#include <dspi.h>

◆ SR_CLR_FLAGS

#define SR_CLR_FLAGS 0x8A0A0000

#include <dspi.h>

◆ SR_EOQF_MASK

#define SR_EOQF_MASK 0x10000000

#include <dspi.h>

◆ TCD_ATTR_16BIT_TRANS

#define TCD_ATTR_16BIT_TRANS 0x0101

#include <dspi.h>

◆ TCD_ATTR_8BIT_TRANS

#define TCD_ATTR_8BIT_TRANS 0x0000

#include <dspi.h>

◆ TCD_CSR_DISABLE_REQ

#define TCD_CSR_DISABLE_REQ 0xC008

#include <dspi.h>

◆ TCD_CSR_DONE_BIT

#define TCD_CSR_DONE_BIT 0x0080

#include <dspi.h>

◆ TCD_CSR_DREQ_INT_MAJOR

#define TCD_CSR_DREQ_INT_MAJOR 0xC00A

#include <dspi.h>

◆ TCD_XITER_CNT_MASK

#define TCD_XITER_CNT_MASK 0x7FFF

#include <dspi.h>

◆ TCD_XOFF_0uint8_t

#define TCD_XOFF_0uint8_t 0x0000

#include <dspi.h>

◆ TCD_XOFF_1uint8_t

#define TCD_XOFF_1uint8_t 0x0001

#include <dspi.h>

◆ TCD_XOFF_2uint8_t

#define TCD_XOFF_2uint8_t 0x0002

#include <dspi.h>

Enumeration Type Documentation

◆ csReturnType

enum csReturnType

#include <dspi.h>

Chip select return types.

Chip select deassertion modes. Used to determine when the driver should deassert chip selects during SPI transfer.

Enumerator
DEASSERT_NEVER	The chip select used for the transaction should remain asserted, even after the transaction is complete.
DEASSERT_AFTER_LAST	The chip select should remain asserted for the full duration of the transaction, and only be deasserted after the final transfer.
DEASSERT_EVERY_TRANSFER	The chip select should be deasserted between every transfer within the transaction.

◆ spiChipSelect

enum spiChipSelect

#include <dspi.h>

Chip select number.

If supported by the SPI peripheral, these values can be used to configure the chip select to be used during a SPI transfer.

Enumerator
CHIP_SELECT_0	Configure bit mask for SPI chip select 0.
CHIP_SELECT_1	Configure bit mask for SPI chip select 1.
CHIP_SELECT_2	Configure bit mask for SPI chip select 2.
CHIP_SELECT_3	Configure bit mask for SPI chip select 3.
CHIP_SELECT_DISABLED	Configure bit mask to disable chip select.

◆ spiChipSelectPolarity

enum spiChipSelectPolarity

#include <dspi.h>

Chip select polarity.

These values can be used to configure the chip select's asserted/deasserted logic level. These values will configure all chip selects to the same configuration. If you intend on using an SPI peripheral with multiple chip selects with different polarities, these values cannot not be used.

Enumerator
CS_ASSERT_LOW	Bit mask configures all active chip selects as active low, inactive high.
CS_ASSERT_HIGH	Bit mask configures all active chip selects as inactive low, active high.

Function Documentation

◆ DSPIdone()

BOOL DSPIdone ( uint8_t SPIModule = DEFAULT_DSPI_MODULE )

#include <dspi.h>

Check current DSPI Data Transfer.

Parameters: None

Return: Progress of transfer - TRUE is finished, FALSE is active

Notes: None

◆ DSPIInit()

uint8_t DSPIInit	(	uint8_t	SPIModule = DEFAULT_DSPI_MODULE,
		uint32_t	Baudrate = 2000000,
		uint8_t	QueueBitSize = 8,
		uint8_t	CS = 0x00,
		uint8_t	CSPol = 0x0F,
		uint8_t	ClkPolarity = 0,
		uint8_t	ClkPhase = 1,
		BOOL	DoutHiz = TRUE,
		uint8_t	QCD = 0,
		uint8_t	DTL = 0 )

#include <dspi.h>

Initialize a DSPI module.

Notes:

The maximum baud rate is CPU_CLOCK / 3
Will initialize to the highest available baud rate that does not exceed the maximum
If configured for 8 bits per transfer then the data must be uint8_t aligned
If configured for greater than 8 bits per transfer then the data must be uint16_t aligned
If configured for greater than 16 bits per transfer then the data must be uint32_t aligned
Chip select is based on chipSelectPolarity
0 data captured leading edge of DSPI_CLK, changed following edge.
1 data changed leading edge of DSPI_CLK, captured following edge.
0 default is as close to 1/2 DSPI_CLK without going under, keeping with the interface to SPI
0 default is 17/(system clock / 2), in keeping with interface to QSPI

Parameters

SPIModule	SPI module number, 0 - 1
Baudrate	Maximum baud rate requested
QueueBitSize	Number of bits per transfer: 8, 16 or 32
CS	SPI chip selects to use for transfer
CSPol	0 = inactive logic level low, 1 = high
ClkPolarity	0 = inactive logic level low, 1 = high
ClkPhase	0 = data captured leading edge clock, changed following edge. 1 = data changed leading edge clock, captured following edge.
DoutHiz	Data output high impedance between transfers
QCD	Delay from chip select to valid clock (default is 0). QCD is a value in the QDLYR register and will change the delay between the assertion of the chip select and the start of the DSPI clock. Default setting of one half DSPI clk will be used if parameter is specified as 0x0 or not included.
DTL	DTL is a value in the QDLYR register and will change the delay following a tranfer of a single uint16_t in the DSPI queue. Default reset value of 17/(fsys/2) will be used if parameter is specified 0 or not included.

Returns: Current stat of DSPI bus MOD5441xDspiStates

◆ DSPIStart()

uint8_t DSPIStart	(	uint8_t	SPIModule,
		puint8_t	transmitBufferPtr,
		volatile uint8_t *	receiveBufferPtr,
		uint32_t	byteCount,
		OS_SEM *	finishedSem = NULL,
		uint8_t	enableDMA = TRUE,
		int	csReturnToInactive = DEASSERT_AFTER_LAST )

#include <dspi.h>

Start DSPI Data Transfer.

Parameters:
    transmitBufferPtr   - Buffer with data to send, NULL for receiving
    receiveBufferPtr    - Buffer to receive data, NULL for sending
    byteCount           - Count of bytes to send or receive
    SPIModule           - Selects the dspi module to use
    finishedSem         - Optional semaphore to set when completed

Return:
    Current DSPI state  - DSPI_OK success or DSPI_BUSY busy

Notes:
    None

                                                                      -

◆ QSPIdone()

BOOL QSPIdone ( void )

inline

#include <dspi.h>

Can be called after QSPIStart(). Returns TRUE when transfer is complete. This is an alternative to using a semaphore.

Return values

TRUE	When transfer is complete
FALSE	On error

See also: QSPIInit(); QSPIStart()

◆ QSPIInit()

uint8_t QSPIInit	(	uint32_t	baudRateInBps = 2000000,
		uint8_t	transferSizeInBits = 8,
		uint8_t	peripheralChipSelects = 0x0F,
		uint8_t	chipSelectPolarity = 1,
		uint8_t	clockPolarity = 0,
		uint8_t	clockPhase = 1,
		BOOL	doutHiz = TRUE,
		uint8_t	csToClockDelay = 0,
		uint8_t	delayAfterTransfer = 0 )

inline

#include <dspi.h>

Initialize Queued Serial Peripheral Interface (QSPI)

Notes: (3) Transfers > 8 must be word aligned (4) Select based on chipSelectPolarity (5) 0 data captured leading edge of QSPI_CLK, changed following edge. (6) 1 data changed leading edge of QSPI_CLK, captured following edge. (7) 0 default is 1/2 QSPI_CLK or see MFCXXXX reference manual (8) 0 default is 8192/(system clock / 2) see MFCXXXX reference manual

Parameters

baudRateInBps	Maximum requested baud rate in bits per second. The maximum possible baud rate is determined by the system clock. The function will select the highest possible baud rate if the specified value cannot be achieved.
transferSizeInBits	Size of data values to be transferred. Values can be 8, 16 or 32 bits. Note that 16 and 32 bit size values must be word (16-bit) aligned (16-bit).
peripheralChipSelects	Peripheral chip select drive level. Used to select an external device for serial data transfer. More than one chip select may be active at once, and more than one device can be connected to each chip select. Bits 3-0 map directly to QSPI_CS[3:0], respectively. For each bit: 0 = Chip select is 0 during a transfer. 1 = Chip select is 1 during a transfer.
chipSelectPolarity	Peripheral chip select inactive level (no transfer in progress). Applies to all chip selects. 0 = 0 when inactive 1 = 1 when inactive
clockPolarity	Clock polarity: 0 = The inactive state value of QSPI_CLK is logic level 0. 1 = The inactive state value of QSPI_CLK is logic level 1.
clockPhase	Clock phase: 0 = Data captured on the leading edge of QSPI_CLK and changed on the following edge of QSPI_CLK. 1 = Data changed on the leading edge of QSPI_CLK and captured on the following edge of QSPI_CLK.
doutHiz	Data output high impedance enable. Selects QSPI_DOUT mode of operation. 0 = Default value after reset. QSPI_DOUT is actively driven between transfers. 1 = QSPI_DOUT is high impedance between transfers.
csToClockDelay	QCD, QSPICLK delay. When the DSCK bit in the command RAM is set this field determines the length of the delay from assertion of the chip selects to valid QSPI_CLK transition.
delayAfterTransfer	Delay after transfer. When the DT bit in the command RAM is set this field determines the length of delay after the serial transfer.

Returns: groupQspiState

See also: QSPIInit(); QSPIStart()

◆ QSPIStart()

uint8_t QSPIStart	(	puint8_t	transmitBufferPtr,
		volatile uint8_t *	receiveBufferPtr,
		uint32_t	byteCount,
		OS_SEM *	finishedSem = NULL )

inline

#include <dspi.h>

Start QSPI Data Transfer.

Parameters

transmitBufferPtr	Pointer to the buffer to use in the transfer. Specify NULL for receive only.
receiveBufferPtr	Pointer to buffer to store received data. NULL for transmit only.
byteCount	Number of bytes to send or receive. If the data size is greater than 8-bit, you must provide the total number of bytes.
finishedSem	Pointer to preinitialized semaphore to post to when transfer is complete. A value of NULL disables the semaphore function.

Returns: groupQspiState

See also: QSPIInit(); QSPIdone()

Classes

Macros

Enumerations

Functions

DSPI state

MCR Register masks

CTAR Register masks

SR Register masks

RSER (Interrupt/DMA enable) Register masks

PUSHR (command) Register masks

DMA CHANNEL NUMBERS

EDMA CR Register masks

EDMA TCD masks

Detailed Description

Macro Definition Documentation

◆ CR_CLEAR_NON_GRP_PRIO

◆ CR_SET_RR_CH_ARB

◆ CTAR_CLOCK_PHASE

◆ CTAR_CLOCK_POLARITY

◆ CTAR_FRAME_16BIT

◆ CTAR_FRAME_4BIT

◆ DEFAULT_DSPI_MODULE

◆ DSPI_BUSY

◆ DSPI_ERROR

◆ DSPI_MODULE_COUNT

◆ DSPI_OK

◆ MCR_CLR_FIFOS

◆ MCR_DIS_RXF

◆ MCR_DIS_TXF

◆ MCR_HALT_BIT

◆ MCR_MASTER_INIT

◆ PUSHR_CONT_BIT

◆ PUSHR_EOQ_BIT

◆ RSER_DMA_IRQ_ONLY

◆ RSER_EOQF_IRQ_ONLY

◆ SR_CLR_FLAGS

◆ SR_EOQF_MASK

◆ TCD_ATTR_16BIT_TRANS

◆ TCD_ATTR_8BIT_TRANS

◆ TCD_CSR_DISABLE_REQ

◆ TCD_CSR_DONE_BIT

◆ TCD_CSR_DREQ_INT_MAJOR

◆ TCD_XITER_CNT_MASK

◆ TCD_XOFF_0uint8_t

◆ TCD_XOFF_1uint8_t

◆ TCD_XOFF_2uint8_t

Enumeration Type Documentation

◆ csReturnType

◆ spiChipSelect

◆ spiChipSelectPolarity

Function Documentation

◆ DSPIdone()

◆ DSPIInit()

◆ DSPIStart()

◆ QSPIdone()

◆ QSPIInit()

◆ QSPIStart()