EBI - External Bus Interface

Classes
struct	EBI_CS_cfg_t
	Configuration structure for an External Bus Interface (EBI) chip select. More...

Enumerations
enum	EBI_CS_BusWidth_t { EBI_BUS_WIDTH_8 = 0 , EBI_BUS_WIDTH_16 = 1 }
	Data bus width configuration for External Bus Interface. More...
enum	EBI_CS_ByteAccess_t { EBI_BYTE_ACCESS_SELECT = 0 , EBI_BYTE_ACCESS_WRITE = 1 }
	Byte access mode for 16-bit bus configurations. More...
enum	EBI_CS_NWait_t { EBI_NWAIT_DISABLED = 0 , EBI_NWAIT_FROZEN = 2 , EBI_NWAIT_READY = 3 }
	NWAIT signal configuration for bus cycle extension. More...
enum	EBI_CS_WrMode_t { EBI_WRITE_MODE_NCS = 0 , EBI_WRITE_MODE_NWE = 1 }
	Write control signal selection. More...
enum	EBI_CS_RdMode_t { EBI_READ_MODE_NCS = 0 , EBI_READ_MODE_NRD = 1 }
	Read control signal selection. More...

Functions
void	ConfigureEBI_CSPin (int csNum)
	Configure the I/O pin for a given Chip Select for the external data bus.
void	ConfigureEBI_NWRPin ()
	Configure the I/O pin for the active low write/read (NWR) bus signal.
void	ConfigureEBI_NRDPin ()
	Configure the I/O pin for the active low read (NRD) bus signal.
void	ConfigureEBI_CS (uint32_t csNum, const EBI_CS_cfg_t &&cfg)
	Configure the given Chip Select for the external data bus (rvalue reference version).
void	ConfigureEBI_CS (uint32_t csNum, const EBI_CS_cfg_t &cfg)
	Configure the given Chip Select for the external data bus (lvalue reference version).

Variables
uint8_t	EBI_CS_cfg_t::ncs_rd_setup
uint8_t	EBI_CS_cfg_t::nrd_setup
uint8_t	EBI_CS_cfg_t::ncs_wr_setup
uint8_t	EBI_CS_cfg_t::nwe_setup
uint8_t	EBI_CS_cfg_t::ncs_rd_pulse
uint8_t	EBI_CS_cfg_t::nrd_pulse
uint8_t	EBI_CS_cfg_t::ncs_wr_pulse
uint8_t	EBI_CS_cfg_t::nwe_pulse
uint16_t	EBI_CS_cfg_t::nrd_cycles
uint16_t	EBI_CS_cfg_t::nwe_cycles
uint8_t	EBI_CS_cfg_t::tdf_cycles
EBI_CS_BusWidth_t	EBI_CS_cfg_t::busWidth
EBI_CS_ByteAccess_t	EBI_CS_cfg_t::byteAccess
EBI_CS_NWait_t	EBI_CS_cfg_t::nWait
EBI_CS_WrMode_t	EBI_CS_cfg_t::wrMode
EBI_CS_RdMode_t	EBI_CS_cfg_t::rdMode

Detailed Description

Supported Platforms: MODM7AE70

The Microchip SAME70 EBI peripheral is a parallel communication port that can only operate in "host" mode to communicate with "slave" devices. The EBI peripheral consists of a set of up to 16 data signals, up to 24 address signals and up to 10 different control signals. Some of the benefits of using the EBI bus are that it has high performance in both throughput and latency. It is directly memory mapped to the processor so it is very easy to use in software once configured. The downsides are mostly that it has many signals which will greatly complicate hardware designs and increase the size of external peripheral chips.
The EBI peripheral is highly configurable to fit the specifications of many types of external devices.
A consequence to this high configurablity is that there are many timing parameters which makes configuration
complicated. The NetBurner examples specify a conservative set of timing parameters with the goal of being compatible with a wide range of peripherals such as FPGAs, CPLDs, buffers, latches displays, flash memory and SRAM. Once successful communication is obtained with the slave target device, these default settings should be refined to increase the performance to match the device you are interfacing with.

Advanced EBI functionality is currently not supported by this examples or this driver. Advaced functionality includes interfacing with SDRAM or NAND memories. Page mode, burst operations and scrambling functionality are all not currently configurable via this driver.

In most applications you will only need to verify the last 5 parameters meet your peripheral requirements: bus width (8 or 16), byte Access 16-bit mode only), timing parameters, read mode (chip select or read signal) and write mode (chip select or write signal).

There are 3 sources of information that are very useful for understanding the EBI:

1. The EBI section of the Microchip SAME70 manual located in "\nburn\docs". It is very important to do this as the first step to understand the signal terminology in the examples and header files. Additionally the Static Memory Controller chapter in this processor manual is essential as it explains all the settings and timing parameters exposed by this driver.
2. The NetBurner EBI examples described in the manual and located in "\nburn\examples\PlatformSpecific\MODM7AE70"
3. The SAME70 ebi.h header file located in "\nburn\arch\cortex-m7\cpu\SAME70\include"

The EBI supports Chip Selects as well as Read and Write signals to interface with peripherals. The basic procedure for configuring the bus is:

• As noted in the examples, the MODM7AE70 has onboard bus buffers to reduce noise and help signal integrity. The following 4 signals must always be configured for EBI functionality as they are control the enable/disable and direction control of the bus buffer ICs:

  P1[5].function(PINP1_5_NCS2);      // chip select 2, active low
  P1[6].function(PINP1_6_NCS0);      // chip select 0, active low
  P1[7].function(PINP1_7_NCS3);      // chip select 3, active low
  P1[8].function(PINP1_8_NRD);       // Bus read, active low

• Declare a Configuration Structure of type EBI_CS_cfg_t. An easy way is to copy one from the examples. Then modify any parameters necessary to meet your specific peripheral requirements, such as bus width, byte access in 16-bit mode, timing parameters, etc.

• Configure the desired chip select using the ConfigureEBI_CS()function. Note that when enabling the EBI, the MODM7AE70 module requires all three chip selects (NCS0, NCS02, NCS03) to be assigned as chip selects. Addtionally the NRD signal must also be configured for NRD bus operation. All of these signals are used for controlling the enable/direction logic of the external bus buffer hardware - they cannot use their alternate functions. Each chip select has a predefined fixed 16MB address range ( MODM7AE70 Memory Map). The NetBurner API supplied predefined base address variables to make access easier as demonstrated in the EBI examples:

  extern volatile uint8_t ebi_0_base[];  // Chip select 0
  extern volatile uint8_t ebi_1_base[];  // Chip select 1
  extern volatile uint8_t ebi_2_base[];  // Chip select 2
  extern volatile uint8_t ebi_3_base[];  // Chip select 3

  In this way you can do a bus write with code such as (please refer to EBI examples for latest code):

  const uint8_t  EBITestData8 = 0x5A;                    // Data byte for testing
  const uint32_t EBITestAddressOffset = 0xA5A5;          // Address offset from chip select base address
   
  ebi_0_base[EBITestAddressOffset] = EBITestData8;       // Write data to EBI, chip select 0
  ebi_0_base[0xA5A5] = 0X5A;                             // Same write with hard coded values
   
  uint32_t EBIdata = ebi_0_base[EBITestAddressOffset];   // Read data from EBI, chip select 0

Warning

When enabling the EBI for the MODM7AE70 module, NCS0, NCS2, NCS3 and NRD must all be configured for their bus functionality as chip selects or nRead signals, even if not used by your application - they cannot be assigned their alternate functions. Additionally the "void EnableExtBusBuff(bool enable);" function from bsp.h must be used to enable the external bus buffer hardware.

Enumeration Type Documentation

EBI_CS_BusWidth_t

enum EBI_CS_BusWidth_t

#include <ebi.h>

Data bus width configuration for External Bus Interface.

Specifies the data bus width for communication with external devices on the EBI. The bus width must match the physical connection and capabilities of the external device connected to the chip select.

Note

The bus width setting affects how data is transferred and accessed on the external bus. Ensure the external device supports the selected width.

See also

EBI_CS_ByteAccess_t

Enumerator
EBI_BUS_WIDTH_8	8-bit data bus width (D0-D7)
EBI_BUS_WIDTH_16	16-bit data bus width (D0-D15)

EBI_CS_ByteAccess_t

enum EBI_CS_ByteAccess_t

#include <ebi.h>

Byte access mode for 16-bit bus configurations.

Controls how 8-bit accesses are handled when the bus is configured for 16-bit mode. This setting determines which control signal (chip select or write enable) is used to select the high or low byte during 8-bit transfers on a 16-bit bus.

Note

This setting is only relevant when using EBI_BUS_WIDTH_16. It has no effect in 8-bit bus mode.

Warning

Incorrect byte access configuration can result in data corruption when performing byte-level operations on a 16-bit bus.

See also

EBI_CS_BusWidth_t

---

Expand for Example Usage

Examples

Example 1: Configuring byte access using chip select

void ConfigureEBI_16BitWithByteAccess() {
    EBI_CS_BusWidth_t busWidth = EBI_BUS_WIDTH_16;
    EBI_CS_ByteAccess_t byteAccess = EBI_BYTE_ACCESS_SELECT;
    
    // Configure for 16-bit bus with CS-controlled byte access
    // This allows upper/lower byte selection via chip select
    
    iprintf("16-bit bus configured with CS byte select\r\n");
}

Example 2: Configuring byte access using write signal

void ConfigureEBI_16BitWithWriteByteAccess() {
    EBI_CS_BusWidth_t busWidth = EBI_BUS_WIDTH_16;
    EBI_CS_ByteAccess_t byteAccess = EBI_BYTE_ACCESS_WRITE;
    
    // Configure for 16-bit bus with write-controlled byte access
    // This uses the write signal to select upper/lower byte
    
    iprintf("16-bit bus configured with write signal byte select\r\n");
}

---

Enumerator
EBI_BYTE_ACCESS_SELECT	Use chip select signal to access individual bytes on 16-bit bus.
EBI_BYTE_ACCESS_WRITE	Use write enable signal to access individual bytes on 16-bit bus.

EBI_CS_NWait_t

enum EBI_CS_NWait_t

#include <ebi.h>

NWAIT signal configuration for bus cycle extension.

Controls how the external NWAIT signal is used to extend read/write cycles when interfacing with slow external devices. The NWAIT signal allows external devices to insert wait states, extending the access time as needed.

This is commonly used with:

• Slow flash memory devices
• Variable-speed peripherals
• Devices that need dynamic timing adjustment

Note

When disabled, the NWAIT signal is ignored and all timing is determined by the configured setup, pulse, and hold times.

In Frozen mode, the NWAIT signal can extend the access time indefinitely while the signal is asserted.

In Ready mode, the NWAIT signal is sampled and can control cycle extension based on device readiness.

Warning

Using NWAIT modes with devices that don't properly drive the NWAIT signal can result in bus hangs or indefinite waits.

---

Expand for Example Usage

Examples

Example 1: Disabled NWAIT for fast SRAM

void ConfigureFastSRAM() {
    EBI_CS_NWait_t nwaitMode = EBI_NWAIT_DISABLED;
    
    // Fast SRAM doesn't need wait states
    // All timing controlled by setup/pulse/hold registers
    
    iprintf("EBI configured for fast SRAM (NWAIT disabled)\r\n");
}

Example 2: Frozen mode for slow flash memory

void ConfigureSlowFlash() {
    EBI_CS_NWait_t nwaitMode = EBI_NWAIT_FROZEN;
    
    // Flash can extend cycles as needed via NWAIT
    // Useful for write operations that need variable time
    
    iprintf("EBI configured for flash with frozen NWAIT mode\r\n");
}

Example 3: Ready mode for variable-speed peripheral

void ConfigureVariableSpeedDevice() {
    EBI_CS_NWait_t nwaitMode = EBI_NWAIT_READY;
    
    // Device can signal when it's ready via NWAIT
    // Allows dynamic timing based on device state
    
    iprintf("EBI configured with ready mode NWAIT\r\n");
}

Example 4: Comparing NWAIT modes for different device types

void ConfigureMultipleDevices() {
    // CS0: Fast SRAM - no wait states needed
    EBI_CS_NWait_t cs0_nwait = EBI_NWAIT_DISABLED;
    
    // CS1: Flash memory - can hold bus during programming
    EBI_CS_NWait_t cs1_nwait = EBI_NWAIT_FROZEN;
    
    // CS2: Variable speed FPGA - signals readiness
    EBI_CS_NWait_t cs2_nwait = EBI_NWAIT_READY;
    
    iprintf("Configured 3 devices with different NWAIT modes\r\n");
}

---

Enumerator
EBI_NWAIT_DISABLED	NWAIT signal ignored, all timing from configuration registers.
EBI_NWAIT_FROZEN	NWAIT can freeze/extend the access cycle indefinitely.
EBI_NWAIT_READY	NWAIT sampled to determine device ready state.

EBI_CS_RdMode_t

enum EBI_CS_RdMode_t

#include <ebi.h>

Read control signal selection.

Determines which signal controls read operations from external devices on the EBI. This setting affects how read cycles are generated and controlled.

• NCS mode: Read cycle controlled by chip select assertion
• NRD mode: Read cycle controlled by dedicated read enable signal

Note

NRD (Read Enable) mode provides more precise read timing control and is commonly used with memory devices that have separate read enable inputs.

NCS mode may be suitable for simpler devices or when minimizing control signal requirements.

See also

EBI_CS_WrMode_t

ConfigureEBI_NRDPin()

---

Expand for Example Usage

Examples

Example 1: Using NRD for standard SRAM

void ConfigureSRAM_WithReadEnable() {
    EBI_CS_RdMode_t readMode = EBI_READ_MODE_NRD;
    
    // Standard SRAM with dedicated OE/RD pin
    // Provides precise read pulse timing
    ConfigureEBI_NRDPin();  // Configure the read enable pin
    
    iprintf("SRAM configured with NRD read control\r\n");
}

Example 2: Using NCS for simple peripheral

void ConfigureSimpleReadDevice() {
    EBI_CS_RdMode_t readMode = EBI_READ_MODE_NCS;
    
    // Simple device controlled only by chip select
    // Data output when CS is asserted
    
    iprintf("Device configured with NCS read control\r\n");
}

Example 3: Complete read/write configuration

void ConfigureExternalMemory() {
    EBI_CS_WrMode_t writeMode = EBI_WRITE_MODE_NWE;
    EBI_CS_RdMode_t readMode = EBI_READ_MODE_NRD;
    
    // Configure pins for read and write operations
    ConfigureEBI_NWRPin();
    ConfigureEBI_NRDPin();
    
    iprintf("Memory configured with NRD/NWE control signals\r\n");
}

Example 4: Mixed control modes for different chip selects

void ConfigureMixedDevices() {
    // CS0: Memory with dedicated control signals
    EBI_CS_RdMode_t cs0_read = EBI_READ_MODE_NRD;
    EBI_CS_WrMode_t cs0_write = EBI_WRITE_MODE_NWE;
    
    // CS1: Simple I/O using only chip select
    EBI_CS_RdMode_t cs1_read = EBI_READ_MODE_NCS;
    EBI_CS_WrMode_t cs1_write = EBI_WRITE_MODE_NCS;
    
    ConfigureEBI_NWRPin();
    ConfigureEBI_NRDPin();
    
    iprintf("CS0: Full control signals (NRD/NWE)\r\n");
    iprintf("CS1: Chip select only (NCS)\r\n");
}

---

Enumerator
EBI_READ_MODE_NCS	Read controlled by chip select (NCS) assertion.
EBI_READ_MODE_NRD	Read controlled by read enable (NRD) signal.

EBI_CS_WrMode_t

enum EBI_CS_WrMode_t

#include <ebi.h>

Write control signal selection.

Determines which signal controls write operations to external devices on the EBI. This setting affects how write cycles are generated and controlled.

• NCS mode: Write cycle controlled by chip select assertion
• NWE mode: Write cycle controlled by dedicated write enable signal

Note

NWE (Write Enable) mode provides more precise write timing control and is commonly used with memory devices that have separate write enable inputs.

NCS mode may be suitable for simpler devices or when minimizing control signal requirements.

See also

EBI_CS_RdMode_t

ConfigureEBI_NWRPin()

---

Expand for Example Usage

Examples

Example 1: Using NWE for standard SRAM

void ConfigureSRAM_WithWriteEnable() {
    EBI_CS_WrMode_t writeMode = EBI_WRITE_MODE_NWE;
    
    // Standard SRAM with dedicated WE pin
    // Provides precise write pulse timing
    ConfigureEBI_NWRPin();  // Configure the write enable pin
    
    iprintf("SRAM configured with NWE write control\r\n");
}

Example 2: Using NCS for simple peripheral

void ConfigureSimplePeripheral() {
    EBI_CS_WrMode_t writeMode = EBI_WRITE_MODE_NCS;
    
    // Simple device controlled only by chip select
    // Write occurs when CS is asserted
    
    iprintf("Peripheral configured with NCS write control\r\n");
}

Example 3: Comparing write modes for different devices

void ConfigureMultipleDeviceWrites() {
    // Memory device: use dedicated write enable
    EBI_CS_WrMode_t sram_write = EBI_WRITE_MODE_NWE;
    
    // Simple I/O device: use chip select
    EBI_CS_WrMode_t io_write = EBI_WRITE_MODE_NCS;
    
    iprintf("CS0: NWE mode for memory\r\n");
    iprintf("CS1: NCS mode for I/O\r\n");
}

---

Enumerator
EBI_WRITE_MODE_NCS	Write controlled by chip select (NCS) assertion.
EBI_WRITE_MODE_NWE	Write controlled by write enable (NWE) signal.

Function Documentation

ConfigureEBI_CS() [1/2]

void ConfigureEBI_CS	(	uint32_t	csNum,
		const EBI_CS_cfg_t &&	cfg )

#include <ebi.h>

Configure the given Chip Select for the external data bus (rvalue reference version).

Configures an External Bus Interface (EBI) chip select with the specified timing and control parameters. This overload accepts an rvalue reference, allowing efficient configuration with temporary configuration objects.

This function sets up all timing parameters (setup, pulse, hold times), control signal modes, bus width, and wait state configuration for the specified chip select line.

Parameters

csNum	The EBI Chip Select number to configure (typically 0-3, platform-dependent).
cfg	Rvalue reference to the configuration structure. The configuration is moved into the function, making this efficient for temporary configuration objects.

Note

This function should be called after pin configuration functions:

• ConfigureEBI_CSPin()
• ConfigureEBI_NWRPin() (if using write operations)
• ConfigureEBI_NRDPin() (if using read operations)

All timing parameters in the configuration are specified in EBI clock cycles. Calculate the required values based on your EBI clock frequency and device datasheet.

Warning

Incorrect timing configuration can cause data corruption or device malfunction. Always verify timing parameters against the external device datasheet.

Ensure the chip select number is valid for your platform. Invalid values may result in undefined behavior.

See also

ConfigureEBI_CS(uint32_t, const EBI_CS_cfg_t&)

ConfigureEBI_CSPin()

EBI_CS_cfg_t

---

Expand for Example Usage

Examples

Example 1: Configure CS0 with temporary configuration object

void InitializeExternalSRAM() {
    // Configure the chip select pin first
    ConfigureEBI_CSPin(0);
    ConfigureEBI_NWRPin();
    ConfigureEBI_NRDPin();
    
    // Configure CS0 using temporary configuration (rvalue)
    // This overload is efficient when creating config inline
    ConfigureEBI_CS(0, EBI_CS_cfg_t{
        .ncs_rd_setup = 2,
        .nrd_setup = 2,
        .ncs_rd_pulse = 10,
        .nrd_pulse = 10,
        .nrd_cycles = 15,
        .ncs_wr_setup = 2,
        .nwe_setup = 2,
        .ncs_wr_pulse = 10,
        .nwe_pulse = 10,
        .nwe_cycles = 15,
        .tdf_cycles = 2,
        .busWidth = EBI_BUS_WIDTH_16,
        .byteAccess = EBI_BYTE_ACCESS_WRITE,
        .nWait = EBI_NWAIT_DISABLED,
        .wrMode = EBI_WRITE_MODE_NWE,
        .rdMode = EBI_READ_MODE_NRD
    });
    
    iprintf("CS0 configured for SRAM\r\n");
}

Example 2: Using a factory function that returns configuration

EBI_CS_cfg_t CreateFastSRAMConfig() {
    return EBI_CS_cfg_t{
        .ncs_rd_setup = 2, .nrd_setup = 2,
        .ncs_rd_pulse = 10, .nrd_pulse = 10,
        .nrd_cycles = 15,
        .ncs_wr_setup = 2, .nwe_setup = 2,
        .ncs_wr_pulse = 10, .nwe_pulse = 10,
        .nwe_cycles = 15,
        .tdf_cycles = 2,
        .busWidth = EBI_BUS_WIDTH_16,
        .byteAccess = EBI_BYTE_ACCESS_WRITE,
        .nWait = EBI_NWAIT_DISABLED,
        .wrMode = EBI_WRITE_MODE_NWE,
        .rdMode = EBI_READ_MODE_NRD
    };
}
 
void UserMain(void *pd) {
    init();
    
    ConfigureEBI_CSPin(0);
    ConfigureEBI_NWRPin();
    ConfigureEBI_NRDPin();
    
    // Rvalue overload called with returned temporary
    ConfigureEBI_CS(0, CreateFastSRAMConfig());
    
    iprintf("CS0 configured using factory function\r\n");
    
    while(1) {
        OSTimeDly(TICKS_PER_SECOND);
    }
}

Example 3: Chain configuration with std::move

void ConfigureMultipleChipSelects() {
    ConfigureEBI_CSPin(0);
    ConfigureEBI_CSPin(1);
    ConfigureEBI_NWRPin();
    ConfigureEBI_NRDPin();
    
    EBI_CS_cfg_t baseConfig = {
        .ncs_rd_setup = 2, .nrd_setup = 2,
        .ncs_rd_pulse = 10, .nrd_pulse = 10,
        .nrd_cycles = 15,
        .ncs_wr_setup = 2, .nwe_setup = 2,
        .ncs_wr_pulse = 10, .nwe_pulse = 10,
        .nwe_cycles = 15,
        .tdf_cycles = 2,
        .busWidth = EBI_BUS_WIDTH_16,
        .byteAccess = EBI_BYTE_ACCESS_WRITE,
        .nWait = EBI_NWAIT_DISABLED,
        .wrMode = EBI_WRITE_MODE_NWE,
        .rdMode = EBI_READ_MODE_NRD
    };
    
    // Configure CS0 with the base config
    ConfigureEBI_CS(0, baseConfig);  // Uses lvalue overload
    
    // Modify for CS1 (slower device)
    baseConfig.nrd_cycles = 20;
    baseConfig.nwe_cycles = 20;
    
    // Move to CS1 configuration
    ConfigureEBI_CS(1, std::move(baseConfig));  // Uses rvalue overload
    
    iprintf("CS0 and CS1 configured\r\n");
}

---

ConfigureEBI_CS() [2/2]

void ConfigureEBI_CS	(	uint32_t	csNum,
		const EBI_CS_cfg_t &	cfg )

#include <ebi.h>

Configure the given Chip Select for the external data bus (lvalue reference version).

Configures an External Bus Interface (EBI) chip select with the specified timing and control parameters. This overload accepts an lvalue reference, allowing configuration with existing configuration objects that may be reused.

This function sets up all timing parameters (setup, pulse, hold times), control signal modes, bus width, and wait state configuration for the specified chip select line.

Parameters

csNum	The EBI Chip Select number to configure (typically 0-3, platform-dependent).
cfg	Const reference to the configuration structure. The configuration is copied, allowing the original to be reused for other chip selects.

Note

This function should be called after pin configuration functions:

• ConfigureEBI_CSPin()
• ConfigureEBI_NWRPin() (if using write operations)
• ConfigureEBI_NRDPin() (if using read operations)

All timing parameters in the configuration are specified in EBI clock cycles. Calculate the required values based on your EBI clock frequency and device datasheet.

Warning

Incorrect timing configuration can cause data corruption or device malfunction. Always verify timing parameters against the external device datasheet.

Ensure the chip select number is valid for your platform. Invalid values may result in undefined behavior.

See also

ConfigureEBI_CS(uint32_t, const EBI_CS_cfg_t&&)

ConfigureEBI_CSPin()

EBI_CS_cfg_t

---

Expand for Example Usage

Examples

Example 1: Basic CS configuration with persistent config object

void InitializeExternalMemory() {
    // Configure the necessary pins
    ConfigureEBI_CSPin(0);
    ConfigureEBI_NWRPin();
    ConfigureEBI_NRDPin();
    
    // Create configuration object
    EBI_CS_cfg_t sramConfig = {
        .ncs_rd_setup = 2,
        .nrd_setup = 2,
        .ncs_rd_pulse = 10,
        .nrd_pulse = 10,
        .nrd_cycles = 15,
        .ncs_wr_setup = 2,
        .nwe_setup = 2,
        .ncs_wr_pulse = 10,
        .nwe_pulse = 10,
        .nwe_cycles = 15,
        .tdf_cycles = 2,
        .busWidth = EBI_BUS_WIDTH_16,
        .byteAccess = EBI_BYTE_ACCESS_WRITE,
        .nWait = EBI_NWAIT_DISABLED,
        .wrMode = EBI_WRITE_MODE_NWE,
        .rdMode = EBI_READ_MODE_NRD
    };
    
    // Configure CS0 using lvalue reference
    ConfigureEBI_CS(0, sramConfig);
    
    iprintf("CS0 configured for SRAM\r\n");
}

Example 2: Reusing configuration for multiple chip selects

void ConfigureMultipleSimilarDevices() {
    // Configure pins for all chip selects
    ConfigureEBI_CSPin(0);
    ConfigureEBI_CSPin(1);
    ConfigureEBI_CSPin(2);
    ConfigureEBI_NWRPin();
    ConfigureEBI_NRDPin();
    
    // Base configuration for similar devices
    EBI_CS_cfg_t baseConfig = {
        .ncs_rd_setup = 2, .nrd_setup = 2,
        .ncs_rd_pulse = 10, .nrd_pulse = 10,
        .nrd_cycles = 15,
        .ncs_wr_setup = 2, .nwe_setup = 2,
        .ncs_wr_pulse = 10, .nwe_pulse = 10,
        .nwe_cycles = 15,
        .tdf_cycles = 2,
        .busWidth = EBI_BUS_WIDTH_16,
        .byteAccess = EBI_BYTE_ACCESS_WRITE,
        .nWait = EBI_NWAIT_DISABLED,
        .wrMode = EBI_WRITE_MODE_NWE,
        .rdMode = EBI_READ_MODE_NRD
    };
    
    // Configure multiple chip selects with same timing
    ConfigureEBI_CS(0, baseConfig);  // Config object still valid
    ConfigureEBI_CS(1, baseConfig);  // Reused for CS1
    ConfigureEBI_CS(2, baseConfig);  // Reused for CS2
    
    iprintf("CS0, CS1, CS2 configured with identical timing\r\n");
}

Example 3: Configuration with device-specific variations

void ConfigureMixedDevices() {
    ConfigureEBI_CSPin(0);
    ConfigureEBI_CSPin(1);
    ConfigureEBI_NWRPin();
    ConfigureEBI_NRDPin();
    
    // Fast SRAM on CS0
    EBI_CS_cfg_t fastConfig = {
        .ncs_rd_setup = 2, .nrd_setup = 2,
        .ncs_rd_pulse = 10, .nrd_pulse = 10,
        .nrd_cycles = 15,
        .ncs_wr_setup = 2, .nwe_setup = 2,
        .ncs_wr_pulse = 10, .nwe_pulse = 10,
        .nwe_cycles = 15,
        .tdf_cycles = 2,
        .busWidth = EBI_BUS_WIDTH_16,
        .byteAccess = EBI_BYTE_ACCESS_WRITE,
        .nWait = EBI_NWAIT_DISABLED,
        .wrMode = EBI_WRITE_MODE_NWE,
        .rdMode = EBI_READ_MODE_NRD
    };
    
    // Slow flash on CS1
    EBI_CS_cfg_t slowConfig = {
        .ncs_rd_setup = 3, .nrd_setup = 3,
        .ncs_rd_pulse = 15, .nrd_pulse = 15,
        .nrd_cycles = 22,
        .ncs_wr_setup = 3, .nwe_setup = 3,
        .ncs_wr_pulse = 20, .nwe_pulse = 20,
        .nwe_cycles = 28,
        .tdf_cycles = 3,
        .busWidth = EBI_BUS_WIDTH_8,
        .byteAccess = EBI_BYTE_ACCESS_SELECT,
        .nWait = EBI_NWAIT_FROZEN,
        .wrMode = EBI_WRITE_MODE_NWE,
        .rdMode = EBI_READ_MODE_NRD
    };
    
    ConfigureEBI_CS(0, fastConfig);
    ConfigureEBI_CS(1, slowConfig);
    
    iprintf("CS0: Fast SRAM, CS1: Slow Flash\r\n");
}

Example 4: Complete initialization with error checking

bool InitializeEBI_Device(uint32_t csNum, const EBI_CS_cfg_t &config) {
    // Validate chip select number
    if (csNum > 3) {
        iprintf("Error: Invalid chip select %lu\r\n", csNum);
        return false;
    }
    
    // Validate TDF cycles
    if (config.tdf_cycles > 15) {
        iprintf("Error: TDF cycles must be 0-15\r\n");
        return false;
    }
    
    // Configure the hardware
    ConfigureEBI_CSPin(csNum);
    
    if (config.wrMode == EBI_WRITE_MODE_NWE) {
        ConfigureEBI_NWRPin();
    }
    
    if (config.rdMode == EBI_READ_MODE_NRD) {
        ConfigureEBI_NRDPin();
    }
    
    // Apply configuration
    ConfigureEBI_CS(csNum, config);
    
    iprintf("CS%lu configured successfully\r\n", csNum);
    return true;
}
 
void UserMain(void *pd) {
    init();
    
    EBI_CS_cfg_t myConfig = {
        .ncs_rd_setup = 2, .nrd_setup = 2,
        .ncs_rd_pulse = 10, .nrd_pulse = 10,
        .nrd_cycles = 15,
        .ncs_wr_setup = 2, .nwe_setup = 2,
        .ncs_wr_pulse = 10, .nwe_pulse = 10,
        .nwe_cycles = 15,
        .tdf_cycles = 2,
        .busWidth = EBI_BUS_WIDTH_16,
        .byteAccess = EBI_BYTE_ACCESS_WRITE,
        .nWait = EBI_NWAIT_DISABLED,
        .wrMode = EBI_WRITE_MODE_NWE,
        .rdMode = EBI_READ_MODE_NRD
    };
    
    if (InitializeEBI_Device(0, myConfig)) {
        iprintf("Device ready for operations\r\n");
    }
    
    while(1) {
        OSTimeDly(TICKS_PER_SECOND);
    }
}

Example 5: Configuration storage and retrieval

// Global storage for configurations
EBI_CS_cfg_t g_csConfigs[4];
 
void StoreConfiguration(uint32_t csNum, const EBI_CS_cfg_t &config) {
    if (csNum < 4) {
        g_csConfigs[csNum] = config;
        iprintf("Configuration stored for CS%lu\r\n", csNum);
    }
}
 
void ApplyStoredConfiguration(uint32_t csNum) {
    if (csNum < 4) {
        ConfigureEBI_CS(csNum, g_csConfigs[csNum]);
        iprintf("Applied stored configuration to CS%lu\r\n", csNum);
    }
}
 
void UserMain(void *pd) {
    init();
    
    // Create and store configurations
    EBI_CS_cfg_t sramConfig = {
        .ncs_rd_setup = 2, .nrd_setup = 2,
        .ncs_rd_pulse = 10, .nrd_pulse = 10,
        .nrd_cycles = 15,
        .ncs_wr_setup = 2, .nwe_setup = 2,
        .ncs_wr_pulse = 10, .nwe_pulse = 10,
        .nwe_cycles = 15,
        .tdf_cycles = 2,
        .busWidth = EBI_BUS_WIDTH_16,
        .byteAccess = EBI_BYTE_ACCESS_WRITE,
        .nWait = EBI_NWAIT_DISABLED,
        .wrMode = EBI_WRITE_MODE_NWE,
        .rdMode = EBI_READ_MODE_NRD
    };
    
    StoreConfiguration(0, sramConfig);
    
    // Later, apply the stored configuration
    ConfigureEBI_CSPin(0);
    ConfigureEBI_NWRPin();
    ConfigureEBI_NRDPin();
    ApplyStoredConfiguration(0);
    
    while(1) {
        OSTimeDly(TICKS_PER_SECOND);
    }
}

Example 6: Dynamic configuration based on clock frequency

EBI_CS_cfg_t CreateTimingConfig(uint32_t ebiClockMHz, 
                                 uint32_t setupNs,
                                 uint32_t pulseNs, 
                                 uint32_t holdNs)
{
    float nsPerCycle = 1000.0f / ebiClockMHz;
    
    uint8_t setupCycles = (uint8_t)((setupNs + nsPerCycle - 1) / nsPerCycle);
    uint8_t pulseCycles = (uint8_t)((pulseNs + nsPerCycle - 1) / nsPerCycle);
    uint8_t holdCycles = (uint8_t)((holdNs + nsPerCycle - 1) / nsPerCycle);
    uint16_t totalCycles = setupCycles + pulseCycles + holdCycles;
    
    return EBI_CS_cfg_t{
        .ncs_rd_setup = setupCycles, .nrd_setup = setupCycles,
        .ncs_rd_pulse = pulseCycles, .nrd_pulse = pulseCycles,
        .nrd_cycles = totalCycles,
        .ncs_wr_setup = setupCycles, .nwe_setup = setupCycles,
        .ncs_wr_pulse = pulseCycles, .nwe_pulse = pulseCycles,
        .nwe_cycles = totalCycles,
        .tdf_cycles = 2,
        .busWidth = EBI_BUS_WIDTH_16,
        .byteAccess = EBI_BYTE_ACCESS_WRITE,
        .nWait = EBI_NWAIT_DISABLED,
        .wrMode = EBI_WRITE_MODE_NWE,
        .rdMode = EBI_WRITE_MODE_NRD
    };
}
 
void InitializeDeviceWithTiming() {
    ConfigureEBI_CSPin(0);
    ConfigureEBI_NWRPin();
    ConfigureEBI_NRDPin();
    
    // Create config for 150MHz clock, 20ns setup, 70ns pulse, 10ns hold
    EBI_CS_cfg_t timing = CreateTimingConfig(150, 20, 70, 10);
    
    // Apply configuration
    ConfigureEBI_CS(0, timing);
    
    iprintf("Device configured with calculated timing\r\n");
}

---

ConfigureEBI_CSPin()

void ConfigureEBI_CSPin

(

int

csNum

)

#include <ebi.h>

Configure the I/O pin for a given Chip Select for the external data bus.

This function configures the GPIO pin associated with a specific chip select line on the External Bus Interface (EBI). The chip select pin is configured for proper timing and electrical characteristics to control external memory or peripheral devices connected to the data bus.

Parameters

csNum

The chip select number to configure (typically 0-3 depending on platform). Valid range depends on the specific NetBurner platform being used.

Note

This function should be called before attempting to access any external devices connected to the specified chip select line.

Warning

Ensure the chip select number is valid for your platform. Invalid values may result in undefined behavior.

See also

ConfigureEBI_NWRPin()

ConfigureEBI_NRDPin()

---

Expand for Example Usage

Examples

Example 1: Configuring a single chip select for external SRAM

void UserMain(void *pd) {
    init();
    
    // Configure chip select 0 for external SRAM
    ConfigureEBI_CSPin(0);
    ConfigureEBI_NWRPin();
    ConfigureEBI_NRDPin();
    
    iprintf("EBI CS0 configured for external memory\r\n");
    
    while(1) {
        OSTimeDly(TICKS_PER_SECOND);
    }
}

Example 2: Configuring multiple chip selects for different peripherals

void InitializeExternalBus() {
    // Configure CS0 for external SRAM
    ConfigureEBI_CSPin(0);
    
    // Configure CS1 for external FPGA
    ConfigureEBI_CSPin(1);
    
    // Configure CS2 for external display controller
    ConfigureEBI_CSPin(2);
    
    // Configure control signals shared by all devices
    ConfigureEBI_NWRPin();
    ConfigureEBI_NRDPin();
    
    iprintf("External bus configured for 3 devices\r\n");
}
 
void UserMain(void *pd) {
    init();
    InitializeExternalBus();
    
    while(1) {
        OSTimeDly(TICKS_PER_SECOND);
    }
}

---

ConfigureEBI_NRDPin()

void ConfigureEBI_NRDPin

(

)

#include <ebi.h>

Configure the I/O pin for the active low read (NRD) bus signal.

This function configures the GPIO pin for the NRD (Not Read) signal on the External Bus Interface (EBI). The NRD signal is an active-low control signal that indicates when the bus is performing a read operation from an external device.

Note

This function must be called once during initialization before performing any read operations from external devices on the EBI bus.

The NRD pin is typically shared across all chip selects on the external bus.

See also

ConfigureEBI_CSPin()

ConfigureEBI_NWRPin()

---

Expand for Example Usage

Examples

Example 1: Basic EBI initialization with read capability

void InitializeEBI() {
    // Configure chip select for external device
    ConfigureEBI_CSPin(0);
    
    // Configure write control signal
    ConfigureEBI_NWRPin();
    
    // Configure read control signal
    ConfigureEBI_NRDPin();
    
    iprintf("EBI configured for read/write operations\r\n");
}
 
void UserMain(void *pd) {
    init();
    InitializeEBI();
    
    while(1) {
        OSTimeDly(TICKS_PER_SECOND);
    }
}

Example 2: Read-only external memory configuration

void InitializeReadOnlyMemory() {
    // Configure CS for ROM device
    ConfigureEBI_CSPin(2);
    
    // Only need read signal for ROM
    ConfigureEBI_NRDPin();
    
    iprintf("Read-only EBI device configured on CS2\r\n");
}
 
void UserMain(void *pd) {
    init();
    InitializeReadOnlyMemory();
    
    // Device ready for read operations
    while(1) {
        OSTimeDly(TICKS_PER_SECOND);
    }
}

Example 3: Complete external bus setup with error checking

bool InitializeExternalBus(int csNum) {
    if (csNum < 0 || csNum > 3) {
        iprintf("Error: Invalid chip select %d\r\n", csNum);
        return false;
    }
    
    // Configure all necessary signals
    ConfigureEBI_CSPin(csNum);
    ConfigureEBI_NWRPin();
    ConfigureEBI_NRDPin();
    
    iprintf("EBI CS%d fully configured\r\n", csNum);
    return true;
}
 
void UserMain(void *pd) {
    init();
    
    if (InitializeExternalBus(0)) {
        iprintf("External device ready for operations\r\n");
    }
    
    while(1) {
        OSTimeDly(TICKS_PER_SECOND);
    }
}

---

ConfigureEBI_NWRPin()

void ConfigureEBI_NWRPin

(

)

#include <ebi.h>

Configure the I/O pin for the active low write/read (NWR) bus signal.

This function configures the GPIO pin for the NWR (Not Write) signal on the External Bus Interface (EBI). The NWR signal is an active-low control signal that indicates when the bus is performing a write operation to an external device.

Note

This function must be called once during initialization before performing any write operations to external devices on the EBI bus.

The NWR pin is typically shared across all chip selects on the external bus.

See also

ConfigureEBI_CSPin()

ConfigureEBI_NRDPin()

---

Expand for Example Usage

Examples

Example 1: Basic EBI initialization with write capability

void InitializeEBI() {
    // Configure chip select for external device
    ConfigureEBI_CSPin(0);
    
    // Configure write control signal
    ConfigureEBI_NWRPin();
    
    // Configure read control signal
    ConfigureEBI_NRDPin();
    
    iprintf("EBI configured for read/write operations\r\n");
}
 
void UserMain(void *pd) {
    init();
    InitializeEBI();
    
    while(1) {
        OSTimeDly(TICKS_PER_SECOND);
    }
}

Example 2: Write-only external bus configuration

void InitializeWriteOnlyDevice() {
    // Configure CS for write-only display
    ConfigureEBI_CSPin(1);
    
    // Only need write signal for this device
    ConfigureEBI_NWRPin();
    
    iprintf("Write-only EBI device configured on CS1\r\n");
}
 
void UserMain(void *pd) {
    init();
    InitializeWriteOnlyDevice();
    
    // Device ready for write operations
    while(1) {
        OSTimeDly(TICKS_PER_SECOND);
    }
}

---

Variable Documentation

busWidth

EBI_CS_BusWidth_t EBI_CS_cfg_t::busWidth

Data bus width configuration.

Specifies whether the external device uses 8-bit or 16-bit data transfers. Must match the physical connection and device capabilities.

See also

EBI_CS_BusWidth_t

byteAccess

EBI_CS_ByteAccess_t EBI_CS_cfg_t::byteAccess

Byte access mode for 16-bit bus configurations.

Controls how 8-bit accesses are handled on a 16-bit bus. Only relevant when busWidth is set to EBI_BUS_WIDTH_16.

See also

EBI_CS_ByteAccess_t

Note

This setting is ignored for 8-bit bus configurations.

ncs_rd_pulse

uint8_t EBI_CS_cfg_t::ncs_rd_pulse

NCS (Chip Select) pulse width during read operations, in clock cycles. Defines how long the chip select remains asserted during a read.

Formula: NCS pulse length = (256 × ncs_rd_pulse[6] + ncs_rd_pulse[5:0]) clock cycles

Range: 0-63 standard (0-16319 with extended bit)

Note

The pulse width determines the active time of the signal.

ncs_rd_setup

uint8_t EBI_CS_cfg_t::ncs_rd_setup

NCS (Chip Select) setup time for read operations, in clock cycles. Defines the time from CS assertion to read signal assertion.

Formula: NCS setup length = (128 × ncs_rd_setup[5] + ncs_rd_setup[4:0]) clock cycles

Range: 0-63 standard (0-8063 with extended bit)

Note

This sets when the chip select activates before the read signal.

ncs_wr_pulse

uint8_t EBI_CS_cfg_t::ncs_wr_pulse

NCS (Chip Select) pulse width during write operations, in clock cycles. Defines how long the chip select remains asserted during a write.

Formula: NCS pulse length = (256 × ncs_wr_pulse[6] + ncs_wr_pulse[5:0]) clock cycles

Range: 0-63 standard (0-16319 with extended bit)

ncs_wr_setup

uint8_t EBI_CS_cfg_t::ncs_wr_setup

NCS (Chip Select) setup time for write operations, in clock cycles. Defines the time from CS assertion to write signal assertion.

Formula: NCS setup length = (128 × ncs_wr_setup[5] + ncs_wr_setup[4:0]) clock cycles

Range: 0-63 standard (0-8063 with extended bit)

nrd_cycles

uint16_t EBI_CS_cfg_t::nrd_cycles

Total read cycle length in clock cycles.

The total read cycle length is the complete duration of a read operation, equal to the sum of setup, pulse, and hold times for NRD and NCS signals.

Formula: Read cycle length = (nrd_cycles[8:7] × 256 + nrd_cycles[6:0]) clock cycles

Range: 0-127 standard (0-32639 with extended bits)

Calculation: nrd_cycles = ncs_rd_setup + ncs_rd_pulse + hold_time

Note

The hold time is implicit: Hold = nrd_cycles - (setup + pulse)

nrd_pulse

uint8_t EBI_CS_cfg_t::nrd_pulse

NRD (Read Enable) pulse width, in clock cycles. Defines how long the read enable signal remains asserted.

Formula: NRD pulse length = (256 × nrd_pulse[6] + nrd_pulse[5:0]) clock cycles

Range: 0-63 standard (0-16319 with extended bit)

Note

This is typically the minimum access time required by the device.

nrd_setup

uint8_t EBI_CS_cfg_t::nrd_setup

NRD (Read Enable) setup time, in clock cycles. Defines the delay from CS assertion to read enable assertion.

Formula: NRD setup length = (128 × nrd_setup[5] + nrd_setup[4:0]) clock cycles

Range: 0-63 standard (0-8063 with extended bit)

nWait

EBI_CS_NWait_t EBI_CS_cfg_t::nWait

NWAIT signal mode for bus cycle extension.

Configures how the external NWAIT signal is used to extend read/write cycles for slow devices. Commonly used with flash memory or variable-speed peripherals.

See also

EBI_CS_NWait_t

Note

When disabled, all timing is strictly controlled by the configured values.

nwe_cycles

uint16_t EBI_CS_cfg_t::nwe_cycles

Total write cycle length in clock cycles.

The total write cycle length is the complete duration of a write operation, equal to the sum of setup, pulse, and hold times for NWE and NCS signals.

Formula: Write cycle length = (nwe_cycles[8:7] × 256 + nwe_cycles[6:0]) clock cycles

Range: 0-127 standard (0-32639 with extended bits)

Calculation: nwe_cycles = ncs_wr_setup + ncs_wr_pulse + hold_time

Note

The hold time is implicit: Hold = nwe_cycles - (setup + pulse)

nwe_pulse

uint8_t EBI_CS_cfg_t::nwe_pulse

NWE (Write Enable) pulse width, in clock cycles. Defines how long the write enable signal remains asserted.

Formula: NWE pulse length = (256 × nwe_pulse[6] + nwe_pulse[5:0]) clock cycles

Range: 0-63 standard (0-16319 with extended bit)

Note

This is typically the minimum write pulse time required by the device.

nwe_setup

uint8_t EBI_CS_cfg_t::nwe_setup

NWE (Write Enable) setup time, in clock cycles. Defines the delay from CS assertion to write enable assertion.

Formula: NWE setup length = (128 × nwe_setup[5] + nwe_setup[4:0]) clock cycles

Range: 0-63 standard (0-8063 with extended bit)

rdMode

EBI_CS_RdMode_t EBI_CS_cfg_t::rdMode

Read control signal selection.

Determines which signal (NCS or NRD) controls read operations from the external device.

See also

EBI_CS_RdMode_t

ConfigureEBI_NRDPin()

tdf_cycles

uint8_t EBI_CS_cfg_t::tdf_cycles

Data Float time - number of clock cycles for the external device to release the data after the rising edge of the read controlling signal.

This represents the time the external device needs to tri-state its outputs after a read operation completes. The SMC always provides one full cycle of bus turnaround after this TDF period.

Valid range: 0-15 clock cycles

Note

This prevents bus contention when switching between read and write operations.

A value of 0-2 is typical for fast devices; 3-5 for slower devices.

wrMode

EBI_CS_WrMode_t EBI_CS_cfg_t::wrMode

Write control signal selection.

Determines which signal (NCS or NWE) controls write operations to the external device.

See also

EBI_CS_WrMode_t

ConfigureEBI_NWRPin()