DSPI for ARM SAME70 (MODM7AE70, SBE70LC) More...

Classes
struct	spiDriverStruct
	Variables/configurations for a DSPI transfer. More...

class	SPIModule
	SPI Peripheral Module Class. More...

Enumerations
enum	csReturnType { DEASSERT_NEVER = 0 , DEASSERT_AFTER_LAST = 1 , DEASSERT_EVERY_TRANSFER = 2 }
	Chip select deassertion modes. Used to determine when the driver should deassert chip selects during SPI transfer. More...

enum	spiChipSelectPolarity { CS_ASSERT_LOW = 0 , CS_ASSERT_HIGH = 1 }
	Chip select polarity. More...

Functions
uint8_t	DSPIInit (uint8_t SPIModule=DEFAULT_DSPI_MODULE, uint32_t Baudrate=2000000, uint8_t QueueBitSize=8, uint8_t CS=0x00, uint8_t CSPol=0x0F, uint8_t ClkPolarity=0, uint8_t ClkPhase=1, BOOL DoutHiz=TRUE, uint8_t QCD=0, uint8_t DTL=0)
	Initialize a DSPI module.

uint8_t	DSPIStart (uint8_t SPIModule, puint8_t transmitBufferPtr, volatile uint8_t receiveBufferPtr, uint32_t byteCount, OS_SEM finishedSem=NULL, uint8_t enableDMA=TRUE, int csReturnToInactive=DEASSERT_AFTER_LAST)
	Start a DSPI transfer.

BOOL	DSPIdone (uint8_t SPIModule=DEFAULT_DSPI_MODULE)
	Check SPI status.

Variables
const uint8_t	CHIP_SELECT_0 = 0
	Chip select number.

const uint8_t	CHIP_SELECT_1 = 1
	Configure the SPI peripheral to use chip select 1.

const uint8_t	CHIP_SELECT_2 = 2
	Configure the SPI peripheral to use chip select 2.

const uint8_t	CHIP_SELECT_3 = 3
	Configure the SPI peripheral to use chip select 3.

const uint8_t	CHIP_SELECT_DISABLED = 0xFF
	Or flag to set multi bit chipselect.

QSPI to DSPI Translation macros
(Compatibility function for previous drivers, note that the 'Q' stands for Queued SPI)
uint8_t	QSPIInit (uint32_t baudRateInBps=2000000, uint8_t transferSizeInBits=8, uint8_t peripheralChipSelects=0x0F, uint8_t chipSelectPolarity=1, uint8_t clockPolarity=0, uint8_t clockPhase=1, BOOL doutHiz=TRUE, uint8_t csToClockDelay=0, uint8_t delayAfterTransfer=0)
	Initialize Queued Serial Peripheral Interface (QSPI)

uint8_t	QSPIStart (puint8_t transmitBufferPtr, volatile uint8_t receiveBufferPtr, uint32_t byteCount, OS_SEM finishedSem=NULL)
	Start QSPI Data Transfer.

BOOL	QSPIdone ()
	Check SPI status. (Compatibility function for previous drivers, note that the 'Q' stands for Queued SPI)

DSPI Bus State

#define	DSPI_OK ( 0 )
	DSPI OK.

#define	DSPI_BUSY ( 1 )
	DSPI Busy.

#define	DSPI_ERROR ( 2 )
	DSPI Error.

DSPI Peripheral Module
#define	DEFAULT_DSPI_MODULE 0
	Default DSPI module.

#define	DSPI_MODULE_COUNT 1
	Number of modules: 0, 1.

Detailed Description

DSPI for ARM SAME70 (MODM7AE70, SBE70LC)

Supported Platforms:

MODM7AE70
SBE70LC

Note that for the SAME70 there are 3 types of SPI peripherals:

SPI using the SPI peripheral: Provides the most configuration options. Used in single data channel mode: SCLK, MISO, MOSI, Chip Selects.
SPI using the QSPI peripheral: Single data channel as with SPI, but fewer configuration options.
SPI using the USART peripheral: Single data channel as with SPI, but fewer configuration options.

Enumeration Type Documentation

◆ csReturnType

enum csReturnType

#include <dspi.h>

Chip select deassertion modes. Used to determine when the driver should deassert chip selects during SPI transfer.

Enumerator
DEASSERT_NEVER	The chip select used for the transaction should remain asserted, even after the transaction is complete.
DEASSERT_AFTER_LAST	The chip select should remain asserted for the full duration of the transaction, and only be deasserted after the final transfer.
DEASSERT_EVERY_TRANSFER	The chip select should be deasserted between every transfer within the transaction.Deassert chip select After every transfer.

◆ spiChipSelectPolarity

enum spiChipSelectPolarity

#include <dspi.h>

Chip select polarity.

This enum exists for API compatibility between platforms. The SAME70's SPI peripheral does not support modifying chip select polarity. The SPI peripheral only supports asserting chip select to logic level LOW during a transaction. If you need to assert the chip select to logic level HIGH during a transaction, your alternative is to use a GPIO for chip select.

Enumerator
CS_ASSERT_LOW	Assert all chip selects to logic level LOW during a SPI transaction.
CS_ASSERT_HIGH	Assert all chip selects to logic level HIGH during a SPI transaction.

Function Documentation

◆ DSPIdone()

BOOL DSPIdone ( uint8_t SPIModule = DEFAULT_DSPI_MODULE )

#include <dspi.h>

Check SPI status.

Returns: true if DSPI is finished, false if active

◆ DSPIInit()

uint8_t DSPIInit	(	uint8_t	SPIModule = DEFAULT_DSPI_MODULE,
		uint32_t	Baudrate = 2000000,
		uint8_t	QueueBitSize = 8,
		uint8_t	CS = 0x00,
		uint8_t	CSPol = 0x0F,
		uint8_t	ClkPolarity = 0,
		uint8_t	ClkPhase = 1,
		BOOL	DoutHiz = TRUE,
		uint8_t	QCD = 0,
		uint8_t	DTL = 0 )

#include <dspi.h>

Initialize a DSPI module.

Notes:

The maximum baud rate is CPU_CLOCK / 3
Will initialize to the highest available baud rate that does not exceed the maximum
If configured for 8 bits per transfer then the data must be uint8_t aligned
If configured for greater than 8 bits per transfer then the data must be uint16_t aligned
If configured for greater than 16 bits per transfer then the data must be uint32_t aligned
Chip select is based on chipSelectPolarity
0 data captured leading edge of DSPI_CLK, changed following edge.
1 data changed leading edge of DSPI_CLK, captured following edge.
0 default is as close to 1/2 DSPI_CLK without going under, keeping with the interface to SPI
0 default is 17/(system clock / 2), in keeping with interface to QSPI

Parameters

SPIModule	SPI module number, 0 - 1
Baudrate	Maximum baud rate requested
QueueBitSize	Number of bits per transfer: 8, 16 or 32
CS	SPI chip selects to use for transfer
CSPol	0 = inactive logic level low, 1 = high
ClkPolarity	0 = inactive logic level low, 1 = high
ClkPhase	0 = data captured leading edge clock, changed following edge. 1 = data changed leading edge clock, captured following edge.
DoutHiz	Data output high impedance between transfers
QCD	Delay from chip select to valid clock (default is 0)
DTL	Chip select mode dspiChipSelectMode

Returns: Current stat of DSPI bus dspiState

◆ DSPIStart()

uint8_t DSPIStart	(	uint8_t	SPIModule,
		puint8_t	transmitBufferPtr,
		volatile uint8_t *	receiveBufferPtr,
		uint32_t	byteCount,
		OS_SEM *	finishedSem = NULL,
		uint8_t	enableDMA = TRUE,
		int	csReturnToInactive = DEASSERT_AFTER_LAST )

#include <dspi.h>

Start a DSPI transfer.

If configured for 8 bits per transfer then the data must be uint8_t aligned
If configured for > than 8 bits per transfer then the data must be uint16_t aligned
If configured for > than 16 bits per transfer then the data must be uint32_t aligned
If either RX or TX pointer is assigned 'null' then that communication direction will not occur.
If DSPI_Finished points to a semaphore, then the DSPI will POST to it when the transfer is complete.
The semaphore is optional, but it can increase efficiency.

Parameters

SPIModule	DSPI module to use, 0 - 1
transmitBufferPtr	Pointer to the buffer containing the data to transmit
receiveBufferPtr	Pointer to the buffer to store the received data
byteCount	Number of bytes to transmit
finishedSem	Optional semaphore to post to when finished
enableDMA	Enable DMA transfers
csReturnToInactive	Chip select state

Returns: The current state of the SPI bus dspiState

◆ QSPIdone()

BOOL QSPIdone ( void )

inline

#include <dspi.h>

Check SPI status. (Compatibility function for previous drivers, note that the 'Q' stands for Queued SPI)

Can be called after QSPIStart(). Returns TRUE when transfer is complete. This is an alternative to using a semaphore.

Returns: true if DSPI is finished, false if active

◆ QSPIInit()

uint8_t QSPIInit	(	uint32_t	baudRateInBps = 2000000,
		uint8_t	transferSizeInBits = 8,
		uint8_t	peripheralChipSelects = 0x0F,
		uint8_t	chipSelectPolarity = 1,
		uint8_t	clockPolarity = 0,
		uint8_t	clockPhase = 1,
		BOOL	doutHiz = TRUE,
		uint8_t	csToClockDelay = 0,
		uint8_t	delayAfterTransfer = 0 )

inline

#include <dspi.h>

Initialize Queued Serial Peripheral Interface (QSPI)

Notes: (3) Transfers > 8 must be word aligned (4) Select based on chipSelectPolarity (5) 0 data captured leading edge of QSPI_CLK, changed following edge. (6) 1 data changed leading edge of QSPI_CLK, captured following edge. (7) 0 default is 1/2 QSPI_CLK or see MFCXXXX reference manual (8) 0 default is 8192/(system clock / 2) see MFCXXXX reference manual

Parameters

baudRateInBps	Maximum requested baud rate in bits per second. The maximum possible baud rate is determined by the system clock. The function will select the highest possible baud rate if the specified value cannot be achieved.
transferSizeInBits	Size of data values to be transferred. Values can be 8, 16 or 32 bits. Note that 16 and 32 bit size values must be word (16-bit) aligned (16-bit).
peripheralChipSelects	Peripheral chip select drive level. Used to select an external device for serial data transfer. More than one chip select may be active at once, and more than one device can be connected to each chip select. Bits 3-0 map directly to QSPI_CS[3:0], respectively. For each bit: 0 = Chip select is 0 during a transfer. 1 = Chip select is 1 during a transfer.
chipSelectPolarity	Peripheral chip select inactive level (no transfer in progress). Applies to all chip selects. 0 = 0 when inactive 1 = 1 when inactive
clockPolarity	Clock polarity: 0 = The inactive state value of QSPI_CLK is logic level 0. 1 = The inactive state value of QSPI_CLK is logic level 1.
clockPhase	Clock phase: 0 = Data captured on the leading edge of QSPI_CLK and changed on the following edge of QSPI_CLK. 1 = Data changed on the leading edge of QSPI_CLK and captured on the following edge of QSPI_CLK.
doutHiz	Data output high impedance enable. Selects QSPI_DOUT mode of operation. 0 = Default value after reset. QSPI_DOUT is actively driven between transfers. 1 = QSPI_DOUT is high impedance between transfers.
csToClockDelay	QCD, QSPICLK delay. When the DSCK bit in the command RAM is set this field determines the length of the delay from assertion of the chip selects to valid QSPI_CLK transition.
delayAfterTransfer	Delay after transfer. When the DT bit in the command RAM is set this field determines the length of delay after the serial transfer.

Returns: groupQspiState

See also: QSPIInit(); QSPIStart()

◆ QSPIStart()

uint8_t QSPIStart	(	puint8_t	transmitBufferPtr,
		volatile uint8_t *	receiveBufferPtr,
		uint32_t	byteCount,
		OS_SEM *	finishedSem = NULL )

inline

#include <dspi.h>

Start QSPI Data Transfer.

Parameters

transmitBufferPtr	Pointer to the buffer to use in the transfer. Specify NULL for receive only.
receiveBufferPtr	Pointer to buffer to store received data. NULL for transmit only.
byteCount	Number of bytes to send or receive. If the data size is greater than 8-bit, you must provide the total number of bytes.
finishedSem	Pointer to preinitialized semaphore to post to when transfer is complete. A value of NULL disables the semaphore function.

Returns: groupQspiState

See also: QSPIInit(); QSPIdone()

Variable Documentation

◆ CHIP_SELECT_0

const uint8_t CHIP_SELECT_0 = 0

#include <dspi.h>

Chip select number.

If supported by the SPI peripheral, these values can be used to configure the chip select to be used during a SPI transfer. Configure the SPI peripheral to use chip select 0.

◆ CHIP_SELECT_DISABLED

const uint8_t CHIP_SELECT_DISABLED = 0xFF

#include <dspi.h>

Or flag to set multi bit chipselect.

Configure the SPI peripheral to disable chip select.

Classes

Enumerations

Functions

Variables

QSPI to DSPI Translation macros

DSPI Bus State

DSPI Peripheral Module

Detailed Description

Enumeration Type Documentation

◆ csReturnType

◆ spiChipSelectPolarity

Function Documentation

◆ DSPIdone()

◆ DSPIInit()

◆ DSPIStart()

◆ QSPIdone()

◆ QSPIInit()

◆ QSPIStart()

Variable Documentation

◆ CHIP_SELECT_0

◆ CHIP_SELECT_DISABLED