coldfire/cpu/MCF5441X/include/dspi.h

/*NB_REVISION*/
 
/*NB_COPYRIGHT*/
 
/* ===========================================================================
 * Note to NetBurner developers -- where to document functions:
 *
 * The Doxygen documentation for the DSPI functions shared by every
 * platform lives in the flagship header:
 *     arch/cortex-m7/cpu/MIMXRT11xx/include/dspi.h
 * Doxygen merges same-name, same-parameter-list functions across the
 * per-architecture dspi.h files onto one page, so documenting the same
 * signature in two files duplicates the documentation. In THIS file:
 *  - Shared functions (DSPIInit, DSPIStart, DSPIdone) carry plain comments
 *    (// ...) only. Plain comments are invisible to Doxygen and keep this
 *    header readable for developers with a single-platform tools install.
 *  - Only functions unique to this platform (or with a unique signature)
 *    carry Doxygen comments, tagged with a platform @note.
 * When adding a new function: if it exists on multiple platforms with the
 * same signature, put its Doxygen comment in the flagship header and a
 * plain // comment here; if it is unique to this platform, document it
 * here with a Doxygen comment and a platform @note.
 * ======================================================================== */


 
#ifndef _DMA_SPI_H_INC
#define _DMA_SPI_H_INC
#include <nbrtos.h>
#include <basictypes.h>
#include <sim5441x.h>
 
#ifndef __cplusplus
#error DSPI driver is a C++ only library
#endif

#define DSPI_OK (0) 
#define DSPI_BUSY (1) 
#define DSPI_ERROR (2) 
 
#define MCR_MASTER_INIT 0x80000C01  
#define MCR_HALT_BIT 0x00000001  
#define MCR_DIS_TXF 0x00002000  
#define MCR_DIS_RXF 0x00001000  
#define MCR_CLR_FIFOS 0x00000C00  
 
#define CTAR_CLOCK_POLARITY 0x04000000  
#define CTAR_CLOCK_PHASE 0x02000000  
#define CTAR_FRAME_16BIT 0x78000000  
#define CTAR_FRAME_4BIT 0x18000000  
 
#define SR_EOQF_MASK 0x10000000  
#define SR_CLR_FLAGS 0x8A0A0000  
 
#define RSER_EOQF_IRQ_ONLY ~0x8B0B0000  
#define RSER_DMA_IRQ_ONLY 0x03030000  
 
#define PUSHR_CONT_BIT 0x80000000  
#define PUSHR_EOQ_BIT 0x08000000  
 
#define DMA_CH_DSPI_0_RX 0x0C 
#define DMA_CH_DSPI_0_TX 0x0D 
#define DMA_CH_DSPI_1_RX 0x0E 
#define DMA_CH_DSPI_1_TX 0x0F 
#define DMA_CH_DSPI_2_RX 0x1C 
#define DMA_CH_DSPI_2_TX 0x1D 
#define DMA_CH_DSPI_3_RX 0x2C 
#define DMA_CH_DSPI_3_TX 0x2D 
 
#define CR_CLEAR_NON_GRP_PRIO ~0x000300FF 
#define CR_SET_RR_CH_ARB 0x00000004 
 
#define TCD_ATTR_8BIT_TRANS 0x0000 
#define TCD_ATTR_16BIT_TRANS 0x0101 
 
#define TCD_XOFF_0uint8_t 0x0000 
#define TCD_XOFF_1uint8_t 0x0001 
#define TCD_XOFF_2uint8_t 0x0002 
 
#define TCD_XITER_CNT_MASK 0x7FFF 
 
#define TCD_CSR_DONE_BIT 0x0080 
#define TCD_CSR_DISABLE_REQ 0xC008 
#define TCD_CSR_DREQ_INT_MAJOR 0xC00A 
 
#define DEFAULT_DSPI_MODULE 1 
#define DSPI_MODULE_COUNT 4 

enum csReturnType
{
    DEASSERT_NEVER = 0,        
    DEASSERT_AFTER_LAST = 1,   
    DEASSERT_EVERY_TRANSFER = 2,   
};

enum spiChipSelect
{
    CHIP_SELECT_0 = 0xFE,          
    CHIP_SELECT_1 = 0xFD,          
    CHIP_SELECT_2 = 0xFB,          
    CHIP_SELECT_3 = 0xF7,          
    CHIP_SELECT_DISABLED = 0xFF,   
};

enum spiChipSelectPolarity
{
    CS_ASSERT_LOW = 0x00,    
    CS_ASSERT_HIGH = 0xFF,   
};

typedef struct
{
    bool enabled;         
    uint8_t byteCount;    
    bool rxPresent;       
    bool txPresent;       
    dspistruct savedDSPI; 
    bool csState;         
} dspiDMAStruct;

typedef struct
{
    volatile uint8_t *pDSPIRxbuf;     
    volatile uint8_t *pDSPITxbuf;     
    uint8_t BitsPerQueue;             
    uint32_t DSPI_SizeLeft;           
    uint16_t Command_Mask;            
    csReturnType csReturnToInactive;  
    OS_SEM *DSPI_Sem;                 
    volatile uint8_t DSPI_INT_STATUS; 
    uint32_t WordsToWrite;            
    uint32_t LastWordsToWrite;        
    volatile BOOL DSPIfinished;       
    dspiDMAStruct dma;                
} dspiDriverStruct;
 
// uint8_t DSPIInit( uint8_t SPIModule, uint32_t Baudrate, uint8_t QueueBitSize, uint8_t CS,
//                 uint8_t CSPol, uint8_t ClkPolarity, uint8_t ClkPhase, BOOL DoutHiz, uint8_t QCD, uint8_t DTL );

class DSPIModule
{
    uint32_t m_moduleNum;
    uint32_t m_mcr;
    uint32_t m_ctar0;
    uint32_t m_ctar1;
    bool m_enableDMA;
    uint16_t m_CommandMask;
    uint8_t m_BitsPerQueue;
    OS_SEM *m_finishedSem;
    uint32_t m_actualBaudrate;
 
   public:
    bool m_inProgress;
 
    static DSPIModule *lastCxts[DSPI_MODULE_COUNT];
    static dspiDriverStruct driverCxt[DSPI_MODULE_COUNT];

    DSPIModule(uint8_t SPIModule);

    DSPIModule(uint8_t SPIModule,
               uint32_t baudRateInBps,
               uint8_t transferSizeInBits = 8,
               uint8_t peripheralChipSelects = 0x00,
               uint8_t chipSelectPolarity = 0x0F,
               uint8_t clockPolarity = 0,
               uint8_t clockPhase = 1,
               BOOL doutHiz = TRUE,
               uint8_t csToClockDelay = 0,
               uint8_t delayAfterTransfer = 0);

    uint8_t Init(uint32_t baudRateInBps = 2000000,
                 uint8_t transferSizeInBits = 8,
                 uint8_t peripheralChipSelects = 0x00,
                 uint8_t chipSelectPolarity = 0x0F,
                 uint8_t clockPolarity = 0,
                 uint8_t clockPhase = 1,
                 BOOL doutHiz = TRUE,
                 uint8_t csToClockDelay = 0,
                 uint8_t delayAfterTransfer = 0);

    uint8_t Start(uint8_t *transmitBufferPtr,
                  volatile uint8_t *receiveBufferPtr,
                  uint32_t byteCount,
                  int csReturnToInactive = DEASSERT_AFTER_LAST);

    inline uint8_t Tx(uint8_t *transmitBufferPtr, uint32_t byteCount, int csReturnToInactive = DEASSERT_AFTER_LAST)
    {
        return Start(transmitBufferPtr, NULL, byteCount, csReturnToInactive);
    }

    inline uint8_t Rx(uint8_t *receiveBufferPtr, uint32_t byteCount, int csReturnToInactive = DEASSERT_AFTER_LAST)
    {
        return Start(NULL, receiveBufferPtr, byteCount, csReturnToInactive);
    }

    bool EnableDMA(bool enableDMA = true);
    inline bool DisableDMA() { return EnableDMA(false); }

    bool RegisterSem(OS_SEM *finishedSem);
    inline bool ClrSem() { return RegisterSem(NULL); }
    inline OS_SEM *GetSem() { return m_finishedSem; }

    inline bool Done() { return !m_inProgress; }

    static BOOL Done(uint8_t SPIModule);

    inline uint32_t GetActualBaudrate() { return m_actualBaudrate; }

    inline bool SetCS(uint8_t CS)
    {
        OSLockObj lock;
        if (m_inProgress) { return false; }
        m_CommandMask = (((m_mcr >> 16) ^ CS) & 0xFF);
        return true;
    }

    friend uint8_t DSPIInit(uint8_t SPIModule,
                            uint32_t Baudrate,
                            uint8_t QueueBitSize,
                            uint8_t CS,
                            uint8_t CSPol,
                            uint8_t ClkPolarity,
                            uint8_t ClkPhase,
                            BOOL DoutHiz,
                            uint8_t QCD,
                            uint8_t DTL);
};
 
// Initialize a DSPI module.
//  SPIModule:   SPI module number, 0 - 1.
//  Baudrate:    maximum baud rate requested; the driver uses the highest
//               available rate that does not exceed it (max CPU_CLOCK / 3).
//  QueueBitSize: bits per transfer, 8, 16 or 32. Data buffers must be
//               uint8_t / uint16_t / uint32_t aligned respectively.
//  CS:          SPI chip select(s) to use for the transfer.
//  CSPol:       chip select inactive level, 0 = low, 1 = high.
//  ClkPolarity: clock inactive level, 0 = low, 1 = high.
//  ClkPhase:    0 = data captured on the leading clock edge and changed on
//               the following edge; 1 = changed leading, captured following.
//  DoutHiz:     data output high impedance between transfers.
//  QCD:         QDLYR delay from chip select assertion to the start of the
//               DSPI clock (0 = one half DSPI clock).
//  DTL:         QDLYR delay following the transfer of each uint16_t in the
//               DSPI queue (0 = 17/(fsys/2)).
//  Returns the DSPI bus state (DSPI_OK, DSPI_BUSY, DSPI_ERROR).
uint8_t DSPIInit(uint8_t SPIModule = DEFAULT_DSPI_MODULE,
                 uint32_t Baudrate = 2000000,
                 uint8_t QueueBitSize = 8,
                 uint8_t CS = 0x00,
                 uint8_t CSPol = 0x0F,
                 uint8_t ClkPolarity = 0,
                 uint8_t ClkPhase = 1,
                 BOOL DoutHiz = TRUE,
                 uint8_t QCD = 0,
                 uint8_t DTL = 0);
 
// Start a DSPI transfer. Pass NULL for transmitBufferPtr or
//  receiveBufferPtr to skip that direction. If finishedSem is provided, it
//  is posted when the transfer completes (otherwise poll with DSPIdone()).
//  csReturnToInactive selects when the chip select is deasserted.
//  Returns the DSPI bus state (DSPI_OK or DSPI_BUSY).
uint8_t DSPIStart(uint8_t SPIModule,
                  puint8_t transmitBufferPtr,
                  volatile uint8_t *receiveBufferPtr,
                  uint32_t byteCount,
                  OS_SEM *finishedSem = NULL,
                  uint8_t enableDMA = TRUE,
                  int csReturnToInactive = DEASSERT_AFTER_LAST);
 
// Check DSPI transfer status: TRUE = finished, FALSE = still active.
BOOL DSPIdone(uint8_t SPIModule = DEFAULT_DSPI_MODULE);
 
// QSPI to DSPITranslation macros
//  Translates QSPI calls to DSPI calls
 
inline uint8_t QSPIInit(uint32_t baudRateInBps = 2000000,
                        uint8_t transferSizeInBits = 8,
                        uint8_t peripheralChipSelects = 0x0F,
                        uint8_t chipSelectPolarity = 1,
                        uint8_t clockPolarity = 0,
                        uint8_t clockPhase = 1,
                        BOOL doutHiz = TRUE,
                        uint8_t csToClockDelay = 0,
                        uint8_t delayAfterTransfer = 0)
{
    return DSPIInit(DEFAULT_DSPI_MODULE, baudRateInBps, transferSizeInBits, peripheralChipSelects, chipSelectPolarity, clockPolarity,
                    clockPhase, doutHiz, csToClockDelay, delayAfterTransfer);
}
 
inline uint8_t QSPIStart(puint8_t transmitBufferPtr, volatile uint8_t *receiveBufferPtr, uint32_t byteCount, OS_SEM *finishedSem = NULL)
{
    return DSPIStart(DEFAULT_DSPI_MODULE, transmitBufferPtr, receiveBufferPtr, byteCount, finishedSem);
}
 
inline BOOL QSPIdone()
{
    return DSPIdone();
}
 
#endif /* ----- #ifndef _DMA_SPI_H_INC  ----- */