#include <nbwatchdog.h>

Detailed Description

Decoded snapshot of why the part last reset. Filled by WatchdogCaptureResetCause() from SRC->SRSR, the per-core System Reset Status Register, which this example clears every boot so it describes exactly the reset that produced the current boot.

A watchdog timeout is positively identified (watchdog1). A ForceReboot() and a reprogram both end in NVIC_SystemReset(), so those two present identically as softwareReset – distinguishable from the watchdog, a power cycle or the reset pin, though not from each other.

WDOG1->WRSR is captured for display only, not decoded: it records the last reset of the WDOG block itself (POR or watchdog timeout) and keeps that stale value across software resets, which do not reset the block.

Decoded snapshot of why the part last reset. Filled by WatchdogCaptureResetCause(), which reads SRC->SRSR and WDOG1->WRSR.

NOTE on this module: the clean watchdog reboot, a menu ForceReboot, a reprogram and an external reset all go through DoSWReset(), which drives the reset PINS – so in SRC->SRSR they are indistinguishable (all present as external-pin + power-on). There is no application-accessible register that survives a ForceReboot to tag the cause (SNVS_LP GPR is write-locked and the boot clears the SRC GPRs). A raw WDOG1 timeout would set a distinct SRSR bit, but that reset hangs the module, so it is never observed on a successful boot. In practice you observe a watchdog reboot LIVE (the module reboots the moment you stop servicing it), not from these post-reboot bits.

The documentation for this struct was generated from the following files: