NetBurner 3.5.8
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SOMRT1061 Hardware Design Guide

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For Carrier Board Designers and System Integrators

NetBurner SOMRT1061-200IR | Industrial Temperature

Module Overview

The SOMRT1061-200IR is a System on Module (SoM) based on the NXP i.MX RT1061 processor running at 528 MHz. It provides dual 10/100 Ethernet (one with integrated PHY), 1 MB internal SRAM, 32 MB external SDRAM, 8 MB flash, and extensive I/O – all in a compact 4x 22-pin form factor with industrial temperature range.

Key Specifications

Parameter Value
Processor NXP i.MX RT1061, 528 MHz ARM Cortex-M7
SRAM 1 MB internal (TCM + OCRAM)
SDRAM 32 MB external (on-module)
Flash 8 MB QuadSPI flash (on-module)
Ethernet 1x 10/100 with integrated PHY + 1x 10/100 RMII (external PHY required)
Operating Temp -40C to +85C
Dimensions 1.50" x 2.65" (38.1 mm x 67.3 mm)
Weight 0.5 oz (14 grams)
Connectors 4x 22-pin, 0.1" (2.54 mm) dual-row male

Block Diagram

+------------------+
| SDRAM |
| 32 MB |
+--------+---------+
|
+----------+ +----------+----------+ +----------+
|App Flash | | | | I/O |
|8MB QSPI +--->+ NXP i.MX RT1061 +--->+ Headers |
| | | 528MHz Cortex-M7 | | J1-J4 |
+----------+ | | | 88 pins |
| 1MB SRAM | +----------+
| |
+---+----+----+-------+
| | |
ENET0 USB1 USB2
(10/100 | |
+PHY) v v
| USB1 USB2
v (J2 (J2
+-----+---+ pins) pins)
| RJ-45 |
| Diff Pair|
| + LEDs |
+---------+
ENET0 (J3 P61-P66)
Ethernet 1: RMII signals on EMC_19-25 and AD_B1_04/05
Requires external PHY on carrier board

Power Supply Design

Main 3.3V Supply

The module requires a single 3.3VDC supply on pins P1, P38, P49 (DCDC_IN). All internal voltage regulators (DCDC and LDO) derive from this rail.

Configuration Current (3.3V)
No Ethernet connections 280 mA
1x Ethernet 100MB 320 mA
2x Ethernet 100MB 360 mA

Design Recommendations:

  • Use a regulator capable of at least 1A continuous output at 3.3V
  • 3.3V supply must reach operating voltage at a minimum rise rate of 2.4V/ms
  • Place bulk capacitance (47–100 uF) near the module power pins
  • Add 0.1 uF ceramic decoupling within 5 mm of each Vcc pin (P1, P38, P49)
  • Ensure low-impedance ground connections between carrier and module

Internal Power Domains

The module generates all internal rails from the 3.3V supply. These are NOT available on connectors and should NOT be externally supplied:

Domain Voltage Purpose
VDD_SOC 1.0V CPU core logic (DCDC output)
VDD_HIGH 3.0V PLLs, USB PHY
VDD_PLL 1.0V PLL analog
VDDA_ADC 3.3V ADC analog supply
VDD_SNVS 3.3V SNVS (POR, RTC, security)

Note: Unlike the i.MX RT1170-family modules, the SOMRT1061 does not expose a separate VDD_SNVS_IN pin. SNVS is powered internally from the 3.3V rail; RTC state is not retained when power is removed.

USB VBUS

The module senses VBUS on the USB OTG pins:

Pin Signal Notes
P32 USB_OTG2_VBUS OTG2 – typically used for host mode (5V)
P35 USB_OTG1_VBUS OTG1 – typically used for device mode
  • In host mode: Carrier board must supply 5V (min 500 mA per port) to these pins
  • In device mode: These pins sense VBUS from an upstream host
  • Add a current-limiting switch (e.g., AP22615A, TPS2051) for host-mode operation
  • Place a TVS diode (e.g., EGUARD0503F, PRTR5V0U2X) on each USB port for ESD protection

Ground Connections

Pin Notes
P5 EMC bank ground
P17 EMC bank ground
P39 USB / AD bank ground
P48 AD bank ground
P60 B1 bank ground
P79 EMC bank ground

Connect ALL ground pins to the carrier board ground plane. Do not leave any ground pin unconnected – these pins partition the module's internal supply domains and missing ground returns can cause supply-domain instability and EMI issues.

Reset Circuit

Pin P23 (POR_B) is the active-low reset input. The module includes:

  • 100K internal pull-up
  • Recommended 5K external pull-up on the carrier board
  • A momentary reset button between P23 and GND provides manual reset

Minimum reset pulse width: 1 ms recommended. The on-module reset IC asserts POR during power-up, so an external POR circuit is not required.

Tip: A 0.1 uF capacitor from P23 to GND adds noise immunity and a brief power-on hold, but is optional.

Ethernet Interface Design

Ethernet 0 (Integrated PHY)

Ethernet 0 uses the on-module integrated PHY (KSZ8081 or equivalent). The Ethernet 0 differential pairs and LED signals are routed to J3 pins P61–P66 for direct connection to an RJ45 with integrated magnetics on the carrier board.

Pin Signal Description
P61 ENET0_JLED2 Speed indicator LED drive
P62 ENET0_JLED1 Link/activity indicator LED drive
P63 ENET0_ERXJ_N Ethernet RX differential, negative
P64 ENET0_ERXJ_P Ethernet RX differential, positive
P65 ENET0_ETXJ_N Ethernet TX differential, negative
P66 ENET0_ETXJ_P Ethernet TX differential, positive

Carrier Board Recommendations:

  • Use an RJ45 with integrated 1:1 magnetics (e.g., YDS 13F-641GGDP2NL, BEL 0826-1G1T-43-F)
  • Route differential pairs as 100ohm differential controlled impedance
  • Length-match pairs within 5 mm
  • Place magnetics within 25 mm of the RJ45 connector
  • Add 75ohm center-tap termination resistors on the magnetics center taps to a 0.01 uF cap to GND
  • Bob Smith termination on unused pairs is built into many RJ45 connectors

Ethernet 1 (External PHY Required)

Ethernet 1 uses an RMII interface to an external 10/100 PHY on the carrier board. NetBurner reference designs typically use the TI DP83825I or similar.

RMII Pin Mapping:

Signal SOM Pin RT1061 Pad Alt Function
ENET_TX_EN P85 GPIO_EMC_24 ENET_TX_EN (ALT3)
ENET_REF_CLK P84 GPIO_EMC_25 ENET_REF_CLK (ALT4)
ENET_TXD0 P88 GPIO_EMC_19 ENET_RDATA01 (ALT3)*
ENET_TXD1 P87 GPIO_EMC_20 ENET_RDATA00 (ALT3)*
ENET_RXD0 P88 GPIO_EMC_19 (see note)
ENET_RXD1 P87 GPIO_EMC_20 (see note)
ENET_CRS_DV P86 GPIO_EMC_23 ENET_RX_EN (ALT4)
ENET_RX_ER P83 GPIO_EMC_26 ENET_RX_ER (ALT3)
ENET_MDC P44 GPIO_AD_B1_04 ENET_MDC (ALT1)
ENET_MDIO P45 GPIO_AD_B1_05 ENET_MDIO (ALT1)
  • RT1061 ENET pin assignments depend on whether ENET or ENET2 module is used. Check the i.MX RT1061 reference manual chapter 11 for definitive routing.

External PHY Requirements:

  • RMII-capable PHY (e.g., DP83825I, KSZ8081, LAN8720)
  • Provide 50 MHz reference clock (from PHY oscillator or external)
  • Place magnetics and RJ45 on carrier board (no integrated magnetics in this path)
  • Connect PHY interrupt to a GPIO pin (typically a free EMC pin)
  • Connect PHY hardware reset to a GPIO pin and assert per PHY datasheet timing
  • MDIO pull-up: 1.5K to 3.3V on the MDIO line

IEEE 1588 Precision Time Protocol

1588 event pins are available on the AD_B1 group:

Signal Pin Pad
ENET_1588_EVENT0_OUT P40 GPIO_AD_B1_00
ENET_1588_EVENT0_IN P41 GPIO_AD_B1_01
ENET_1588_EVENT2_OUT P42 GPIO_AD_B1_02
ENET_1588_EVENT2_IN P43 GPIO_AD_B1_03

ENET2 (Ethernet 1 path) has its own 1588 events on B0/B1 pins (P52, P53, P59, etc.).

Analog Interface Design

ADC (Analog-to-Digital Converter)

The i.MX RT1061 has two 12-bit SAR ADCs (ADC1 and ADC2), sharing the VDDA_ADC supply. Reference voltage is the 3.3V supply (no separate VREF input).

Critical Design Constraint:

  • Maximum analog input voltage: 3.3V (rail)
  • Source impedance should be < 1Kohm for accurate readings; buffer high-impedance sources with an op-amp

ADC1/ADC2 Channel Mapping (multiplexed across both ADCs):

Channel Pin Pad
IN5 P40 GPIO_AD_B1_00
IN6 P41 GPIO_AD_B1_01
IN7 P42 GPIO_AD_B1_02
IN8 P43 GPIO_AD_B1_03
IN9 P44 GPIO_AD_B1_04
IN10 P45 GPIO_AD_B1_05
IN11 P46 GPIO_AD_B1_06
IN12 P47 GPIO_AD_B1_07

Pins P40–P47 are shared between ADC1 and ADC2 – either ADC instance can read any channel. P61 (GPIO_AD_B0_14) is also analog-capable as ADC1_IN3.

Layout Recommendations:

  • Route ADC traces away from digital signals and switching power supplies
  • Use a ground guard ring around ADC input traces on the carrier board
  • Keep trace lengths short (< 25 mm recommended)
  • Place anti-aliasing RC filter (100ohm + 100 pF) at the carrier board connector
  • For high-Z sensor sources, add an op-amp buffer (e.g., MCP6009)

Analog Comparators (ACMP)

Four comparator modules with 4 inputs each are available. ACMP inputs share pins with ADC channels:

Comparator Inputs Pins
ACMP1 IN0, IN1, IN3, IN5 P41, P46, P42, P47
ACMP2 IN0, IN1, IN2, IN3 P41, P46, P61, P43
ACMP3 IN0, IN1, IN3 P41, P46, P44
ACMP4 IN0, IN1, IN2, IN3 P41, P46, P40, P45

ACMP inputs are "always-on" – they connect to the analog mux regardless of the pin's ALT function. A pin used for digital and ACMP input simultaneously is supported.

Digital I/O Design

Voltage Domains

Pin Group I/O Voltage Pins
GPIO_EMC_xx 3.3V J1 (P2-P22), J4 (P67-P88)
GPIO_SD_B0_xx 3.3V J2 (P24-P29)
GPIO_AD_B0_xx 3.3V J3 P61
GPIO_AD_B1_xx 3.3V J2 (P40-P44), J3 (P45-P47)
GPIO_B0_xx 3.3V J3 (P50-P55)
GPIO_B1_xx 3.3V J3 (P56-P59)
USB 5V VBUS, 3.3V data J2 (P32-P37)

All user pins operate at 3.3V CMOS levels. Unlike the MODRT1171, there is no 1.8V LPSR domain on this module.

Reset State Defaults

All GPIO pins reset to their GPIO_MUX function (Alt 5) as inputs. Default pull configurations vary by pin group:

Pin Group Default Pull
EMC_xx Keeper (latched state)
SD_B0_xx Keeper
AD_B0_xx Keeper
AD_B1_xx Keeper
B0_xx Keeper / 100K pull-down (boot config pins)
B1_xx Keeper

Boot configuration pins (P52-P55, P58-P59): Have 100K pull-down at reset to set boot mode. Take care if these pins are driven externally during reset – strong drives can override the boot config.

Drive Strength and Slew Rate

All GPIO pads support configurable:

  • Drive strength: 6 levels (R0/1, R0/2, ..., R0/7)
  • Slew rate: Fast / slow
  • Open-drain mode: Available on all pads
  • Pull-up/pull-down: Configurable per pin (22K, 47K, 100K)
  • Hysteresis (Schmitt trigger): Configurable per pin

Tied Pins

Some SOM pins internally connect to two RT1061 pads. When using one of the pair as an output, the other must be set to high-impedance (input) mode to avoid contention.

Primary Pin Tied Pin Notes
P52 P89 (GPIO_B0_02) P89 = LCD_HSYNC, FLEXCAN1_TX, LPSPI4_SOUT
P53 P90 (GPIO_B0_03) P90 = LCD_VSYNC, FLEXCAN1_RX, LPSPI4_SCK
P83 P4 (GPIO_EMC_22) P4 = LPI2C3_SCL, ENET_TX_DATA0
P84 P91 (GPIO_EMC_21) P91 = LPI2C3_SDA, ENET_TX_DATA1

Tied pin pairs are useful when you need to swap functions at runtime – drive one pad as output, leave the other as input.

Communication Interface Routing

UART

The module provides 8 LPUART peripherals:

Recommended Default UART Assignments:

UART TX RX CTS RTS Notes
LPUART2 P42 P43 P40 P41 TX/RX/CTS/RTS on AD_B1
LPUART3 P8 P7 P6 P4 Default boot console; alt P46/P47
LPUART4 P56 P58 P3 P2 Multiple pin options on EMC and B1
LPUART5 P86 P85 P81 P82 TX/RX on EMC_23/24, CTS/RTS on EMC_27/28
LPUART6 P84 P83 P78 P80 TX/RX on EMC_25/26
LPUART7 P77 P76 – – TX/RX only on EMC_31/32
LPUART8 P29 P28 P25 P24 Alt: P70/P69 on EMC_38/39
  • All UARTs output 3.3V CMOS levels
  • For RS-232: Add a level-shifting transceiver (e.g., MAX3243) on the carrier
  • For RS-485: Add a transceiver (e.g., MAX3079) with direction control (DE) tied to TX or driven by GPIO

SPI

Bus SCK SDO SDI PCS0 Notes
LPSPI1 P27 P25 P24 P26 Alt: P82 (SCK), P81 (SDO), P80 (SDI), P78 (PCS0) on EMC
LPSPI2 P14 P16 P18 P15 EMC_00-03
LPSPI4 – P51* P50 P51 B0/B1; P51 SOUT/PCS0, P50 SDI
  • LPSPI4 SCK on tied pin P90 (GPIO_B0_03 ALT3); use only if P53 is high-impedance.

LPSPI3 is not exposed; reserved for on-module flash interface.

I2C

Bus SCL SDA Notes
LPI2C1 P40 P41 AD_B1_00/01
LPI2C3 P27 P26 Alt: P47/P46 on AD_B1_07/06
LPI2C4 P9 P10 EMC_12/11

LPI2C2 is not exposed on user pins.

Design Recommendations:

  • Add 2.2K-4.7K pull-up resistors to 3.3V on the carrier board
  • For long cable runs (> 30 cm), consider an I2C bus extender (e.g., P82B96)
  • Maximum bus capacitance: 400 pF for standard/fast mode

CAN Bus

Bus TX RX Notes
FLEXCAN1 P3 P2 Alt on tied pins P89/P90 (B0_02/03)
FLEXCAN2 P12 P11 EMC_09/10
FLEXCAN3 P72 P71 EMC_36/37; supports CAN-FD
  • All buses support CAN 2.0B; FLEXCAN3 also supports CAN-FD
  • Add a CAN transceiver (e.g., ATA6561, MCP2562FD, TJA1051) on the carrier board
  • Terminate the bus with 120ohm resistors at each end
  • Recommended: 47–100 nF cap from CANH to CANL near the transceiver for noise rejection

USB

Port VBUS D- D+ Notes
USB OTG1 P35 P36 P37 HS/FS/LS, integrated PHY
USB OTG2 P32 P33 P34 HS/FS/LS, integrated PHY

Design Recommendations:

  • Route D+/D- as 90ohm differential pairs
  • Keep trace lengths matched within 0.5 mm
  • Place ESD protection (e.g., EGUARD0503F, PRTR5V0U2X) near the USB connector
  • Add 0.1 uF decoupling on VBUS near the connector
  • For host mode, add a current-limiting switch (e.g., AP22615A) controlled by USB_OTGn_PWR
  • Provide overcurrent feedback to the module on USB_OTGn_OC

SD Card Interface

USDHC1 is available on J2 for connecting an external MicroSD or SD card socket:

Signal Pin Pad Function
CMD P27 GPIO_SD_B0_00 Command line
CLK P26 GPIO_SD_B0_01 Clock (up to 50 MHz)
DATA0 P25 GPIO_SD_B0_02 Data bit 0
DATA1 P24 GPIO_SD_B0_03 Data bit 1
DATA2 P29 GPIO_SD_B0_04 Data bit 2
DATA3 P28 GPIO_SD_B0_05 Data bit 3

Design Recommendations:

  • Place the SD card socket as close to the J2 connector as possible
  • Route all signals as 50ohm controlled impedance
  • Add 33ohm series resistors on CMD, CLK, and all DATA lines for signal integrity
  • Add 47K pull-up resistors on CMD and DATA lines to 3.3V
  • Card detect can use any free GPIO; common choice is a USDHC2_CD_B alt (e.g., P43, P69)

Layout Guidelines

Carrier Board Connector Placement

  • Module headers are 11x2, 0.1" (2.54 mm) pitch &ndash; four total (J1, J2, J3, J4) - Each header is approximately 28 mm long; allow 30 mm clearance with mating sockets - Module dimensions: 1.50" x 2.65" (38.1 mm x 67.3 mm) - Allow 5 mm clearance below the module for airflow @subsection autotoc_md500 Signal Integrity - <strong>USB differential pairs:</strong> Route as 90ohm differential, length-matched within 0.5 mm - <strong>Ethernet 0 differential pairs (P63-P66):</strong> Route as 100ohm differential, length-matched within 5 mm - <strong>Ethernet 1 RMII signals:</strong> Length-match TX and RX bundles separately; keep clock < 100 mm - <strong>SD card signals:</strong> Route as 50ohm, length-matched within 5 mm - <strong>High-speed digital (SPI, I2S):</strong> Keep trace lengths under 100 mm - <strong>Analog (ADC inputs):</strong> Route away from switching supplies; use ground guard traces @subsection autotoc_md501 Thermal Considerations - The module dissipates 0.9&ndash;1.2 W depending on Ethernet configuration and CPU load - Ensure adequate airflow across the module surface - For enclosed designs at +85C ambient, consider a small heatsink on the i.MX RT1061 - Module mounting can use the connector pin retention; no dedicated mounting holes are provided @subsection autotoc_md502 EMI/EMC - Connect all module ground pins to a solid ground plane - Place ferrite beads (e.g., BLM18PG221SN1D, 220ohm @ 100 MHz) on power supply inputs - Keep USB and Ethernet traces short and well-shielded - For Ethernet 0, the on-module PHY's MDIO clock can radiate &ndash; keep MDIO trace short - Use common-mode chokes on Ethernet connections external to the module <hr> @section autotoc_md504 Appendix A: Pin-to-Peripheral Quick Reference @subsection autotoc_md505 Pins Reserved by Module (Do Not Use) <table class="markdownTable"> <tr class="markdownTableHead"> <th class="markdownTableHeadNone"> Pins

Function

Notes

Internal

SDRAM bus (16-bit)

On-module 32 MB SDRAM

Internal

FlexSPI Flash

On-module 8 MB QuadSPI flash

Internal

Ethernet 0 PHY

Integrated KSZ8081-equivalent PHY

P61–P66

Ethernet 0 differential pairs + LEDs

Routed to PHY; cannot be repurposed

Pins Available for General GPIO

Any pin not in the reserved list above can be configured as GPIO. Total available GPIO: 82 pins (88 user pins minus 6 dedicated Ethernet 0 pins).