NetBurner 3.5.7
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Clock Module Example

Example Path: examples/PlatformSpecific/SOMRT1061/ClockModule

Demonstrates the Clock Control Module (CCM) for the SOMRT1061 platform

Location: examples/PlatformSpecific/SOMRT1061/ClockModule

Supported Platforms

  • SOMRT1061

Overview

The Clock Control Module (CCM) generates and controls clocks to the various modules in the design and manages low power modes. This example enables, sets, and displays the available clock sources for the SOMRT1061 platform.

The CCM uses available clock sources to generate clock roots and includes separate dividers to control generation of core and bus root clocks (AXI, AHB, IPG).

Key Features

Feature Description
Clock Configuration Sets external oscillator and RTC crystal
Clock Speed Display Reports all major clock frequencies
Clock Root Enumeration Lists all peripheral clock root frequencies
Visual Feedback LED blink at 2Hz to indicate operation

Clock Architecture

AMBA Background

AMBA (Arm Advanced Microcontroller Bus Architecture) is an open-standard, on-chip interconnect specification for the connection and management of functional blocks in system-on-a-chip (SoC) designs. AMBA was introduced by Arm in 1996. The first AMBA buses were:

  • Advanced System Bus (ASB)
  • Advanced Peripheral Bus (APB)

Clock Types

IPG Clock (IPBus Global Clock)

The IPG clock drives the AHB to IP Bridge (AIPSTZ); the IPBus drives chip-specific peripherals

The AIPS bridge serves as a protocol translator between the AHB system bus and the IPbus. The AHB to IP bridge is the interface between the AHB and on-chip IPS peripherals, which are sub-blocks containing readable/writable control and status registers.

The AHB master reads and writes these registers through the AIPSTZ. The bridge generates:

  • Block enables
  • Block address
  • Transfer attributes
  • Byte enables
  • Write data as inputs to the IPS peripherals

The bridge captures read data from the IPS interface and drives it on the AHB.

Each bridge that connects to the IPS (or peripherals) is referred to as AIPS. The chip has several separate AIPS modules, and peripherals are grouped and assigned under each AIPS block.

AHB Clock (AMBA High-performance Bus)

The AHB clock drives the high-performance system bus used for high-speed communication between the CPU and high-bandwidth peripherals.

Clock Hierarchy

+------------------+
| External OSC |
| (24 MHz) |
+--------+---------+
|
v
+------------------+
| Clock Control |
| Module (CCM) |
+--------+---------+
|
+---------------+---------------+
| | |
v v v
+--------+ +--------+ +--------+
| AXI | | AHB | | IPG |
| Clock | | Clock | | Clock |
| Root | | Root | | Root |
+---+----+ +---+----+ +---+----+
| | |
v v v
+------+------+ +-----+-----+ +------+------+
| CPU Core | | AHB Bus | | Peripherals |
| (528 MHz) | | | | (FlexPWM, |
| | | | | UART, etc) |
+-------------+ +-----------+ +-------------+
SEMC_AddrMux_t::Bus
@ Bus
Non-multiplexed bus mode (write only). Separate address and data buses. Reads are performed as AD-Mux...

Code Structure

Main Components

The example consists of three main functions:

displayClockSpeeds()

Reports all major clock frequencies and clock root frequencies:

Clock Type Description
Ext OSC External oscillator frequency (24 MHz)
CPU CPU core clock frequency
AHB AHB bus clock frequency
IPG IPG bus clock and peripheral clock
PER Peripheral clock frequency
SEMC SDRAM controller clock frequency

Clock roots enumerated:

  • kCLOCK_Usdhc1ClkRoot / kCLOCK_Usdhc2ClkRoot
  • kCLOCK_FlexspiClkRoot / kCLOCK_Flexspi2ClkRoot
  • kCLOCK_CsiClkRoot
  • kCLOCK_LpspiClkRoot
  • kCLOCK_TraceClkRoot
  • kCLOCK_Sai1ClkRoot / kCLOCK_Sai2ClkRoot / kCLOCK_Sai3ClkRoot
  • kCLOCK_Lpi2cClkRoot
  • kCLOCK_CanClkRoot
  • kCLOCK_UartClkRoot
  • kCLOCK_LcdifClkRoot
  • kCLOCK_SpdifClkRoot
  • kCLOCK_Flexio1ClkRoot / kCLOCK_Flexio2ClkRoot

ledBlink()

Toggles LED0 (PIN_78_GPIO4_IO30) at 2Hz to provide visual feedback that the application is running.

UserMain()

Main entry point that:

  1. Initializes the NetBurner system
  2. Configures crystal frequencies (24 MHz OSC, 32 KHz RTC)
  3. Displays all clock speeds to serial console
  4. Enters main loop blinking LED at 2Hz

Clock Configuration

CLOCK_SetXtalFreq(24); // OSC is 24MHz. 88x multiplier provides 528MHz System Clock
CLOCK_SetRtcXtalFreq(32); // RTC crystal is 32KHz

The 24 MHz external oscillator is multiplied by 88 to generate the 528 MHz system clock.

Hardware Requirements

Development Board

  • SOMRT1061 Development Kit

LED Connections

LED Pin GPIO
LED0 PIN_78_GPIO4_IO30 Used for blink
LED1 PIN_21_GPIO4_IO06 Not used in example
LED2 PIN_75_GPIO3_IO19 Not used in example
LED3 PIN_74_GPIO3_IO20 Not used in example

Serial Connection

Connect a serial terminal to the development board:

  • Baud rate: 115200
  • Data bits: 8
  • Parity: None
  • Stop bits: 1
Warning
The fsl_ files use the assert() debug function to test values. If an assert fails, an error message is displayed on the serial port and the system is halted. Be sure to connect a serial terminal program to watch for any error messages.

Expected Output

Upon startup, the serial console will display:

Running SOMRT1061 Clock Module
Ext OSC: 24 MHz
CPU: 528 MHz
AHB: 132 MHz
IPG: 66 MHz, Peripheral Clock: 66 MHz
PER: 24 MHz
SEMC: 132 MHz
Running SOMRT1061 Clock Module
Ext OSC: 24 MHz
CPU: 528 MHz
AHB: 528 MHz
IPG: 132 MHz, Peripheral Clock: 528 MHz
PER: 24 MHz
SEMC: 176 MHz
CLOCK ROOT FREQ
kCLOCK_Usdhc1ClkRoot 198 MHz
kCLOCK_Usdhc2ClkRoot 198 MHz
kCLOCK_FlexspiClkRoot 315 MHz
kCLOCK_Flexspi2ClkRoot 45 MHz
kCLOCK_CsiClkRoot 12 MHz
kCLOCK_LpspiClkRoot 132 MHz
kCLOCK_TraceClkRoot 99 MHz
kCLOCK_Sai1ClkRoot 40 MHz
kCLOCK_Sai2ClkRoot 40 MHz
kCLOCK_Sai3ClkRoot 40 MHz
kCLOCK_Lpi2cClkRoot 60 MHz
kCLOCK_LcdifClkRoot 29 MHz
kCLOCK_SpdifClkRoot 30 MHz
kCLOCK_Flexio1ClkRoot 30 MHz
kCLOCK_Flexio2ClkRoot 30 MHz

LED0 will blink at 2Hz (500ms on, 500ms off).

API Reference

Clock Functions Used

The example uses the following functions from fsl_clock.h:

Function Description
CLOCK_SetXtalFreq() Set external crystal oscillator frequency
CLOCK_SetRtcXtalFreq() Set RTC crystal oscillator frequency
CLOCK_GetOscFreq() Get external oscillator frequency
CLOCK_GetCpuClkFreq() Get CPU clock frequency
CLOCK_GetAhbFreq() Get AHB bus frequency
CLOCK_GetIpgFreq() Get IPG bus frequency
CLOCK_GetPeriphClkFreq() Get peripheral clock frequency
CLOCK_GetPerClkFreq() Get PER clock frequency
CLOCK_GetSemcFreq() Get SEMC (SDRAM controller) frequency
CLOCK_GetClockRootFreq() Get specific clock root frequency

Required Headers

#include <predef.h>
#include <stdio.h>
#include <init.h>
#include <sim.h>
#include <nbrtos.h>
#include <iosys.h>
#include <pins.h>
#include <cpu_pins.h>
#include <string.h>
#include "fsl_clock.h"
Note
All fsl_ MCUXpresso files are located in: \nburn\arch\cortex-m7\cpu\MIMXRT10xx\include

Usage Notes

PWM Clock Source

For applications using FlexPWM, the IPG clock is the source:

#define PWM_SRC_CLK_FREQ CLOCK_GetFreq(kCLOCK_IpgClk)

Timing Considerations

  • The example uses a 500ms delay (TICKS_PER_SECOND / 2) for LED blinking
  • Clock speeds are displayed once at startup
  • The main loop runs continuously

Extending the Example

To modify clock speeds or add additional clock monitoring:

  1. Reference the i.MX RT1061 Reference Manual for clock tree details
  2. Use fsl_clock.h functions to read or modify clock configurations
  3. Be aware that changing core clocks may require adjusting wait states and voltage regulators

Troubleshooting

Issue Solution
LED not blinking Check LED0 connection on PIN_78_GPIO4_IO30
No serial output Verify serial terminal settings (115200 8N1)
Assert message Review serial output for specific error
Incorrect frequencies Ensure crystal oscillators are correct values

References

  • i.MX RT1061 Reference Manual - Clock Control Module (CCM) chapter
  • NXP MCUXpresso SDK Documentation
  • AMBA Bus Specification (ARM)
  • NetBurner fsl_clock.h API documentation

Related Examples

  • GPIO examples for additional LED control
  • Timer examples for precision timing
  • FlexPWM examples for PWM clock usage