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fsl_clock.h
1/*
2 * Copyright 2018 -2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _FSL_CLOCK_H_
9#define _FSL_CLOCK_H_
10
11#include <assert.h>
12#include <sim.h>
13
14/* @addtogroup clock */
15/* @{ */
16
17/*~ @file */
18
19/*******************************************************************************
20 * Configurations
21 ******************************************************************************/
22
23/*~ @brief Configure whether driver controls clock
24 *
25 * When set to 0, peripheral drivers will enable clock in initialize function
26 * and disable clock in de-initialize function. When set to 1, peripheral
27 * driver will not control the clock, application could control the clock out of
28 * the driver.
29 *
30 * @note All drivers share this feature switcher. If it is set to 1, application
31 * should handle clock enable and disable for all drivers.
32 */
33#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
34#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
35#endif
36
37/*******************************************************************************
38 * Definitions
39 ******************************************************************************/
40
41/*~ @name Driver version */
43/*~ @brief CLOCK driver version 2.4.0. */
44#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
45
46/* Definition for delay API in clock driver, users can redefine it to the real application. */
47#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
48#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (600000000UL)
49#endif
50
51/* analog pll definition */
52#define CCM_ANALOG_PLL_BYPASS_SHIFT (16U)
53#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U)
54#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)
55
58/*~
59 * @brief CCM registers offset.
60 */
61#define CCSR_OFFSET 0x0C
62#define CBCDR_OFFSET 0x14
63#define CBCMR_OFFSET 0x18
64#define CSCMR1_OFFSET 0x1C
65#define CSCMR2_OFFSET 0x20
66#define CSCDR1_OFFSET 0x24
67#define CDCDR_OFFSET 0x30
68#define CSCDR2_OFFSET 0x38
69#define CSCDR3_OFFSET 0x3C
70#define CACRR_OFFSET 0x10
71#define CS1CDR_OFFSET 0x28
72#define CS2CDR_OFFSET 0x2C
73
74/*~
75 * @brief CCM Analog registers offset.
76 */
77#define PLL_ARM_OFFSET 0x00
78#define PLL_SYS_OFFSET 0x30
79#define PLL_USB1_OFFSET 0x10
80#define PLL_AUDIO_OFFSET 0x70
81#define PLL_VIDEO_OFFSET 0xA0
82#define PLL_ENET_OFFSET 0xE0
83#define PLL_USB2_OFFSET 0x20
84
85#define CCM_TUPLE(reg, shift, mask, busyShift) \
86 (int)(((reg)&0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))
87#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((uint32_t)(tuple)&0xFFU))))
88#define CCM_TUPLE_SHIFT(tuple) ((((uint32_t)tuple) >> 8U) & 0x1FU)
89#define CCM_TUPLE_MASK(tuple) \
90 ((uint32_t)((((uint32_t)(tuple) >> 13U) & 0x1FFFU) << (((((uint32_t)tuple) >> 8U) & 0x1FU))))
91#define CCM_TUPLE_BUSY_SHIFT(tuple) ((((uint32_t)tuple) >> 26U) & 0x3FU)
92
93#define CCM_NO_BUSY_WAIT (0x20U)
94
95/*~
96 * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields.
97 */
98#define CCM_ANALOG_TUPLE(reg, shift) ((((reg)&0xFFFU) << 16U) | (shift))
99#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)tuple) & 0x1FU)
100#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \
101 (*((volatile uint32_t *)((uint32_t)(base) + (((uint32_t)(tuple) >> 16U) & 0xFFFU) + (off))))
102#define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)
103
104/* Definition for ERRATA 50235 check */
105#if (defined(FSL_FEATURE_CCM_HAS_ERRATA_50235) && FSL_FEATURE_CCM_HAS_ERRATA_50235)
106#define CAN_CLOCK_CHECK_NO_AFFECTS \
107 ((CCM_CSCMR2_CAN_CLK_SEL(2U) != (CCM->CSCMR2 & CCM_CSCMR2_CAN_CLK_SEL_MASK)) || \
108 (CCM_CCGR5_CG12(0) != (CCM->CCGR5 & CCM_CCGR5_CG12_MASK)))
109#endif /* FSL_FEATURE_CCM_HAS_ERRATA_50235 */
110
111/*~
112 * @brief clock1PN frequency.
113 */
114#define CLKPN_FREQ 0U
115
116/*~ @brief External XTAL (24M OSC/SYSOSC) clock frequency.
117 *
118 * The XTAL (24M OSC/SYSOSC) clock frequency in Hz, when the clock is setup, use the
119 * function CLOCK_SetXtalFreq to set the value in to clock driver. For example,
120 * if XTAL is 24MHz,
121 * @code
122 * CLOCK_InitExternalClk(false);
123 * CLOCK_SetXtalFreq(240000000);
124 * @endcode
125 */
126extern volatile uint32_t g_xtalFreq;
127
128/*~ @brief External RTC XTAL (32K OSC) clock frequency.
129 *
130 * The RTC XTAL (32K OSC) clock frequency in Hz, when the clock is setup, use the
131 * function CLOCK_SetRtcXtalFreq to set the value in to clock driver.
132 */
133extern volatile uint32_t g_rtcXtalFreq;
134
135/* For compatible with other platforms */
136#define CLOCK_SetXtal0Freq CLOCK_SetXtalFreq
137#define CLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreq
138
139/*~ @brief Clock ip name array for ADC. */
140#define ADC_CLOCKS \
141 { \
142 kCLOCK_IpInvalid, kCLOCK_Adc1, kCLOCK_Adc2 \
143 }
144
145/*~ @brief Clock ip name array for AOI. */
146#define AOI_CLOCKS \
147 { \
148 kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2 \
149 }
150
151/*~ @brief Clock ip name array for BEE. */
152#define BEE_CLOCKS \
153 { \
154 kCLOCK_Bee \
155 }
156
157/*~ @brief Clock ip name array for CMP. */
158#define CMP_CLOCKS \
159 { \
160 kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 \
161 }
162
163/*~ @brief Clock ip name array for CSI. */
164#define CSI_CLOCKS \
165 { \
166 kCLOCK_Csi \
167 }
168
169/*~ @brief Clock ip name array for DCDC. */
170#define DCDC_CLOCKS \
171 { \
172 kCLOCK_Dcdc \
173 }
174
175/*~ @brief Clock ip name array for DCP. */
176#define DCP_CLOCKS \
177 { \
178 kCLOCK_Dcp \
179 }
180
181/*~ @brief Clock ip name array for DMAMUX_CLOCKS. */
182#define DMAMUX_CLOCKS \
183 { \
184 kCLOCK_Dma \
185 }
186
187/*~ @brief Clock ip name array for DMA. */
188#define EDMA_CLOCKS \
189 { \
190 kCLOCK_Dma \
191 }
192
193/*~ @brief Clock ip name array for ENC. */
194#define ENC_CLOCKS \
195 { \
196 kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2, kCLOCK_Enc3, kCLOCK_Enc4 \
197 }
198
199/*~ @brief Clock ip name array for ENET. */
200#define ENET_CLOCKS \
201 { \
202 kCLOCK_Enet, kCLOCK_IpInvalid, kCLOCK_Enet2 \
203 }
204
205/*~ @brief Clock ip name array for EWM. */
206#define EWM_CLOCKS \
207 { \
208 kCLOCK_Ewm0 \
209 }
210
211/*~ @brief Clock ip name array for FLEXCAN. */
212#define FLEXCAN_CLOCKS \
213 { \
214 kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2, kCLOCK_Can3 \
215 }
216
217/*~ @brief Clock ip name array for FLEXCAN Peripheral clock. */
218#define FLEXCAN_PERIPH_CLOCKS \
219 { \
220 kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S, kCLOCK_Can3S \
221 }
222
223/*~ @brief Clock ip name array for FLEXIO. */
224#define FLEXIO_CLOCKS \
225 { \
226 kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2, kCLOCK_Flexio3 \
227 }
228
229/*~ @brief Clock ip name array for FLEXRAM. */
230#define FLEXRAM_CLOCKS \
231 { \
232 kCLOCK_FlexRam \
233 }
234
235/*~ @brief Clock ip name array for FLEXSPI. */
236#define FLEXSPI_CLOCKS \
237 { \
238 kCLOCK_FlexSpi, kCLOCK_IpInvalid, kCLOCK_FlexSpi2 \
239 }
240
241/*~ @brief Clock ip name array for FLEXSPI EXSC. */
242#define FLEXSPI_EXSC_CLOCKS \
243 { \
244 kCLOCK_FlexSpiExsc \
245 }
246
247/*~ @brief Clock ip name array for GPIO. */
248#define GPIO_CLOCKS \
249 { \
250 kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \
251 }
252
253/*~ @brief Clock ip name array for GPT. */
254#define GPT_CLOCKS \
255 { \
256 kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 \
257 }
258
259/*~ @brief Clock ip name array for KPP. */
260#define KPP_CLOCKS \
261 { \
262 kCLOCK_Kpp \
263 }
264
265/*~ @brief Clock ip name array for LCDIF. */
266#define LCDIF_CLOCKS \
267 { \
268 kCLOCK_Lcd \
269 }
270
271/*~ @brief Clock ip name array for LCDIF PIXEL. */
272#define LCDIF_PERIPH_CLOCKS \
273 { \
274 kCLOCK_LcdPixel \
275 }
276
277/*~ @brief Clock ip name array for LPI2C. */
278#define LPI2C_CLOCKS \
279 { \
280 kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4 \
281 }
282
283/*~ @brief Clock ip name array for LPSPI. */
284#define LPSPI_CLOCKS \
285 { \
286 kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4 \
287 }
288
289/*~ @brief Clock ip name array for LPUART. */
290#define LPUART_CLOCKS \
291 { \
292 kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, \
293 kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8 \
294 }
295
296/*~ @brief Clock ip name array for MQS. */
297#define MQS_CLOCKS \
298 { \
299 kCLOCK_Mqs \
300 }
301
302/*~ @brief Clock ip name array for OCRAM EXSC. */
303#define OCRAM_EXSC_CLOCKS \
304 { \
305 kCLOCK_OcramExsc \
306 }
307
308/*~ @brief Clock ip name array for PIT. */
309#define PIT_CLOCKS \
310 { \
311 kCLOCK_Pit \
312 }
313
314/*~ @brief Clock ip name array for PWM. */
315#define PWM_CLOCKS \
316 { \
317 {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid}, \
318 {kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1}, \
319 {kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2}, \
320 {kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3}, \
321 { \
322 kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4 \
323 } \
324 }
325
326/*~ @brief Clock ip name array for PXP. */
327#define PXP_CLOCKS \
328 { \
329 kCLOCK_Pxp \
330 }
331
332/*~ @brief Clock ip name array for RTWDOG. */
333#define RTWDOG_CLOCKS \
334 { \
335 kCLOCK_Wdog3 \
336 }
337
338/*~ @brief Clock ip name array for SAI. */
339#define SAI_CLOCKS \
340 { \
341 kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 \
342 }
343
344/*~ @brief Clock ip name array for SEMC. */
345#define SEMC_CLOCKS \
346 { \
347 kCLOCK_Semc \
348 }
349
350/*~ @brief Clock ip name array for SEMC EXSC. */
351#define SEMC_EXSC_CLOCKS \
352 { \
353 kCLOCK_SemcExsc \
354 }
355
356/*~ @brief Clock ip name array for QTIMER. */
357#define TMR_CLOCKS \
358 { \
359 kCLOCK_IpInvalid, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \
360 }
361
362/*~ @brief Clock ip name array for TRNG. */
363#define TRNG_CLOCKS \
364 { \
365 kCLOCK_Trng \
366 }
367
368/*~ @brief Clock ip name array for TSC. */
369#define TSC_CLOCKS \
370 { \
371 kCLOCK_Tsc \
372 }
373
374/*~ @brief Clock ip name array for WDOG. */
375#define WDOG_CLOCKS \
376 { \
377 kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 \
378 }
379
380/*~ @brief Clock ip name array for USDHC. */
381#define USDHC_CLOCKS \
382 { \
383 kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \
384 }
385
386/*~ @brief Clock ip name array for SPDIF. */
387#define SPDIF_CLOCKS \
388 { \
389 kCLOCK_Spdif \
390 }
391
392/*~ @brief Clock ip name array for XBARA. */
393#define XBARA_CLOCKS \
394 { \
395 kCLOCK_Xbar1 \
396 }
397
398/*~ @brief Clock ip name array for XBARB. */
399#define XBARB_CLOCKS \
400 { \
401 kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, kCLOCK_Xbar3 \
402 }
403
404#define CLOCK_SOURCE_NONE (0xFFU)
405
406#define CLOCK_ROOT_SOUCE \
407 { \
408 {kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, kCLOCK_NoneName, \
409 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* USDHC1 Clock Root. */ \
410 {kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, kCLOCK_NoneName, \
411 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* USDHC2 Clock Root. */ \
412 {kCLOCK_SemcClk, kCLOCK_Usb1SwClk, kCLOCK_SysPllPfd2Clk, \
413 kCLOCK_Usb1PllPfd0Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* FLEXSPI Clock Root. */ \
414 {kCLOCK_SysPllPfd2Clk, kCLOCK_Usb1PllPfd0Clk, kCLOCK_Usb1PllPfd1Clk, \
415 kCLOCK_SysPllClk, kCLOCK_NoneName, kCLOCK_NoneName}, /* FLEXSPI2 Clock Root. */ \
416 {kCLOCK_OscClk, kCLOCK_SysPllPfd2Clk, kCLOCK_Usb1Sw120MClk, \
417 kCLOCK_Usb1PllPfd1Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* CSI Clock Root. */ \
418 {kCLOCK_Usb1PllPfd1Clk, kCLOCK_Usb1PllPfd0Clk, kCLOCK_SysPllClk, \
419 kCLOCK_SysPllPfd2Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* LPSPI Clock Root. */ \
420 {kCLOCK_SysPllClk, kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, \
421 kCLOCK_SysPllPfd1Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* TRACE Clock Root */ \
422 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, kCLOCK_AudioPllClk, \
423 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* SAI1 Clock Root */ \
424 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, kCLOCK_AudioPllClk, \
425 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* SAI2 Clock Root */ \
426 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, kCLOCK_AudioPllClk, \
427 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* SAI3 Clock Root */ \
428 {kCLOCK_Usb1Sw60MClk, kCLOCK_OscClk, kCLOCK_NoneName, \
429 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* LPI2C Clock Root */ \
430 {kCLOCK_Usb1Sw60MClk, kCLOCK_OscClk, kCLOCK_Usb1Sw80MClk, \
431 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* CAN Clock Root. */ \
432 {kCLOCK_Usb1Sw80MClk, kCLOCK_OscClk, kCLOCK_NoneName, \
433 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* UART Clock Root */ \
434 {kCLOCK_SysPllClk, kCLOCK_Usb1PllPfd3Clk, kCLOCK_VideoPllClk, \
435 kCLOCK_SysPllPfd0Clk, kCLOCK_SysPllPfd1Clk, kCLOCK_Usb1PllPfd1Clk}, /* LCDIF Clock Root */ \
436 {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, \
437 kCLOCK_Usb1SwClk, kCLOCK_NoneName, kCLOCK_NoneName}, /* SPDIF0 Clock Root */ \
438 {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, \
439 kCLOCK_Usb1SwClk, kCLOCK_NoneName, kCLOCK_NoneName}, /* FLEXIO1 Clock Root */ \
440 {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, \
441 kCLOCK_Usb1PllClk, kCLOCK_NoneName, kCLOCK_NoneName}, /* FLEXIO2 Clock ROOT */ \
442 }
443
444#define CLOCK_ROOT_MUX_TUPLE \
445 { \
446 kCLOCK_Usdhc1Mux, kCLOCK_Usdhc2Mux, kCLOCK_FlexspiMux, kCLOCK_Flexspi2Mux, kCLOCK_CsiMux, kCLOCK_LpspiMux, \
447 kCLOCK_TraceMux, kCLOCK_Sai1Mux, kCLOCK_Sai2Mux, kCLOCK_Sai3Mux, kCLOCK_Lpi2cMux, kCLOCK_CanMux, \
448 kCLOCK_UartMux, kCLOCK_LcdifPreMux, kCLOCK_SpdifMux, kCLOCK_Flexio1Mux, kCLOCK_Flexio2Mux, \
449 }
450
451#define CLOCK_ROOT_NONE_PRE_DIV 0UL
452
453#define CLOCK_ROOT_DIV_TUPLE \
454 { \
455 {kCLOCK_NonePreDiv, kCLOCK_Usdhc1Div}, {kCLOCK_NonePreDiv, kCLOCK_Usdhc2Div}, \
456 {kCLOCK_NonePreDiv, kCLOCK_FlexspiDiv}, {kCLOCK_NonePreDiv, kCLOCK_Flexspi2Div}, \
457 {kCLOCK_NonePreDiv, kCLOCK_CsiDiv}, {kCLOCK_NonePreDiv, kCLOCK_LpspiDiv}, \
458 {kCLOCK_NonePreDiv, kCLOCK_TraceDiv}, {kCLOCK_Sai1PreDiv, kCLOCK_Sai1Div}, \
459 {kCLOCK_Sai2PreDiv, kCLOCK_Sai2Div}, {kCLOCK_Sai3PreDiv, kCLOCK_Sai3Div}, \
460 {kCLOCK_NonePreDiv, kCLOCK_Lpi2cDiv}, {kCLOCK_NonePreDiv, kCLOCK_CanDiv}, \
461 {kCLOCK_NonePreDiv, kCLOCK_UartDiv}, {kCLOCK_LcdifPreDiv, kCLOCK_LcdifDiv}, \
462 {kCLOCK_Spdif0PreDiv, kCLOCK_Spdif0Div}, {kCLOCK_Flexio1PreDiv, kCLOCK_Flexio1Div}, \
463 {kCLOCK_Flexio2PreDiv, kCLOCK_Flexio2Div}, \
464 }
465
466/*~ @brief Clock name used to get clock frequency. */
467typedef enum _clock_name
468{
469 kCLOCK_CpuClk = 0x0U, /*~< CPU clock */
470 kCLOCK_AhbClk = 0x1U, /*~< AHB clock */
471 kCLOCK_SemcClk = 0x2U, /*~< SEMC clock */
472 kCLOCK_IpgClk = 0x3U, /*~< IPG clock */
473 kCLOCK_PerClk = 0x4U, /*~< PER clock */
474
475 kCLOCK_OscClk = 0x5U, /*~< OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL]. */
476 kCLOCK_RtcClk = 0x6U, /*~< RTC clock. (RTCCLK) */
477
478 kCLOCK_ArmPllClk = 0x7U, /*~< ARMPLLCLK. */
479
480 kCLOCK_Usb1PllClk = 0x8U, /*~< USB1PLLCLK. */
481 kCLOCK_Usb1PllPfd0Clk = 0x9U, /*~< USB1PLLPDF0CLK. */
482 kCLOCK_Usb1PllPfd1Clk = 0xAU, /*~< USB1PLLPFD1CLK. */
483 kCLOCK_Usb1PllPfd2Clk = 0xBU, /*~< USB1PLLPFD2CLK. */
484 kCLOCK_Usb1PllPfd3Clk = 0xCU, /*~< USB1PLLPFD3CLK. */
485 kCLOCK_Usb1SwClk = 0x18U, /*~< USB1PLLSWCLK */
486 kCLOCK_Usb1Sw120MClk = 0x19U, /*~< USB1PLLSw120MCLK */
487 kCLOCK_Usb1Sw60MClk = 0x1AU, /*~< USB1PLLSw60MCLK */
488 kCLOCK_Usb1Sw80MClk = 0x1BU, /*~< USB1PLLSw80MCLK */
489
490 kCLOCK_Usb2PllClk = 0xDU, /*~< USB2PLLCLK. */
491
492 kCLOCK_SysPllClk = 0xEU, /*~< SYSPLLCLK. */
493 kCLOCK_SysPllPfd0Clk = 0xFU, /*~< SYSPLLPDF0CLK. */
494 kCLOCK_SysPllPfd1Clk = 0x10U, /*~< SYSPLLPFD1CLK. */
495 kCLOCK_SysPllPfd2Clk = 0x11U, /*~< SYSPLLPFD2CLK. */
496 kCLOCK_SysPllPfd3Clk = 0x12U, /*~< SYSPLLPFD3CLK. */
497
498 kCLOCK_EnetPll0Clk = 0x13U, /*~< Enet PLLCLK ref_enetpll0. */
499 kCLOCK_EnetPll1Clk = 0x14U, /*~< Enet PLLCLK ref_enetpll1. */
500 kCLOCK_EnetPll2Clk = 0x15U, /*~< Enet PLLCLK ref_enetpll2. */
501
502 kCLOCK_AudioPllClk = 0x16U, /*~< Audio PLLCLK. */
503 kCLOCK_VideoPllClk = 0x17U, /*~< Video PLLCLK. */
504
505 kCLOCK_NoneName = CLOCK_SOURCE_NONE, /*~< None Clock Name. */
506} clock_name_t;
507
508#define kCLOCK_CoreSysClk kCLOCK_CpuClk /*~< For compatible with other platforms without CCM. */
509#define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq /*~< For compatible with other platforms without CCM. */
510
511/*~
512 * @brief CCM CCGR gate control for each module independently.
513 */
514typedef enum _clock_ip_name
515{
516 kCLOCK_IpInvalid = -1,
517
518 /* CCM CCGR0 */
519 kCLOCK_Aips_tz1 = (0U << 8U) | CCM_CCGR0_CG0_SHIFT, /*~< CCGR0, CG0 */
520 kCLOCK_Aips_tz2 = (0U << 8U) | CCM_CCGR0_CG1_SHIFT, /*~< CCGR0, CG1 */
521 kCLOCK_Mqs = (0U << 8U) | CCM_CCGR0_CG2_SHIFT, /*~< CCGR0, CG2 */
522 kCLOCK_FlexSpiExsc = (0U << 8U) | CCM_CCGR0_CG3_SHIFT, /*~< CCGR0, CG3 */
523 kCLOCK_Sim_M_Main = (0U << 8U) | CCM_CCGR0_CG4_SHIFT, /*~< CCGR0, CG4 */
524 kCLOCK_Dcp = (0U << 8U) | CCM_CCGR0_CG5_SHIFT, /*~< CCGR0, CG5 */
525 kCLOCK_Lpuart3 = (0U << 8U) | CCM_CCGR0_CG6_SHIFT, /*~< CCGR0, CG6 */
526 kCLOCK_Can1 = (0U << 8U) | CCM_CCGR0_CG7_SHIFT, /*~< CCGR0, CG7 */
527 kCLOCK_Can1S = (0U << 8U) | CCM_CCGR0_CG8_SHIFT, /*~< CCGR0, CG8 */
528 kCLOCK_Can2 = (0U << 8U) | CCM_CCGR0_CG9_SHIFT, /*~< CCGR0, CG9 */
529 kCLOCK_Can2S = (0U << 8U) | CCM_CCGR0_CG10_SHIFT, /*~< CCGR0, CG10 */
530 kCLOCK_Trace = (0U << 8U) | CCM_CCGR0_CG11_SHIFT, /*~< CCGR0, CG11 */
531 kCLOCK_Gpt2 = (0U << 8U) | CCM_CCGR0_CG12_SHIFT, /*~< CCGR0, CG12 */
532 kCLOCK_Gpt2S = (0U << 8U) | CCM_CCGR0_CG13_SHIFT, /*~< CCGR0, CG13 */
533 kCLOCK_Lpuart2 = (0U << 8U) | CCM_CCGR0_CG14_SHIFT, /*~< CCGR0, CG14 */
534 kCLOCK_Gpio2 = (0U << 8U) | CCM_CCGR0_CG15_SHIFT, /*~< CCGR0, CG15 */
535
536 /* CCM CCGR1 */
537 kCLOCK_Lpspi1 = (1U << 8U) | CCM_CCGR1_CG0_SHIFT, /*~< CCGR1, CG0 */
538 kCLOCK_Lpspi2 = (1U << 8U) | CCM_CCGR1_CG1_SHIFT, /*~< CCGR1, CG1 */
539 kCLOCK_Lpspi3 = (1U << 8U) | CCM_CCGR1_CG2_SHIFT, /*~< CCGR1, CG2 */
540 kCLOCK_Lpspi4 = (1U << 8U) | CCM_CCGR1_CG3_SHIFT, /*~< CCGR1, CG3 */
541 kCLOCK_Adc2 = (1U << 8U) | CCM_CCGR1_CG4_SHIFT, /*~< CCGR1, CG4 */
542 kCLOCK_Enet = (1U << 8U) | CCM_CCGR1_CG5_SHIFT, /*~< CCGR1, CG5 */
543 kCLOCK_Pit = (1U << 8U) | CCM_CCGR1_CG6_SHIFT, /*~< CCGR1, CG6 */
544 kCLOCK_Aoi2 = (1U << 8U) | CCM_CCGR1_CG7_SHIFT, /*~< CCGR1, CG7 */
545 kCLOCK_Adc1 = (1U << 8U) | CCM_CCGR1_CG8_SHIFT, /*~< CCGR1, CG8 */
546 kCLOCK_SemcExsc = (1U << 8U) | CCM_CCGR1_CG9_SHIFT, /*~< CCGR1, CG9 */
547 kCLOCK_Gpt1 = (1U << 8U) | CCM_CCGR1_CG10_SHIFT, /*~< CCGR1, CG10 */
548 kCLOCK_Gpt1S = (1U << 8U) | CCM_CCGR1_CG11_SHIFT, /*~< CCGR1, CG11 */
549 kCLOCK_Lpuart4 = (1U << 8U) | CCM_CCGR1_CG12_SHIFT, /*~< CCGR1, CG12 */
550 kCLOCK_Gpio1 = (1U << 8U) | CCM_CCGR1_CG13_SHIFT, /*~< CCGR1, CG13 */
551 kCLOCK_Csu = (1U << 8U) | CCM_CCGR1_CG14_SHIFT, /*~< CCGR1, CG14 */
552 kCLOCK_Gpio5 = (1U << 8U) | CCM_CCGR1_CG15_SHIFT, /*~< CCGR1, CG15 */
553
554 /* CCM CCGR2 */
555 kCLOCK_OcramExsc = (2U << 8U) | CCM_CCGR2_CG0_SHIFT, /*~< CCGR2, CG0 */
556 kCLOCK_Csi = (2U << 8U) | CCM_CCGR2_CG1_SHIFT, /*~< CCGR2, CG1 */
557 kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT, /*~< CCGR2, CG2 */
558 kCLOCK_Lpi2c1 = (2U << 8U) | CCM_CCGR2_CG3_SHIFT, /*~< CCGR2, CG3 */
559 kCLOCK_Lpi2c2 = (2U << 8U) | CCM_CCGR2_CG4_SHIFT, /*~< CCGR2, CG4 */
560 kCLOCK_Lpi2c3 = (2U << 8U) | CCM_CCGR2_CG5_SHIFT, /*~< CCGR2, CG5 */
561 kCLOCK_Ocotp = (2U << 8U) | CCM_CCGR2_CG6_SHIFT, /*~< CCGR2, CG6 */
562 kCLOCK_Xbar3 = (2U << 8U) | CCM_CCGR2_CG7_SHIFT, /*~< CCGR2, CG7 */
563 kCLOCK_Ipmux1 = (2U << 8U) | CCM_CCGR2_CG8_SHIFT, /*~< CCGR2, CG8 */
564 kCLOCK_Ipmux2 = (2U << 8U) | CCM_CCGR2_CG9_SHIFT, /*~< CCGR2, CG9 */
565 kCLOCK_Ipmux3 = (2U << 8U) | CCM_CCGR2_CG10_SHIFT, /*~< CCGR2, CG10 */
566 kCLOCK_Xbar1 = (2U << 8U) | CCM_CCGR2_CG11_SHIFT, /*~< CCGR2, CG11 */
567 kCLOCK_Xbar2 = (2U << 8U) | CCM_CCGR2_CG12_SHIFT, /*~< CCGR2, CG12 */
568 kCLOCK_Gpio3 = (2U << 8U) | CCM_CCGR2_CG13_SHIFT, /*~< CCGR2, CG13 */
569 kCLOCK_Lcd = (2U << 8U) | CCM_CCGR2_CG14_SHIFT, /*~< CCGR2, CG14 */
570 kCLOCK_Pxp = (2U << 8U) | CCM_CCGR2_CG15_SHIFT, /*~< CCGR2, CG15 */
571
572 /* CCM CCGR3 */
573 kCLOCK_Flexio2 = (3U << 8U) | CCM_CCGR3_CG0_SHIFT, /*~< CCGR3, CG0 */
574 kCLOCK_Lpuart5 = (3U << 8U) | CCM_CCGR3_CG1_SHIFT, /*~< CCGR3, CG1 */
575 kCLOCK_Semc = (3U << 8U) | CCM_CCGR3_CG2_SHIFT, /*~< CCGR3, CG2 */
576 kCLOCK_Lpuart6 = (3U << 8U) | CCM_CCGR3_CG3_SHIFT, /*~< CCGR3, CG3 */
577 kCLOCK_Aoi1 = (3U << 8U) | CCM_CCGR3_CG4_SHIFT, /*~< CCGR3, CG4 */
578 kCLOCK_LcdPixel = (3U << 8U) | CCM_CCGR3_CG5_SHIFT, /*~< CCGR3, CG5 */
579 kCLOCK_Gpio4 = (3U << 8U) | CCM_CCGR3_CG6_SHIFT, /*~< CCGR3, CG6 */
580 kCLOCK_Ewm0 = (3U << 8U) | CCM_CCGR3_CG7_SHIFT, /*~< CCGR3, CG7 */
581 kCLOCK_Wdog1 = (3U << 8U) | CCM_CCGR3_CG8_SHIFT, /*~< CCGR3, CG8 */
582 kCLOCK_FlexRam = (3U << 8U) | CCM_CCGR3_CG9_SHIFT, /*~< CCGR3, CG9 */
583 kCLOCK_Acmp1 = (3U << 8U) | CCM_CCGR3_CG10_SHIFT, /*~< CCGR3, CG10 */
584 kCLOCK_Acmp2 = (3U << 8U) | CCM_CCGR3_CG11_SHIFT, /*~< CCGR3, CG11 */
585 kCLOCK_Acmp3 = (3U << 8U) | CCM_CCGR3_CG12_SHIFT, /*~< CCGR3, CG12 */
586 kCLOCK_Acmp4 = (3U << 8U) | CCM_CCGR3_CG13_SHIFT, /*~< CCGR3, CG13 */
587 kCLOCK_Ocram = (3U << 8U) | CCM_CCGR3_CG14_SHIFT, /*~< CCGR3, CG14 */
588 kCLOCK_IomuxcSnvsGpr = (3U << 8U) | CCM_CCGR3_CG15_SHIFT, /*~< CCGR3, CG15 */
589
590 /* CCM CCGR4 */
591 kCLOCK_Iomuxc = (4U << 8U) | CCM_CCGR4_CG1_SHIFT, /*~< CCGR4, CG1 */
592 kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT, /*~< CCGR4, CG2 */
593 kCLOCK_Bee = (4U << 8U) | CCM_CCGR4_CG3_SHIFT, /*~< CCGR4, CG3 */
594 kCLOCK_SimM7 = (4U << 8U) | CCM_CCGR4_CG4_SHIFT, /*~< CCGR4, CG4 */
595 kCLOCK_Tsc = (4U << 8U) | CCM_CCGR4_CG5_SHIFT, /*~< CCGR4, CG5 */
596 kCLOCK_SimM = (4U << 8U) | CCM_CCGR4_CG6_SHIFT, /*~< CCGR4, CG6 */
597 kCLOCK_SimEms = (4U << 8U) | CCM_CCGR4_CG7_SHIFT, /*~< CCGR4, CG7 */
598 kCLOCK_Pwm1 = (4U << 8U) | CCM_CCGR4_CG8_SHIFT, /*~< CCGR4, CG8 */
599 kCLOCK_Pwm2 = (4U << 8U) | CCM_CCGR4_CG9_SHIFT, /*~< CCGR4, CG9 */
600 kCLOCK_Pwm3 = (4U << 8U) | CCM_CCGR4_CG10_SHIFT, /*~< CCGR4, CG10 */
601 kCLOCK_Pwm4 = (4U << 8U) | CCM_CCGR4_CG11_SHIFT, /*~< CCGR4, CG11 */
602 kCLOCK_Enc1 = (4U << 8U) | CCM_CCGR4_CG12_SHIFT, /*~< CCGR4, CG12 */
603 kCLOCK_Enc2 = (4U << 8U) | CCM_CCGR4_CG13_SHIFT, /*~< CCGR4, CG13 */
604 kCLOCK_Enc3 = (4U << 8U) | CCM_CCGR4_CG14_SHIFT, /*~< CCGR4, CG14 */
605 kCLOCK_Enc4 = (4U << 8U) | CCM_CCGR4_CG15_SHIFT, /*~< CCGR4, CG15 */
606
607 /* CCM CCGR5 */
608 kCLOCK_Rom = (5U << 8U) | CCM_CCGR5_CG0_SHIFT, /*~< CCGR5, CG0 */
609 kCLOCK_Flexio1 = (5U << 8U) | CCM_CCGR5_CG1_SHIFT, /*~< CCGR5, CG1 */
610 kCLOCK_Wdog3 = (5U << 8U) | CCM_CCGR5_CG2_SHIFT, /*~< CCGR5, CG2 */
611 kCLOCK_Dma = (5U << 8U) | CCM_CCGR5_CG3_SHIFT, /*~< CCGR5, CG3 */
612 kCLOCK_Kpp = (5U << 8U) | CCM_CCGR5_CG4_SHIFT, /*~< CCGR5, CG4 */
613 kCLOCK_Wdog2 = (5U << 8U) | CCM_CCGR5_CG5_SHIFT, /*~< CCGR5, CG5 */
614 kCLOCK_Aips_tz4 = (5U << 8U) | CCM_CCGR5_CG6_SHIFT, /*~< CCGR5, CG6 */
615 kCLOCK_Spdif = (5U << 8U) | CCM_CCGR5_CG7_SHIFT, /*~< CCGR5, CG7 */
616 kCLOCK_SimMain = (5U << 8U) | CCM_CCGR5_CG8_SHIFT, /*~< CCGR5, CG8 */
617 kCLOCK_Sai1 = (5U << 8U) | CCM_CCGR5_CG9_SHIFT, /*~< CCGR5, CG9 */
618 kCLOCK_Sai2 = (5U << 8U) | CCM_CCGR5_CG10_SHIFT, /*~< CCGR5, CG10 */
619 kCLOCK_Sai3 = (5U << 8U) | CCM_CCGR5_CG11_SHIFT, /*~< CCGR5, CG11 */
620 kCLOCK_Lpuart1 = (5U << 8U) | CCM_CCGR5_CG12_SHIFT, /*~< CCGR5, CG12 */
621 kCLOCK_Lpuart7 = (5U << 8U) | CCM_CCGR5_CG13_SHIFT, /*~< CCGR5, CG13 */
622 kCLOCK_SnvsHp = (5U << 8U) | CCM_CCGR5_CG14_SHIFT, /*~< CCGR5, CG14 */
623 kCLOCK_SnvsLp = (5U << 8U) | CCM_CCGR5_CG15_SHIFT, /*~< CCGR5, CG15 */
624
625 /* CCM CCGR6 */
626 kCLOCK_UsbOh3 = (6U << 8U) | CCM_CCGR6_CG0_SHIFT, /*~< CCGR6, CG0 */
627 kCLOCK_Usdhc1 = (6U << 8U) | CCM_CCGR6_CG1_SHIFT, /*~< CCGR6, CG1 */
628 kCLOCK_Usdhc2 = (6U << 8U) | CCM_CCGR6_CG2_SHIFT, /*~< CCGR6, CG2 */
629 kCLOCK_Dcdc = (6U << 8U) | CCM_CCGR6_CG3_SHIFT, /*~< CCGR6, CG3 */
630 kCLOCK_Ipmux4 = (6U << 8U) | CCM_CCGR6_CG4_SHIFT, /*~< CCGR6, CG4 */
631 kCLOCK_FlexSpi = (6U << 8U) | CCM_CCGR6_CG5_SHIFT, /*~< CCGR6, CG5 */
632 kCLOCK_Trng = (6U << 8U) | CCM_CCGR6_CG6_SHIFT, /*~< CCGR6, CG6 */
633 kCLOCK_Lpuart8 = (6U << 8U) | CCM_CCGR6_CG7_SHIFT, /*~< CCGR6, CG7 */
634 kCLOCK_Timer4 = (6U << 8U) | CCM_CCGR6_CG8_SHIFT, /*~< CCGR6, CG8 */
635 kCLOCK_Aips_tz3 = (6U << 8U) | CCM_CCGR6_CG9_SHIFT, /*~< CCGR6, CG9 */
636 kCLOCK_SimPer = (6U << 8U) | CCM_CCGR6_CG10_SHIFT, /*~< CCGR6, CG10 */
637 kCLOCK_Anadig = (6U << 8U) | CCM_CCGR6_CG11_SHIFT, /*~< CCGR6, CG11 */
638 kCLOCK_Lpi2c4 = (6U << 8U) | CCM_CCGR6_CG12_SHIFT, /*~< CCGR6, CG12 */
639 kCLOCK_Timer1 = (6U << 8U) | CCM_CCGR6_CG13_SHIFT, /*~< CCGR6, CG13 */
640 kCLOCK_Timer2 = (6U << 8U) | CCM_CCGR6_CG14_SHIFT, /*~< CCGR6, CG14 */
641 kCLOCK_Timer3 = (6U << 8U) | CCM_CCGR6_CG15_SHIFT, /*~< CCGR6, CG15 */
642
643 /* CCM CCGR7 */
644 kCLOCK_Enet2 = (7U << 8U) | CCM_CCGR7_CG0_SHIFT, /*~< CCGR7, CG0 */
645 kCLOCK_FlexSpi2 = (7U << 8U) | CCM_CCGR7_CG1_SHIFT, /*~< CCGR7, CG1 */
646 kCLOCK_Axbs_l = (7U << 8U) | CCM_CCGR7_CG2_SHIFT, /*~< CCGR7, CG2 */
647 kCLOCK_Can3 = (7U << 8U) | CCM_CCGR7_CG3_SHIFT, /*~< CCGR7, CG3 */
648 kCLOCK_Can3S = (7U << 8U) | CCM_CCGR7_CG4_SHIFT, /*~< CCGR7, CG4 */
649 kCLOCK_Aips_lite = (7U << 8U) | CCM_CCGR7_CG5_SHIFT, /*~< CCGR7, CG5 */
650 kCLOCK_Flexio3 = (7U << 8U) | CCM_CCGR7_CG6_SHIFT, /*~< CCGR7, CG6 */
651
652} clock_ip_name_t;
653
654/*~ @brief OSC 24M sorce select */
655typedef enum _clock_osc
656{
657 kCLOCK_RcOsc = 0U, /*~< On chip OSC. */
658 kCLOCK_XtalOsc = 1U, /*~< 24M Xtal OSC */
659} clock_osc_t;
660
661/*~ @brief Clock gate value */
662typedef enum _clock_gate_value
663{
664 kCLOCK_ClockNotNeeded = 0U, /*~< Clock is off during all modes. */
665 kCLOCK_ClockNeededRun = 1U, /*~< Clock is on in run mode, but off in WAIT and STOP modes */
666 kCLOCK_ClockNeededRunWait = 3U, /*~< Clock is on during all modes, except STOP mode */
667} clock_gate_value_t;
668
669/*~ @brief System clock mode */
670typedef enum _clock_mode_t
671{
672 kCLOCK_ModeRun = 0U, /*~< Remain in run mode. */
673 kCLOCK_ModeWait = 1U, /*~< Transfer to wait mode. */
674 kCLOCK_ModeStop = 2U, /*~< Transfer to stop mode. */
675} clock_mode_t;
676
677/*~
678 * @brief MUX control names for clock mux setting.
679 *
680 * These constants define the mux control names for clock mux setting.\n
681 * - 0:7: REG offset to CCM_BASE in bytes.
682 * - 8:15: Root clock setting bit field shift.
683 * - 16:31: Root clock setting bit field width.
684 */
685typedef enum _clock_mux
686{
687 kCLOCK_Pll3SwMux = CCM_TUPLE(CCSR_OFFSET,
688 CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT,
689 CCM_CCSR_PLL3_SW_CLK_SEL_MASK,
690 CCM_NO_BUSY_WAIT), /*~< pll3_sw_clk mux name */
691
692 kCLOCK_PeriphMux = CCM_TUPLE(CBCDR_OFFSET,
693 CCM_CBCDR_PERIPH_CLK_SEL_SHIFT,
694 CCM_CBCDR_PERIPH_CLK_SEL_MASK,
695 CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT), /*~< periph mux name */
696 kCLOCK_SemcAltMux = CCM_TUPLE(CBCDR_OFFSET,
697 CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT,
698 CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK,
699 CCM_NO_BUSY_WAIT), /*~< semc mux name */
700 kCLOCK_SemcMux = CCM_TUPLE(CBCDR_OFFSET,
701 CCM_CBCDR_SEMC_CLK_SEL_SHIFT,
702 CCM_CBCDR_SEMC_CLK_SEL_MASK,
703 CCM_NO_BUSY_WAIT), /*~< semc mux name */
704
705 kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR_OFFSET,
706 CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT,
707 CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK,
708 CCM_NO_BUSY_WAIT), /*~< pre-periph mux name */
709 kCLOCK_TraceMux = CCM_TUPLE(CBCMR_OFFSET,
710 CCM_CBCMR_TRACE_CLK_SEL_SHIFT,
711 CCM_CBCMR_TRACE_CLK_SEL_MASK,
712 CCM_NO_BUSY_WAIT), /*~< trace mux name */
713 kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR_OFFSET,
714 CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT,
715 CCM_CBCMR_PERIPH_CLK2_SEL_MASK,
716 CCM_NO_BUSY_WAIT), /*~< periph clock2 mux name */
717 kCLOCK_Flexspi2Mux = CCM_TUPLE(CBCMR_OFFSET,
718 CCM_CBCMR_FLEXSPI2_CLK_SEL_SHIFT,
719 CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK,
720 CCM_NO_BUSY_WAIT), /*~< flexspi2 mux name */
721 kCLOCK_LpspiMux = CCM_TUPLE(CBCMR_OFFSET,
722 CCM_CBCMR_LPSPI_CLK_SEL_SHIFT,
723 CCM_CBCMR_LPSPI_CLK_SEL_MASK,
724 CCM_NO_BUSY_WAIT), /*~< lpspi mux name */
725
726 kCLOCK_FlexspiMux = CCM_TUPLE(CSCMR1_OFFSET,
727 CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT,
728 CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK,
729 CCM_NO_BUSY_WAIT), /*~< flexspi mux name */
730 kCLOCK_Usdhc2Mux = CCM_TUPLE(CSCMR1_OFFSET,
731 CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT,
732 CCM_CSCMR1_USDHC2_CLK_SEL_MASK,
733 CCM_NO_BUSY_WAIT), /*~< usdhc2 mux name */
734 kCLOCK_Usdhc1Mux = CCM_TUPLE(CSCMR1_OFFSET,
735 CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT,
736 CCM_CSCMR1_USDHC1_CLK_SEL_MASK,
737 CCM_NO_BUSY_WAIT), /*~< usdhc1 mux name */
738 kCLOCK_Sai3Mux = CCM_TUPLE(CSCMR1_OFFSET,
739 CCM_CSCMR1_SAI3_CLK_SEL_SHIFT,
740 CCM_CSCMR1_SAI3_CLK_SEL_MASK,
741 CCM_NO_BUSY_WAIT), /*~< sai3 mux name */
742 kCLOCK_Sai2Mux = CCM_TUPLE(CSCMR1_OFFSET,
743 CCM_CSCMR1_SAI2_CLK_SEL_SHIFT,
744 CCM_CSCMR1_SAI2_CLK_SEL_MASK,
745 CCM_NO_BUSY_WAIT), /*~< sai2 mux name */
746 kCLOCK_Sai1Mux = CCM_TUPLE(CSCMR1_OFFSET,
747 CCM_CSCMR1_SAI1_CLK_SEL_SHIFT,
748 CCM_CSCMR1_SAI1_CLK_SEL_MASK,
749 CCM_NO_BUSY_WAIT), /*~< sai1 mux name */
750 kCLOCK_PerclkMux = CCM_TUPLE(CSCMR1_OFFSET,
751 CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT,
752 CCM_CSCMR1_PERCLK_CLK_SEL_MASK,
753 CCM_NO_BUSY_WAIT), /*~< perclk mux name */
754
755 kCLOCK_Flexio2Mux = CCM_TUPLE(CSCMR2_OFFSET,
756 CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT,
757 CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK,
758 CCM_NO_BUSY_WAIT), /*~< flexio2 mux name */
759 kCLOCK_CanMux = CCM_TUPLE(CSCMR2_OFFSET,
760 CCM_CSCMR2_CAN_CLK_SEL_SHIFT,
761 CCM_CSCMR2_CAN_CLK_SEL_MASK,
762 CCM_NO_BUSY_WAIT), /*~< can mux name */
763
764 kCLOCK_UartMux = CCM_TUPLE(CSCDR1_OFFSET,
765 CCM_CSCDR1_UART_CLK_SEL_SHIFT,
766 CCM_CSCDR1_UART_CLK_SEL_MASK,
767 CCM_NO_BUSY_WAIT), /*~< uart mux name */
768
769 kCLOCK_SpdifMux = CCM_TUPLE(CDCDR_OFFSET,
770 CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT,
771 CCM_CDCDR_SPDIF0_CLK_SEL_MASK,
772 CCM_NO_BUSY_WAIT), /*~< spdif mux name */
773 kCLOCK_Flexio1Mux = CCM_TUPLE(CDCDR_OFFSET,
774 CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT,
775 CCM_CDCDR_FLEXIO1_CLK_SEL_MASK,
776 CCM_NO_BUSY_WAIT), /*~< flexio1 mux name */
777
778 kCLOCK_Lpi2cMux = CCM_TUPLE(CSCDR2_OFFSET,
779 CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT,
780 CCM_CSCDR2_LPI2C_CLK_SEL_MASK,
781 CCM_NO_BUSY_WAIT), /*~< lpi2c mux name */
782 kCLOCK_LcdifPreMux = CCM_TUPLE(CSCDR2_OFFSET,
783 CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT,
784 CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK,
785 CCM_NO_BUSY_WAIT), /*~< lcdif pre mux name */
786
787 kCLOCK_CsiMux = CCM_TUPLE(CSCDR3_OFFSET,
788 CCM_CSCDR3_CSI_CLK_SEL_SHIFT,
789 CCM_CSCDR3_CSI_CLK_SEL_MASK,
790 CCM_NO_BUSY_WAIT), /*~< csi mux name */
791} clock_mux_t;
792
793/*~
794 * @brief DIV control names for clock div setting.
795 *
796 * These constants define div control names for clock div setting.\n
797 * - 0:7: REG offset to CCM_BASE in bytes.
798 * - 8:15: Root clock setting bit field shift.
799 * - 16:31: Root clock setting bit field width.
800 */
801typedef enum _clock_div
802{
803 kCLOCK_ArmDiv = CCM_TUPLE(CACRR_OFFSET,
804 CCM_CACRR_ARM_PODF_SHIFT,
805 CCM_CACRR_ARM_PODF_MASK,
806 CCM_CDHIPR_ARM_PODF_BUSY_SHIFT), /*~< core div name */
807
808 kCLOCK_PeriphClk2Div = CCM_TUPLE(CBCDR_OFFSET,
809 CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT,
810 CCM_CBCDR_PERIPH_CLK2_PODF_MASK,
811 CCM_NO_BUSY_WAIT), /*~< periph clock2 div name */
812 kCLOCK_SemcDiv = CCM_TUPLE(CBCDR_OFFSET,
813 CCM_CBCDR_SEMC_PODF_SHIFT,
814 CCM_CBCDR_SEMC_PODF_MASK,
815 CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT), /*~< semc div name */
816 kCLOCK_AhbDiv = CCM_TUPLE(CBCDR_OFFSET,
817 CCM_CBCDR_AHB_PODF_SHIFT,
818 CCM_CBCDR_AHB_PODF_MASK,
819 CCM_CDHIPR_AHB_PODF_BUSY_SHIFT), /*~< ahb div name */
820 kCLOCK_IpgDiv = CCM_TUPLE(
821 CBCDR_OFFSET, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), /*~< ipg div name */
822
823 kCLOCK_Flexspi2Div = CCM_TUPLE(CBCMR_OFFSET,
824 CCM_CBCMR_FLEXSPI2_PODF_SHIFT,
825 CCM_CBCMR_FLEXSPI2_PODF_MASK,
826 CCM_NO_BUSY_WAIT), /*~< flexspi2 div name */
827 kCLOCK_LpspiDiv = CCM_TUPLE(
828 CBCMR_OFFSET, CCM_CBCMR_LPSPI_PODF_SHIFT, CCM_CBCMR_LPSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*~< lpspi div name */
829 kCLOCK_LcdifDiv = CCM_TUPLE(
830 CBCMR_OFFSET, CCM_CBCMR_LCDIF_PODF_SHIFT, CCM_CBCMR_LCDIF_PODF_MASK, CCM_NO_BUSY_WAIT), /*~< lcdif div name */
831
832 kCLOCK_FlexspiDiv = CCM_TUPLE(CSCMR1_OFFSET,
833 CCM_CSCMR1_FLEXSPI_PODF_SHIFT,
834 CCM_CSCMR1_FLEXSPI_PODF_MASK,
835 CCM_NO_BUSY_WAIT), /*~< flexspi div name */
836 kCLOCK_PerclkDiv = CCM_TUPLE(CSCMR1_OFFSET,
837 CCM_CSCMR1_PERCLK_PODF_SHIFT,
838 CCM_CSCMR1_PERCLK_PODF_MASK,
839 CCM_NO_BUSY_WAIT), /*~< perclk div name */
840
841 kCLOCK_CanDiv = CCM_TUPLE(CSCMR2_OFFSET,
842 CCM_CSCMR2_CAN_CLK_PODF_SHIFT,
843 CCM_CSCMR2_CAN_CLK_PODF_MASK,
844 CCM_NO_BUSY_WAIT), /*~< can div name */
845
846 kCLOCK_TraceDiv = CCM_TUPLE(CSCDR1_OFFSET,
847 CCM_CSCDR1_TRACE_PODF_SHIFT,
848 CCM_CSCDR1_TRACE_PODF_MASK,
849 CCM_NO_BUSY_WAIT), /*~< trace div name */
850 kCLOCK_Usdhc2Div = CCM_TUPLE(CSCDR1_OFFSET,
851 CCM_CSCDR1_USDHC2_PODF_SHIFT,
852 CCM_CSCDR1_USDHC2_PODF_MASK,
853 CCM_NO_BUSY_WAIT), /*~< usdhc2 div name */
854 kCLOCK_Usdhc1Div = CCM_TUPLE(CSCDR1_OFFSET,
855 CCM_CSCDR1_USDHC1_PODF_SHIFT,
856 CCM_CSCDR1_USDHC1_PODF_MASK,
857 CCM_NO_BUSY_WAIT), /*~< usdhc1 div name */
858 kCLOCK_UartDiv = CCM_TUPLE(CSCDR1_OFFSET,
859 CCM_CSCDR1_UART_CLK_PODF_SHIFT,
860 CCM_CSCDR1_UART_CLK_PODF_MASK,
861 CCM_NO_BUSY_WAIT), /*~< uart div name */
862
863 kCLOCK_Flexio2Div = CCM_TUPLE(CS1CDR_OFFSET,
864 CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT,
865 CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK,
866 CCM_NO_BUSY_WAIT), /*~< flexio2 pre div name */
867 kCLOCK_Sai3PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
868 CCM_CS1CDR_SAI3_CLK_PRED_SHIFT,
869 CCM_CS1CDR_SAI3_CLK_PRED_MASK,
870 CCM_NO_BUSY_WAIT), /*~< sai3 pre div name */
871 kCLOCK_Sai3Div = CCM_TUPLE(CS1CDR_OFFSET,
872 CCM_CS1CDR_SAI3_CLK_PODF_SHIFT,
873 CCM_CS1CDR_SAI3_CLK_PODF_MASK,
874 CCM_NO_BUSY_WAIT), /*~< sai3 div name */
875 kCLOCK_Flexio2PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
876 CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT,
877 CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK,
878 CCM_NO_BUSY_WAIT), /*~< sai3 pre div name */
879 kCLOCK_Sai1PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
880 CCM_CS1CDR_SAI1_CLK_PRED_SHIFT,
881 CCM_CS1CDR_SAI1_CLK_PRED_MASK,
882 CCM_NO_BUSY_WAIT), /*~< sai1 pre div name */
883 kCLOCK_Sai1Div = CCM_TUPLE(CS1CDR_OFFSET,
884 CCM_CS1CDR_SAI1_CLK_PODF_SHIFT,
885 CCM_CS1CDR_SAI1_CLK_PODF_MASK,
886 CCM_NO_BUSY_WAIT), /*~< sai1 div name */
887
888 kCLOCK_Sai2PreDiv = CCM_TUPLE(CS2CDR_OFFSET,
889 CCM_CS2CDR_SAI2_CLK_PRED_SHIFT,
890 CCM_CS2CDR_SAI2_CLK_PRED_MASK,
891 CCM_NO_BUSY_WAIT), /*~< sai2 pre div name */
892 kCLOCK_Sai2Div = CCM_TUPLE(CS2CDR_OFFSET,
893 CCM_CS2CDR_SAI2_CLK_PODF_SHIFT,
894 CCM_CS2CDR_SAI2_CLK_PODF_MASK,
895 CCM_NO_BUSY_WAIT), /*~< sai2 div name */
896
897 kCLOCK_Spdif0PreDiv = CCM_TUPLE(CDCDR_OFFSET,
898 CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT,
899 CCM_CDCDR_SPDIF0_CLK_PRED_MASK,
900 CCM_NO_BUSY_WAIT), /*~< spdif pre div name */
901 kCLOCK_Spdif0Div = CCM_TUPLE(CDCDR_OFFSET,
902 CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT,
903 CCM_CDCDR_SPDIF0_CLK_PODF_MASK,
904 CCM_NO_BUSY_WAIT), /*~< spdif div name */
905 kCLOCK_Flexio1PreDiv = CCM_TUPLE(CDCDR_OFFSET,
906 CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT,
907 CCM_CDCDR_FLEXIO1_CLK_PRED_MASK,
908 CCM_NO_BUSY_WAIT), /*~< flexio1 pre div name */
909 kCLOCK_Flexio1Div = CCM_TUPLE(CDCDR_OFFSET,
910 CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT,
911 CCM_CDCDR_FLEXIO1_CLK_PODF_MASK,
912 CCM_NO_BUSY_WAIT), /*~< flexio1 div name */
913
914 kCLOCK_Lpi2cDiv = CCM_TUPLE(CSCDR2_OFFSET,
915 CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT,
916 CCM_CSCDR2_LPI2C_CLK_PODF_MASK,
917 CCM_NO_BUSY_WAIT), /*~< lpi2c div name */
918 kCLOCK_LcdifPreDiv = CCM_TUPLE(CSCDR2_OFFSET,
919 CCM_CSCDR2_LCDIF_PRED_SHIFT,
920 CCM_CSCDR2_LCDIF_PRED_MASK,
921 CCM_NO_BUSY_WAIT), /*~< lcdif pre div name */
922
923 kCLOCK_CsiDiv = CCM_TUPLE(
924 CSCDR3_OFFSET, CCM_CSCDR3_CSI_PODF_SHIFT, CCM_CSCDR3_CSI_PODF_MASK, CCM_NO_BUSY_WAIT), /*~< csi div name */
925
926 kCLOCK_NonePreDiv = CLOCK_ROOT_NONE_PRE_DIV, /*~< None Pre div. */
927} clock_div_t;
928
929/*~ @brief USB clock source definition. */
930typedef enum _clock_usb_src
931{
932 kCLOCK_Usb480M = 0, /*~< Use 480M. */
933 kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU, /*~< Used when the function does not
934 care the clock source. */
935} clock_usb_src_t;
936
937/*~ @brief Source of the USB HS PHY. */
938typedef enum _clock_usb_phy_src
939{
940 kCLOCK_Usbphy480M = 0, /*~< Use 480M. */
941} clock_usb_phy_src_t;
942
943/*~@brief PLL clock source, bypass cloco source also */
944enum _clock_pll_clk_src
945{
946 kCLOCK_PllClkSrc24M = 0U, /*~< Pll clock source 24M */
947 kCLOCK_PllSrcClkPN = 1U, /*~< Pll clock source CLK1_P and CLK1_N */
948};
949
950/*~ @brief PLL configuration for ARM */
951typedef struct _clock_arm_pll_config
952{
953 uint32_t loopDivider; /*~< PLL loop divider. Valid range for divider value: 54-108. Fout=Fin*loopDivider/2. */
954 uint8_t src; /*~< Pll clock source, reference _clock_pll_clk_src */
955} clock_arm_pll_config_t;
956
957/*~ @brief PLL configuration for USB */
958typedef struct _clock_usb_pll_config
959{
960 uint8_t loopDivider; /*~< PLL loop divider.
961 0 - Fout=Fref*20;
962 1 - Fout=Fref*22 */
963 uint8_t src; /*~< Pll clock source, reference _clock_pll_clk_src */
964
965} clock_usb_pll_config_t;
966
967/*~ @brief PLL configuration for System */
968typedef struct _clock_sys_pll_config
969{
970 uint8_t loopDivider; /*~< PLL loop divider. Intended to be 1 (528M).
971 0 - Fout=Fref*20;
972 1 - Fout=Fref*22 */
973 uint32_t numerator; /*~< 30 bit numerator of fractional loop divider.*/
974 uint32_t denominator; /*~< 30 bit denominator of fractional loop divider */
975 uint8_t src; /*~< Pll clock source, reference _clock_pll_clk_src */
976 uint16_t ss_stop; /*~< Stop value to get frequency change. */
977 uint8_t ss_enable; /*~< Enable spread spectrum modulation */
978 uint16_t ss_step; /*~< Step value to get frequency change step. */
979} clock_sys_pll_config_t;
980
981/*~ @brief PLL configuration for AUDIO and VIDEO */
982typedef struct _clock_audio_pll_config
983{
984 uint8_t loopDivider; /*~< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */
985 uint8_t postDivider; /*~< Divider after the PLL, should only be 1, 2, 4, 8, 16. */
986 uint32_t numerator; /*~< 30 bit numerator of fractional loop divider.*/
987 uint32_t denominator; /*~< 30 bit denominator of fractional loop divider */
988 uint8_t src; /*~< Pll clock source, reference _clock_pll_clk_src */
989} clock_audio_pll_config_t;
990
991/*~ @brief PLL configuration for AUDIO and VIDEO */
992typedef struct _clock_video_pll_config
993{
994 uint8_t loopDivider; /*~< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */
995 uint8_t postDivider; /*~< Divider after the PLL, should only be 1, 2, 4, 8, 16. */
996 uint32_t numerator; /*~< 30 bit numerator of fractional loop divider.*/
997 uint32_t denominator; /*~< 30 bit denominator of fractional loop divider */
998 uint8_t src; /*~< Pll clock source, reference _clock_pll_clk_src */
999
1000} clock_video_pll_config_t;
1001
1002/*~ @brief PLL configuration for ENET */
1003typedef struct _clock_enet_pll_config
1004{
1005 bool enableClkOutput; /*~< Power on and enable PLL clock output for ENET0 (ref_enetpll0). */
1006 bool enableClkOutput25M; /*~< Power on and enable PLL clock output for ENET2 (ref_enetpll2). */
1007 uint8_t loopDivider; /*~< Controls the frequency of the ENET0 reference clock.
1008 b00 25MHz
1009 b01 50MHz
1010 b10 100MHz (not 50% duty cycle)
1011 b11 125MHz */
1012 uint8_t src; /*~< Pll clock source, reference _clock_pll_clk_src */
1013 bool enableClkOutput1; /*~< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */
1014 uint8_t loopDivider1; /*~< Controls the frequency of the ENET1 reference clock.
1015 b00 25MHz
1016 b01 50MHz
1017 b10 100MHz (not 50% duty cycle)
1018 b11 125MHz */
1019} clock_enet_pll_config_t;
1020
1021/*~ @brief PLL name */
1022typedef enum _clock_pll
1023{
1024 kCLOCK_PllArm = CCM_ANALOG_TUPLE(PLL_ARM_OFFSET, CCM_ANALOG_PLL_ARM_ENABLE_SHIFT), /*~< PLL ARM */
1025 kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS_OFFSET, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT), /*~< PLL SYS */
1026 kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1_OFFSET, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT), /*~< PLL USB1 */
1027 kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO_OFFSET, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT), /*~< PLL Audio */
1028 kCLOCK_PllVideo = CCM_ANALOG_TUPLE(PLL_VIDEO_OFFSET, CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT), /*~< PLL Video */
1029
1030 kCLOCK_PllEnet = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENABLE_SHIFT), /*~< PLL Enet0 */
1031 kCLOCK_PllEnet2 = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET2_REF_EN_SHIFT), /*~< PLL Enet1 */
1032 kCLOCK_PllEnet25M = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT), /*~< PLL Enet2 */
1033
1034 kCLOCK_PllUsb2 = CCM_ANALOG_TUPLE(PLL_USB2_OFFSET, CCM_ANALOG_PLL_USB2_ENABLE_SHIFT), /*~< PLL USB2 */
1035
1036} clock_pll_t;
1037
1038/*~ @brief PLL PFD name */
1039typedef enum _clock_pfd
1040{
1041 kCLOCK_Pfd0 = 0U, /*~< PLL PFD0 */
1042 kCLOCK_Pfd1 = 1U, /*~< PLL PFD1 */
1043 kCLOCK_Pfd2 = 2U, /*~< PLL PFD2 */
1044 kCLOCK_Pfd3 = 3U, /*~< PLL PFD3 */
1045} clock_pfd_t;
1046
1047/*~
1048 * @brief The enumerater of clock output1's clock source, such as USB1 PLL, SYS PLL and so on.
1049 */
1050typedef enum _clock_output1_selection
1051{
1052 kCLOCK_OutputPllUsb1 = 0U, /*~< Selects USB1 PLL clock(Divided by 2) output. */
1053 kCLOCK_OutputPllSys = 1U, /*~< Selects SYS PLL clock(Divided by 2) output. */
1054 kCLOCK_OutputPllVideo = 3U, /*~< Selects Video PLL clock(Divided by 2) output. */
1055 kCLOCK_OutputSemcClk = 5U, /*~< Selects semc clock root output. */
1056 kCLOCK_OutputLcdifPixClk = 0xAU, /*~< Selects Lcdif pix clock root output. */
1057 kCLOCK_OutputAhbClk = 0xBU, /*~< Selects AHB clock root output. */
1058 kCLOCK_OutputIpgClk = 0xCU, /*~< Selects IPG clock root output. */
1059 kCLOCK_OutputPerClk = 0xDU, /*~< Selects PERCLK clock root output. */
1060 kCLOCK_OutputCkilSyncClk = 0xEU, /*~< Selects Ckil clock root output. */
1061 kCLOCK_OutputPll4MainClk = 0xFU, /*~< Selects PLL4 main clock output. */
1062 kCLOCK_DisableClockOutput1 = 0x10U, /*~< Disables CLKO1. */
1063} clock_output1_selection_t;
1064
1065/*~
1066 * @brief The enumerater of clock output2's clock source, such as USDHC1 clock root, LPI2C clock root and so on.
1067 *
1068 */
1069typedef enum _clock_output2_selection
1070{
1071 kCLOCK_OutputUsdhc1Clk = 3U, /*~< Selects USDHC1 clock root output. */
1072 kCLOCK_OutputLpi2cClk = 6U, /*~< Selects LPI2C clock root output. */
1073 kCLOCK_OutputCsiClk = 0xBU, /*~< Selects CSI clock root output. */
1074 kCLOCK_OutputOscClk = 0xEU, /*~< Selects OSC output. */
1075 kCLOCK_OutputUsdhc2Clk = 0x11U, /*~< Selects USDHC2 clock root output. */
1076 kCLOCK_OutputSai1Clk = 0x12U, /*~< Selects SAI1 clock root output. */
1077 kCLOCK_OutputSai2Clk = 0x13U, /*~< Selects SAI2 clock root output. */
1078 kCLOCK_OutputSai3Clk = 0x14U, /*~< Selects SAI3 clock root output. */
1079 kCLOCK_OutputCanClk = 0x17U, /*~< Selects CAN clock root output. */
1080 kCLOCK_OutputFlexspiClk = 0x1BU, /*~< Selects FLEXSPI clock root output. */
1081 kCLOCK_OutputUartClk = 0x1CU, /*~< Selects UART clock root output. */
1082 kCLOCK_OutputSpdif0Clk = 0x1DU, /*~< Selects SPDIF0 clock root output. */
1083 kCLOCK_DisableClockOutput2 = 0x1FU, /*~< Disables CLKO2. */
1084} clock_output2_selection_t;
1085
1086/*~
1087 * @brief The enumerator of clock output's divider.
1088 */
1089typedef enum _clock_output_divider
1090{
1091 kCLOCK_DivideBy1 = 0U, /*~< Output clock divided by 1. */
1092 kCLOCK_DivideBy2, /*~< Output clock divided by 2. */
1093 kCLOCK_DivideBy3, /*~< Output clock divided by 3. */
1094 kCLOCK_DivideBy4, /*~< Output clock divided by 4. */
1095 kCLOCK_DivideBy5, /*~< Output clock divided by 5. */
1096 kCLOCK_DivideBy6, /*~< Output clock divided by 6. */
1097 kCLOCK_DivideBy7, /*~< Output clock divided by 7. */
1098 kCLOCK_DivideBy8, /*~< Output clock divided by 8. */
1099} clock_output_divider_t;
1100
1101/*~
1102 * @brief The enumerator of clock root.
1103 */
1104typedef enum _clock_root
1105{
1106 kCLOCK_Usdhc1ClkRoot = 0U, /*~< USDHC1 clock root. */
1107 kCLOCK_Usdhc2ClkRoot, /*~< USDHC2 clock root. */
1108 kCLOCK_FlexspiClkRoot, /*~< FLEXSPI clock root. */
1109 kCLOCK_Flexspi2ClkRoot, /*~< FLEXSPI2 clock root. */
1110 kCLOCK_CsiClkRoot, /*~< CSI clock root. */
1111 kCLOCK_LpspiClkRoot, /*~< LPSPI clock root. */
1112 kCLOCK_TraceClkRoot, /*~< Trace clock root. */
1113 kCLOCK_Sai1ClkRoot, /*~< SAI1 clock root. */
1114 kCLOCK_Sai2ClkRoot, /*~< SAI2 clock root. */
1115 kCLOCK_Sai3ClkRoot, /*~< SAI3 clock root. */
1116 kCLOCK_Lpi2cClkRoot, /*~< LPI2C clock root. */
1117 kCLOCK_CanClkRoot, /*~< CAN clock root. */
1118 kCLOCK_UartClkRoot, /*~< UART clock root. */
1119 kCLOCK_LcdifClkRoot, /*~< LCD clock root. */
1120 kCLOCK_SpdifClkRoot, /*~< SPDIF clock root. */
1121 kCLOCK_Flexio1ClkRoot, /*~< FLEXIO1 clock root. */
1122 kCLOCK_Flexio2ClkRoot, /*~< FLEXIO2 clock root. */
1123} clock_root_t;
1124
1125/*******************************************************************************
1126 * API
1127 ******************************************************************************/
1128
1129#if defined(__cplusplus)
1130extern "C" {
1131#endif /* __cplusplus */
1132
1133/*~
1134 * @brief Set CCM MUX node to certain value.
1135 *
1136 * @param mux Which mux node to set, see \ref clock_mux_t.
1137 * @param value Clock mux value to set, different mux has different value range.
1138 */
1139static inline void CLOCK_SetMux(clock_mux_t mux, uint32_t value)
1140{
1141 uint32_t busyShift;
1142
1143 busyShift = (uint32_t)CCM_TUPLE_BUSY_SHIFT(mux);
1144 CCM_TUPLE_REG(CCM, mux) = (CCM_TUPLE_REG(CCM, mux) & (~CCM_TUPLE_MASK(mux))) |
1145 (((uint32_t)((value) << CCM_TUPLE_SHIFT(mux))) & CCM_TUPLE_MASK(mux));
1146
1147 assert(busyShift <= CCM_NO_BUSY_WAIT);
1148
1149 /* Clock switch need Handshake? */
1150 if (CCM_NO_BUSY_WAIT != busyShift)
1151 {
1152 /* Wait until CCM internal handshake finish. */
1153 while ((CCM->CDHIPR & ((1UL << busyShift))) != 0UL)
1154 {
1155 }
1156 }
1157}
1158
1159/*~
1160 * @brief Get CCM MUX value.
1161 *
1162 * @param mux Which mux node to get, see \ref clock_mux_t.
1163 * @return Clock mux value.
1164 */
1165static inline uint32_t CLOCK_GetMux(clock_mux_t mux)
1166{
1167 return (((uint32_t)(CCM_TUPLE_REG(CCM, mux) & CCM_TUPLE_MASK(mux))) >> CCM_TUPLE_SHIFT(mux));
1168}
1169
1170/*~
1171 * @brief Set CCM DIV node to certain value.
1172 *
1173 * @param divider Which div node to set, see \ref clock_div_t.
1174 * @param value Clock div value to set, different divider has different value range.
1175 */
1176static inline void CLOCK_SetDiv(clock_div_t divider, uint32_t value)
1177{
1178 uint32_t busyShift;
1179
1180 busyShift = CCM_TUPLE_BUSY_SHIFT(divider);
1181 CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) |
1182 (((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider));
1183
1184 assert(busyShift <= CCM_NO_BUSY_WAIT);
1185
1186 /* Clock switch need Handshake? */
1187 if (CCM_NO_BUSY_WAIT != busyShift)
1188 {
1189 /* Wait until CCM internal handshake finish. */
1190 while ((CCM->CDHIPR & ((uint32_t)(1UL << busyShift))) != 0UL)
1191 {
1192 }
1193 }
1194}
1195
1196/*~
1197 * @brief Get CCM DIV node value.
1198 *
1199 * @param divider Which div node to get, see \ref clock_div_t.
1200 */
1201static inline uint32_t CLOCK_GetDiv(clock_div_t divider)
1202{
1203 return ((uint32_t)(CCM_TUPLE_REG(CCM, divider) & CCM_TUPLE_MASK(divider)) >> CCM_TUPLE_SHIFT(divider));
1204}
1205
1206/*~
1207 * @brief Control the clock gate for specific IP.
1208 *
1209 * @param name Which clock to enable, see \ref clock_ip_name_t.
1210 * @param value Clock gate value to set, see \ref clock_gate_value_t.
1211 */
1212static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t value)
1213{
1214 uint32_t index = ((uint32_t)name) >> 8U;
1215 uint32_t shift = ((uint32_t)name) & 0x1FU;
1216 volatile uint32_t *reg;
1217
1218 assert(index <= 7UL);
1219
1220 reg = (volatile uint32_t *)(&(((volatile uint32_t *)&CCM->CCGR0)[index]));
1221 *reg = ((*reg) & ~((uint32_t)(3UL << shift))) | (((uint32_t)value) << shift);
1222}
1223
1224/*~
1225 * @brief Enable the clock for specific IP.
1226 *
1227 * @param name Which clock to enable, see \ref clock_ip_name_t.
1228 */
1229static inline void CLOCK_EnableClock(clock_ip_name_t name)
1230{
1231 CLOCK_ControlGate(name, kCLOCK_ClockNeededRunWait);
1232}
1233
1234/*~
1235 * @brief Disable the clock for specific IP.
1236 *
1237 * @param name Which clock to disable, see \ref clock_ip_name_t.
1238 */
1239static inline void CLOCK_DisableClock(clock_ip_name_t name)
1240{
1241 CLOCK_ControlGate(name, kCLOCK_ClockNotNeeded);
1242}
1243
1244/*~
1245 * @brief Setting the low power mode that system will enter on next assertion of dsm_request signal.
1246 *
1247 * @param mode Which mode to enter, see \ref clock_mode_t.
1248 */
1249static inline void CLOCK_SetMode(clock_mode_t mode)
1250{
1251 CCM->CLPCR = (CCM->CLPCR & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM((uint32_t)mode);
1252}
1253
1254/*~
1255 * @brief Gets the OSC clock frequency.
1256 *
1257 * This function will return the external XTAL OSC frequency if it is selected as the source of OSC,
1258 * otherwise internal 24MHz RC OSC frequency will be returned.
1259 *
1260 * @param osc OSC type to get frequency.
1261 *
1262 * @return Clock frequency; If the clock is invalid, returns 0.
1263 */
1264static inline uint32_t CLOCK_GetOscFreq(void)
1265{
1266 return ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 24000000UL : g_xtalFreq;
1267}
1268
1269/*~
1270 * @brief Gets the AHB clock frequency.
1271 *
1272 * @return The AHB clock frequency value in hertz.
1273 */
1274uint32_t CLOCK_GetAhbFreq(void);
1275
1276/*~
1277 * @brief Gets the SEMC clock frequency.
1278 *
1279 * @return The SEMC clock frequency value in hertz.
1280 */
1281uint32_t CLOCK_GetSemcFreq(void);
1282
1283/*~
1284 * @brief Gets the IPG clock frequency.
1285 *
1286 * @return The IPG clock frequency value in hertz.
1287 */
1288uint32_t CLOCK_GetIpgFreq(void);
1289uint32_t CLOCK_GetPeriphClkFreq(void);
1290
1291/*~
1292 * @brief Gets the PER clock frequency.
1293 *
1294 * @return The PER clock frequency value in hertz.
1295 */
1296uint32_t CLOCK_GetPerClkFreq(void);
1297
1298/*~
1299 * @brief Gets the clock frequency for a specific clock name.
1300 *
1301 * This function checks the current clock configurations and then calculates
1302 * the clock frequency for a specific clock name defined in clock_name_t.
1303 *
1304 * @param clockName Clock names defined in clock_name_t
1305 * @return Clock frequency value in hertz
1306 */
1307uint32_t CLOCK_GetFreq(clock_name_t name);
1308
1309/*~
1310 * @brief Get the CCM CPU/core/system frequency.
1311 *
1312 * @return Clock frequency; If the clock is invalid, returns 0.
1313 */
1314static inline uint32_t CLOCK_GetCpuClkFreq(void)
1315{
1316 return CLOCK_GetFreq(kCLOCK_CpuClk);
1317}
1318
1319/*~
1320 * @brief Gets the frequency of selected clock root.
1321 *
1322 * @param clockRoot The clock root used to get the frequency, please refer to @ref clock_root_t.
1323 * @return The frequency of selected clock root.
1324 */
1325uint32_t CLOCK_GetClockRootFreq(clock_root_t clockRoot);
1326
1327/*~
1328 * @name OSC operations
1329 * @{
1330 */
1331
1332/*~
1333 * @brief Initialize the external 24MHz clock.
1334 *
1335 * This function supports two modes:
1336 * 1. Use external crystal oscillator.
1337 * 2. Bypass the external crystal oscillator, using input source clock directly.
1338 *
1339 * After this function, please call @ref CLOCK_SetXtal0Freq to inform clock driver
1340 * the external clock frequency.
1341 *
1342 * @param bypassXtalOsc Pass in true to bypass the external crystal oscillator.
1343 * @note This device does not support bypass external crystal oscillator, so
1344 * the input parameter should always be false.
1345 */
1346void CLOCK_InitExternalClk(bool bypassXtalOsc);
1347
1348/*~
1349 * @brief Deinitialize the external 24MHz clock.
1350 *
1351 * This function disables the external 24MHz clock.
1352 *
1353 * After this function, please call @ref CLOCK_SetXtal0Freq to set external clock
1354 * frequency to 0.
1355 */
1356void CLOCK_DeinitExternalClk(void);
1357
1358/*~
1359 * @brief Switch the OSC.
1360 *
1361 * This function switches the OSC source for SoC.
1362 *
1363 * @param osc OSC source to switch to.
1364 */
1365void CLOCK_SwitchOsc(clock_osc_t osc);
1366
1367/*~
1368 * @brief Gets the RTC clock frequency.
1369 *
1370 * @return Clock frequency; If the clock is invalid, returns 0.
1371 */
1372static inline uint32_t CLOCK_GetRtcFreq(void)
1373{
1374 return 32768U;
1375}
1376
1377/*~
1378 * @brief Set the XTAL (24M OSC) frequency based on board setting.
1379 *
1380 * @param freq The XTAL input clock frequency in Hz.
1381 */
1382static inline void CLOCK_SetXtalFreq(uint32_t freq)
1383{
1384 g_xtalFreq = freq;
1385}
1386
1387/*~
1388 * @brief Set the RTC XTAL (32K OSC) frequency based on board setting.
1389 *
1390 * @param freq The RTC XTAL input clock frequency in Hz.
1391 */
1392static inline void CLOCK_SetRtcXtalFreq(uint32_t freq)
1393{
1394 g_rtcXtalFreq = freq;
1395}
1396
1397/*~
1398 * @brief Initialize the RC oscillator 24MHz clock.
1399 */
1400void CLOCK_InitRcOsc24M(void);
1401
1402/*~
1403 * @brief Power down the RCOSC 24M clock.
1404 */
1405void CLOCK_DeinitRcOsc24M(void);
1406/* @} */
1407
1408/*~ @brief Enable USB HS clock.
1409 *
1410 * This function only enables the access to USB HS prepheral, upper layer
1411 * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
1412 * clock to use USB HS.
1413 *
1414 * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused.
1415 * @param freq USB HS does not care about the clock source, so this parameter is ignored.
1416 * @retval true The clock is set successfully.
1417 * @retval false The clock source is invalid to get proper USB HS clock.
1418 */
1419bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq);
1420
1421/*~ @brief Enable USB HS clock.
1422 *
1423 * This function only enables the access to USB HS prepheral, upper layer
1424 * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
1425 * clock to use USB HS.
1426 *
1427 * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused.
1428 * @param freq USB HS does not care about the clock source, so this parameter is ignored.
1429 * @retval true The clock is set successfully.
1430 * @retval false The clock source is invalid to get proper USB HS clock.
1431 */
1432bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq);
1433
1434/* @} */
1435
1436/*~
1437 * @name PLL/PFD operations
1438 * @{
1439 */
1440/*~
1441 * @brief PLL bypass setting
1442 *
1443 * @param base CCM_ANALOG base pointer.
1444 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1445 * @param bypass Bypass the PLL.
1446 * - true: Bypass the PLL.
1447 * - false:Not bypass the PLL.
1448 */
1449static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_t pll, bool bypass)
1450{
1451 if (bypass)
1452 {
1453 CCM_ANALOG_TUPLE_REG_OFF(base, pll, 4U) = 1UL << CCM_ANALOG_PLL_BYPASS_SHIFT;
1454 }
1455 else
1456 {
1457 CCM_ANALOG_TUPLE_REG_OFF(base, pll, 8U) = 1UL << CCM_ANALOG_PLL_BYPASS_SHIFT;
1458 }
1459}
1460
1461/*~
1462 * @brief Check if PLL is bypassed
1463 *
1464 * @param base CCM_ANALOG base pointer.
1465 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1466 * @return PLL bypass status.
1467 * - true: The PLL is bypassed.
1468 * - false: The PLL is not bypassed.
1469 */
1470static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_t pll)
1471{
1472 return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1UL << CCM_ANALOG_PLL_BYPASS_SHIFT));
1473}
1474
1475/*~
1476 * @brief Check if PLL is enabled
1477 *
1478 * @param base CCM_ANALOG base pointer.
1479 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1480 * @return PLL bypass status.
1481 * - true: The PLL is enabled.
1482 * - false: The PLL is not enabled.
1483 */
1484static inline bool CLOCK_IsPllEnabled(CCM_ANALOG_Type *base, clock_pll_t pll)
1485{
1486 return ((CCM_ANALOG_TUPLE_REG(base, pll) & (1UL << CCM_ANALOG_TUPLE_SHIFT(pll))) != 0U);
1487}
1488
1489/*~
1490 * @brief PLL bypass clock source setting.
1491 * Note: change the bypass clock source also change the pll reference clock source.
1492 *
1493 * @param base CCM_ANALOG base pointer.
1494 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1495 * @param src Bypass clock source, reference _clock_pll_bypass_clk_src.
1496 */
1497static inline void CLOCK_SetPllBypassRefClkSrc(CCM_ANALOG_Type *base, clock_pll_t pll, uint32_t src)
1498{
1499 CCM_ANALOG_TUPLE_REG(base, pll) |= (CCM_ANALOG_TUPLE_REG(base, pll) & (~CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK)) | src;
1500}
1501
1502/*~
1503 * @brief Get PLL bypass clock value, it is PLL reference clock actually.
1504 * If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0
1505 * will be returned.
1506 * @param base CCM_ANALOG base pointer.
1507 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1508 * @retval bypass reference clock frequency value.
1509 */
1510static inline uint32_t CLOCK_GetPllBypassRefClk(CCM_ANALOG_Type *base, clock_pll_t pll)
1511{
1512 return (((CCM_ANALOG_TUPLE_REG(base, pll) & CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK) >>
1513 CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT) == (uint32_t)kCLOCK_PllClkSrc24M) ?
1514 CLOCK_GetOscFreq() :
1515 CLKPN_FREQ;
1516}
1517
1518/*~
1519 * @brief Initialize the ARM PLL.
1520 *
1521 * This function initialize the ARM PLL with specific settings
1522 *
1523 * @param config configuration to set to PLL.
1524 */
1525void CLOCK_InitArmPll(const clock_arm_pll_config_t *config);
1526
1527/*~
1528 * @brief De-initialize the ARM PLL.
1529 */
1530void CLOCK_DeinitArmPll(void);
1531
1532/*~
1533 * @brief Initialize the System PLL.
1534 *
1535 * This function initializes the System PLL with specific settings
1536 *
1537 * @param config Configuration to set to PLL.
1538 */
1539void CLOCK_InitSysPll(const clock_sys_pll_config_t *config);
1540
1541/*~
1542 * @brief De-initialize the System PLL.
1543 */
1544void CLOCK_DeinitSysPll(void);
1545
1546/*~
1547 * @brief Initialize the USB1 PLL.
1548 *
1549 * This function initializes the USB1 PLL with specific settings
1550 *
1551 * @param config Configuration to set to PLL.
1552 */
1553void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config);
1554
1555/*~
1556 * @brief Deinitialize the USB1 PLL.
1557 */
1558void CLOCK_DeinitUsb1Pll(void);
1559
1560/*~
1561 * @brief Initialize the USB2 PLL.
1562 *
1563 * This function initializes the USB2 PLL with specific settings
1564 *
1565 * @param config Configuration to set to PLL.
1566 */
1567void CLOCK_InitUsb2Pll(const clock_usb_pll_config_t *config);
1568
1569/*~
1570 * @brief Deinitialize the USB2 PLL.
1571 */
1572void CLOCK_DeinitUsb2Pll(void);
1573
1574/*~
1575 * @brief Initializes the Audio PLL.
1576 *
1577 * This function initializes the Audio PLL with specific settings
1578 *
1579 * @param config Configuration to set to PLL.
1580 */
1581void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config);
1582
1583/*~
1584 * @brief De-initialize the Audio PLL.
1585 */
1586void CLOCK_DeinitAudioPll(void);
1587
1588/*~
1589 * @brief Initialize the video PLL.
1590 *
1591 * This function configures the Video PLL with specific settings
1592 *
1593 * @param config configuration to set to PLL.
1594 */
1595void CLOCK_InitVideoPll(const clock_video_pll_config_t *config);
1596
1597/*~
1598 * @brief De-initialize the Video PLL.
1599 */
1600void CLOCK_DeinitVideoPll(void);
1601/*~
1602 * @brief Initialize the ENET PLL.
1603 *
1604 * This function initializes the ENET PLL with specific settings.
1605 *
1606 * @param config Configuration to set to PLL.
1607 */
1608void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config);
1609
1610/*~
1611 * @brief Deinitialize the ENET PLL.
1612 *
1613 * This function disables the ENET PLL.
1614 */
1615void CLOCK_DeinitEnetPll(void);
1616
1617/*~
1618 * @brief Get current PLL output frequency.
1619 *
1620 * This function get current output frequency of specific PLL
1621 *
1622 * @param pll pll name to get frequency.
1623 * @return The PLL output frequency in hertz.
1624 */
1625uint32_t CLOCK_GetPllFreq(clock_pll_t pll);
1626
1627/*~
1628 * @brief Initialize the System PLL PFD.
1629 *
1630 * This function initializes the System PLL PFD. During new value setting,
1631 * the clock output is disabled to prevent glitch.
1632 *
1633 * @param pfd Which PFD clock to enable.
1634 * @param pfdFrac The PFD FRAC value.
1635 * @note It is recommended that PFD settings are kept between 12-35.
1636 */
1637void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac);
1638
1639/*~
1640 * @brief De-initialize the System PLL PFD.
1641 *
1642 * This function disables the System PLL PFD.
1643 *
1644 * @param pfd Which PFD clock to disable.
1645 */
1646void CLOCK_DeinitSysPfd(clock_pfd_t pfd);
1647
1648/*~
1649 * @brief Initialize the USB1 PLL PFD.
1650 *
1651 * This function initializes the USB1 PLL PFD. During new value setting,
1652 * the clock output is disabled to prevent glitch.
1653 *
1654 * @param pfd Which PFD clock to enable.
1655 * @param pfdFrac The PFD FRAC value.
1656 * @note It is recommended that PFD settings are kept between 12-35.
1657 */
1658void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac);
1659
1660/*~
1661 * @brief De-initialize the USB1 PLL PFD.
1662 *
1663 * This function disables the USB1 PLL PFD.
1664 *
1665 * @param pfd Which PFD clock to disable.
1666 */
1667void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd);
1668
1669/*~
1670 * @brief Get current System PLL PFD output frequency.
1671 *
1672 * This function get current output frequency of specific System PLL PFD
1673 *
1674 * @param pfd pfd name to get frequency.
1675 * @return The PFD output frequency in hertz.
1676 */
1677uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd);
1678
1679/*~
1680 * @brief Get current USB1 PLL PFD output frequency.
1681 *
1682 * This function get current output frequency of specific USB1 PLL PFD
1683 *
1684 * @param pfd pfd name to get frequency.
1685 * @return The PFD output frequency in hertz.
1686 */
1687uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd);
1688
1689/*~ @brief Enable USB HS PHY PLL clock.
1690 *
1691 * This function enables the internal 480MHz USB PHY PLL clock.
1692 *
1693 * @param src USB HS PHY PLL clock source.
1694 * @param freq The frequency specified by src.
1695 * @retval true The clock is set successfully.
1696 * @retval false The clock source is invalid to get proper USB HS clock.
1697 */
1698bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
1699
1700/*~ @brief Disable USB HS PHY PLL clock.
1701 *
1702 * This function disables USB HS PHY PLL clock.
1703 */
1704void CLOCK_DisableUsbhs0PhyPllClock(void);
1705
1706/*~ @brief Enable USB HS PHY PLL clock.
1707 *
1708 * This function enables the internal 480MHz USB PHY PLL clock.
1709 *
1710 * @param src USB HS PHY PLL clock source.
1711 * @param freq The frequency specified by src.
1712 * @retval true The clock is set successfully.
1713 * @retval false The clock source is invalid to get proper USB HS clock.
1714 */
1715bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
1716
1717/*~ @brief Disable USB HS PHY PLL clock.
1718 *
1719 * This function disables USB HS PHY PLL clock.
1720 */
1721void CLOCK_DisableUsbhs1PhyPllClock(void);
1722
1723/* @} */
1724
1725/*~
1726 * @name Clock Output Inferfaces
1727 * @{
1728 */
1729
1730/*~
1731 * @brief Set the clock source and the divider of the clock output1.
1732 *
1733 * @param selection The clock source to be output, please refer to @ref clock_output1_selection_t.
1734 * @param divider The divider of the output clock signal, please refer to @ref clock_output_divider_t.
1735 */
1736void CLOCK_SetClockOutput1(clock_output1_selection_t selection, clock_output_divider_t divider);
1737
1738/*~
1739 * @brief Set the clock source and the divider of the clock output2.
1740 *
1741 * @param selection The clock source to be output, please refer to @ref clock_output2_selection_t.
1742 * @param divider The divider of the output clock signal, please refer to @ref clock_output_divider_t.
1743 */
1744void CLOCK_SetClockOutput2(clock_output2_selection_t selection, clock_output_divider_t divider);
1745
1746/*~
1747 * @brief Get the frequency of clock output1 clock signal.
1748 *
1749 * @return The frequency of clock output1 clock signal.
1750 */
1751uint32_t CLOCK_GetClockOutCLKO1Freq(void);
1752
1753/*~
1754 * @brief Get the frequency of clock output2 clock signal.
1755 *
1756 * @return The frequency of clock output2 clock signal.
1757 */
1758uint32_t CLOCK_GetClockOutClkO2Freq(void);
1759
1760/*~ @} */
1761
1762#if defined(__cplusplus)
1763}
1764#endif /* __cplusplus */
1765
1766/* @} */
1767
1768#endif /* _FSL_CLOCK_H_ */