MIMXRT11xx/include/semc.h

/*NB_REVISION*/
 
/*NB_COPYRIGHT*/


 
#ifndef  __SEMC_H
#define  __SEMC_H
#include <predef.h>
#include <stdint.h>
#include <cpu_pins.h>
 
 
/* These configuration enums are documented with the SOMRT1061 SEMC API
 * (MIMXRT10xx/include/semc.h); the values are identical, except the
 * non-multiplexed SEMC_AddrMux_t value is named None here (Bus there). */
enum class SEMC_BusWidth_t {
    Width_8     = 0,
    Width_16    = 1,
};
 
enum class SEMC_AddrMux_t {
    Mux     = 0,
    AdvMux  = 1,
    None    = 2,
};
 
enum class SEMC_ColAddrWidth_t {
    Width_12 = 0,
    Width_11 = 1,
    Width_10 = 2,
    Width_9  = 3,
    Width_8  = 4,
    Width_7  = 5,
    Width_6  = 6,
    Width_5  = 7,
    Width_4  = 8,
    Width_3  = 9,
    Width_2  = 10,
    Width_0  = 12, // Do not configure ADDR Pins
};
 
enum class SEMC_ClkMode_t {
    Async = 0,
    Sync  = 1,
};
 
enum class SEMC_Burst_t {
    Burst_1 = 0,
    Burst_2 = 1,
    Burst_4 = 2,
    Burst_8 = 3,
    Burst_16 = 4,
    Burst_32 = 5,
    Burst_64 = 6,
};
 
// Configuration for an SEMC chip select. Each control register can be set
//  through its individual bit fields or written whole through the CR0/CR1/
//  CR2 overlay values. Timing fields are in SEMC clock cycles.
struct SEMC_cfg_t {
    // Control Register 0: basic interface configuration.
    union {
        struct {
            SEMC_BusWidth_t     busWidth       : 1;  // Data bus width (8-bit or 16-bit)
            SEMC_ClkMode_t      clkMode        : 1;  // Clock mode (asynchronous or synchronous)
            uint8_t             RESERVED0      : 2;  // Reserved, must be 0
            SEMC_Burst_t        burstLen       : 3;  // Burst transfer length (synchronous mode)
            uint8_t             RESERVED1      : 1;  // Reserved, must be 0
            SEMC_AddrMux_t      muxMode        : 2;  // Address/data multiplexing mode
            bool                advPol         : 1;  // Address valid (ADV) signal polarity
            bool                advHoldLvl     : 1;  // ADV signal hold level
            SEMC_ColAddrWidth_t colAddrWidth   : 4;  // Column address bit width
        };
        uint32_t CR0;  // Direct access to complete Control Register 0
    };
 
    // Control Register 1: setup/hold/enable timing for chip select,
    //  address, read enable, and write enable signals.
    union {
        struct {
            uint8_t rd_en_hi    : 4;  // Read enable high period (async only)
            uint8_t rd_en_lo    : 4;  // Read enable low pulse width (async only)
            uint8_t we_en_hi    : 4;  
            uint8_t we_en_lo    : 4;  
            uint8_t addr_hold   : 4;  // Address hold time
            uint8_t addr_setup  : 4;  // Address setup time
            uint8_t cs_hold_min : 4;  // Minimum chip select hold time after cycle end
            uint8_t cs_setup    : 4;  // Chip select setup time before address valid
        };
        uint32_t CR1;  // Direct access to complete Control Register 1
    };
    // Control Register 2: extended timing -- write data timing, latency,
    //  read cycle length, turnaround, and minimum chip select interval.
    union {
        struct {
            uint8_t rd_hold      : 4;  // Read data hold time (sync/burst only)
            uint8_t cs_min_intv  : 4;  // Minimum interval between chip select assertions
            uint8_t rd_cycle     : 4;  // Total read cycle length (sync/burst only)
            uint8_t latency      : 4;  // Read data latency cycles (sync/burst only)
            uint8_t turnaround   : 4;  // Bus turnaround time between transfers (async only)
            uint8_t wr_dat_hold  : 4;  // Write data hold time (sync/burst only)
            uint8_t wr_dat_setup : 4;  // Write data setup time (sync/burst only)
        };
        uint32_t CR2;  // Direct access to complete Control Register 2
    };
    PinIO clkPin;  // Clock output pin assignment (synchronous mode only)
    PinIO csPin;   // Chip select output pin assignment
};
 
// Symbol for the Base Address of the SEMC memory region
extern uint8_t SEMC_Base[];
extern uint8_t _s_data_bus[];
extern uint8_t _e_data_bus[];
 
 
// Configure an SEMC chip select for the external data bus.
//  baseAddr: base address of the memory region within the SEMC address
//            space (see SEMC_Base) that the chip select will decode.
//  siz:      size of the region in bytes.
//  cfg:      the bus width, mux mode, pins, and timing to use.
//  The two overloads accept a temporary or a named configuration structure.
void ConfigureSEMC(uint32_t baseAddr, uint32_t siz, SEMC_cfg_t &&cfg);
 
void ConfigureSEMC(uint32_t baseAddr, uint32_t siz, SEMC_cfg_t &cfg);
 
#endif   /* ----- #ifndef __SEMC_H  ----- */