MIMXRT10xx/include/semc.h

/*NB_REVISION*/
 
/*NB_COPYRIGHT*/

 
#ifndef  __SEMC_H
#define  __SEMC_H
 
#include <predef.h>
#include <stdint.h>
#include <cpu_pins.h>
 

 

enum class SEMC_BusWidth_t : uint8_t {
    Width_8     = 0,  
    Width_16    = 1   
};

enum class SEMC_AddrMux_t: uint8_t  {
    Mux     = 0,  
    AdvMux  = 1,  
    Bus     = 2   
};

enum class SEMC_ColAddrWidth_t : uint8_t {
    Width_12 = 0,   
    Width_11 = 1,   
    Width_10 = 2,   
    Width_9  = 3,   
    Width_8  = 4,   
    Width_7  = 5,   
    Width_6  = 6,   
    Width_5  = 7,   
    Width_4  = 8,   
    Width_3  = 9,   
    Width_2  = 10,  
    Width_0  = 12   
};

enum class SEMC_ClkMode_t : uint8_t {
    Async = 0,  
    Sync  = 1   
};

enum class SEMC_Burst_t : uint8_t {
    Burst_1  = 0,  
    Burst_2  = 1,  
    Burst_4  = 2,  
    Burst_8  = 3,  
    Burst_16 = 4,  
    Burst_32 = 5,  
    Burst_64 = 6   
};
 

struct SEMC_cfg_t {
    union {
        struct {
            SEMC_BusWidth_t     busWidth       : 1;  
            SEMC_ClkMode_t      clkMode        : 1;  
            uint8_t             RESERVED0      : 2;  
            SEMC_Burst_t        burstLen       : 3;  
            uint8_t             RESERVED1      : 1;  
            SEMC_AddrMux_t      muxMode        : 2;  
            bool                advPol         : 1;  
            bool                advHoldLvl     : 1;  
            SEMC_ColAddrWidth_t colAddrWidth   : 4;  
        };
        uint32_t CR0;  
    };

    union {
        struct {
            uint32_t cs_setup    : 4; 
            uint32_t cs_hold_min : 4; 
            uint32_t addr_setup  : 4; 
            uint32_t addr_hold   : 4; 
            uint32_t wr_en_lo    : 4; 
            uint32_t wr_en_hi    : 4; 
            uint32_t rd_en_lo    : 4; 
            uint32_t rd_en_hi    : 4; 
        };
        uint32_t CR1;  
    };
    
    union {
        struct {
            uint32_t wr_dat_setup : 4; 
            uint32_t wr_dat_hold  : 4; 
            uint32_t addr_wr_hold : 4; 
            uint32_t turnaround   : 4; 
            uint32_t latency      : 4; 
            uint32_t rd_cycle     : 4; 
            uint32_t cs_min_intv  : 4; 
            uint32_t rd_hold      : 4; 
        };
        uint32_t CR2;  
    };
    
    PinIO clkPin;  
    PinIO csPin;   
};
 
 
// Symbol for the Base Address of the SEMC memory region
extern uint8_t SEMC_Base[];
extern uint8_t _s_data_bus[];
extern uint8_t _e_data_bus[];
 

void ConfigureSEMC(uint32_t baseAddr, uint32_t siz, SEMC_cfg_t &&cfg);
 
 
 
 

void ConfigureSEMC(uint32_t baseAddr, uint32_t siz, SEMC_cfg_t &cfg);
 
   // groupSEMC
 
 
#endif   /* ----- #ifndef __SEMC_H  ----- */