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Quick Reference

Minimum Connections for Operation

The following signals must be connected for the module to boot and run:

REQUIRED

  • Power (3.3V)
    • P1-3 Vcc 3.3V --— 3.3VDC supply (250mA max)
    • P1-48 Vcc 3.3V --— 3.3VDC supply
    • P2-2 Vcc 3.3V --— 3.3VDC supply
    • P2-50 Vcc 3.3V --— 3.3VDC supply
  • Ground (connect ALL)
    • P1-1, P1-2, P1-49, P1-50
    • P2-1, P2-14, P2-46, P2-49
  • Reset (P1-28 RESET) – typically tied to 3.3V through a 10k pull-up
  • Ethernet (100-version: on-module RJ-45 is ready; 200-version: bring TX+/TX-/RX+/RX-/CT taps to external RJ-45)
Signal Pins Why Required
Vcc 3.3V P1-3, P1-48, P2-2, P2-50 Main supply (250 mA max)
GND P1-1, P1-2, P1-49, P1-50 Return path; connect all for low impedance
GND P2-1, P2-14, P2-46, P2-49 Return path
RESET P1-28 Active-low reset input (10 k pull-up to 3.3V)

Optional but recommended:

Signal Pins When Needed
AD_VREFP P2-5 External ADC reference (else internal reference is used)
USB (P3) P3-1..4 USB device port (VBUSEN, D-, ID, D+)
Debug UART P2-34, P2-35 UART0 RX/TX for serial console (NetBurner serial port 2)
Ethernet TIP P1-9 (TIP) EBI buffer "Transfer In Progress" – only relevant when EBI is used
Note
Simplest possible carrier board: Connect 3.3V power, ground, route Ethernet, and tie P1-28 to 3.3V through a 10 k resistor. The module will boot, bring up the network stack, and be accessible.

Connector Pinout

Two 50-pin 0.1-inch 2.54 mm dual-in-line headers. Pin 1 is at the top-left of each connector. A large fraction of P1 is committed to the External Bus Interface (EBI), which carries the on-module SDRAM bus through bus-buffer chips out to the header for optional external memory-mapped expansion. EBI signals are marked EBI_BUF.* and are HiZ on the header until EnableExtBusBuff(true) is called.

Header P1 (Left):

ODD EVEN Note
GND 1 2 GND
Vcc3.3 3 4 PC8 (NWE) EBI Write Enable / GPIO / Timer 7
PA22 5 6 PC14 (NCS0) USART1 RK / GPIO / Bus CS / CAN1 TX
PD19 7 8 PC11 (NRD) Serial Port 6 / GPIO / Bus Read / Timer 8
TIP 9 10 PD15 EBI Buffer enable / GPIO
NWR1 11 12 (D0) EBI byte select / EBI buffered data 0
(BA0) 13 14 (D2) EBI bank address / EBI buffered data 2
(D4) 15 16 (D1) EBI buffered data 4 / EBI buffered data 1
PC13 17 18 (D3) GPIO / EBI buffered data 3
(D6) 19 20 (D5) EBI buffered data 6 / 5
(D8) 21 22 (D7) EBI buffered data 8 / 7
(D10) 23 24 (D9) EBI buffered data 10 / 9
(D12) 25 26 (D11) EBI buffered data 12 / 11
(D14) 27 28 (D13) EBI buffered data 14 / 13
NRST 29 30 (D15) Reset input / EBI buffered data 15
PA6 31 32 (A0/NSB0) GPIO/UART1 TX / EBI address 0 (buffered)
(A2) 33 34 PC19 (A1) EBI A2 (buffered) / EBI A1 + GPIO + PWM
(A4) 35 36 (A3) EBI A4 / A3 (buffered)
(A6) 37 38 (A5) EBI A6 / A5 (buffered)
(A8) 39 40 (A7) EBI A8 / A7 (buffered)
(A10) 41 42 (A9) EBI A10 / A9 (buffered)
PC30 43 44 (A11) GPIO / EBI A11 (buffered)
PA19 45 46 (A13) GPIO / EBI A13 (buffered)
GND 47 48 Vcc 3.3V
GND 49 50 GND

P1 GPIO is limited to 11 pins (PC8, PA22, PC14, PD19, PC11, PD15, PC13, PA6, PC19, PC30, PA19); the rest are EBI bus signals that are only useful as GPIO if you disable EBI buffering and accept that all external bus access goes away.

Header P2 (Right)

ODD EVEN Note
GND 1 2 Vcc 3.3V
PB0 3 4 PB1 USART0 RX / USART0 TX
PA17 5 6 PC12 QSPI / GPIO / CAN1 RX / Timer 8
VREFP 7 8 PD30 ADC reference / UART3 TX
PA2 9 10 PD18 DAC trigger / UART4 RX
PB13 11 12 PA5 (or PB5) GPIO/SCK0 / UART1 RX (multiplexed)
PA8 13 14 GND AFE0 ADTRG / Ground
PD24 15 16 PA28 GPIO / GPIO
PA26 17 18 PA27 GPIO / GPIO
PA1 19 20 PA29 EBI A18 / GPIO
PA21 21 22 PB4 USART1 RX / USART1 TX (TWI1 SDA alt)
PD28 23 24 PD31 Serial 5 RX / Serial 5 TX
PD22 25 26 PD27 SPI0 SPCK / SPI0 NPCS3
PD20 27 28 PD21 SPI0 MISO / SPI0 MOSI
PB2 29 30 PD12 CAN0 TX / GMAC GRX3 (RMII alt)
PA23 31 32 PA24 USART1 SCK / USART1 RTS
PA25 33 34 PA9 USART1 CTS / UART0 RX (Serial 2)
PA10 35 36 PA30 UART0 TX (Serial 2) / GPIO
PD11 37 38 PB3 GMAC GRX2 / USART0 RTS
PA3 39 40 PA31 TWI0 SDA / SPI0 NPCS1
PD25 41 42 PA4 UART2 RX / TWI0 SCL / UART1 TX
PA13 43 44 PD26 QSPI MOSI / UART2 TX
PA14 45 46 GND QSPI SCK / Ground
PA12 47 48 PA11 QSPI MISO / QSPI CS
GND 49 50 (NC)

USB Connector (P3)

P3 Pin Signal Description
1 VCCUSB USB VBUS enable (PC16, GPIO; voltage-divided for 5 V tolerance)
2 USB.D_N USB data negative
3 USB.ID USB ID (PA7)
4 USB.D_P USB data positive

The USB connector is intended for USB Device operation; signals route directly to the SAM E70's high-speed USB controller via internal magnetics and ESD protection on the module.

Ethernet Connector (200-Version 10-Pin Header)

The 200 version omits the on-module RJ-45 and exposes the magnetics-side signals on a 10-pin header so the user can place the jack remotely or add PoE. The 100 version provides a built-in RJ-45 and these signals are not exposed.

Pin Signal Description
1 TX- Transmit -
2 TX+ Transmit +
3 TXCT Transmit center tap (driven by module)
4 RX+ Receive +
5 RX- Receive -
6 RXCT Receive center tap (driven by module)
7 GND Ground
8 N/C Not connected
9 LED Link/activity LED sink
10 LED Speed LED sink

Power

Parameter Value
Supply voltage 3.3 V DC
Typical current 100 mA
Maximum current 250 mA
Supply pins P1-3, P1-48, P2-2, P2-50
Ground pins P1-1, P1-2, P1-49, P1-50; P2-1, P2-14, P2-46, P2-49
Internal regs On-module 1.2 V (VDDCORE), USB analog rails
AD_VREFP P2-5 (external optional reference)

The module has no battery-backed domain on the headers – the SAM E70's general-purpose backup registers are inside the MCU and depend on whatever supply you provide. There is no separate "Vstby" pin.

Peripheral Availability Summary

Serial Ports

NetBurner Port # Hardware Module Header Pins (default route) Notes
0 USART0 P2-3 (RX), P2-4 (TX) RTS = P2-38, CTS = P2-29; SCK = P2-11
1 USART1 P2-21 (RX), P2-22 (TX) RTS = P2-32, CTS = P2-33; SCK = P2-31
2 UART0 P2-34 (RX), P2-35 (TX) –
3 UART1 P2-12 (RX) or P1-31 (TX) / P2-42 (TX) / P2-44 (TX) Multiple TX options
4 UART2 P2-41 (RX), P2-44 (TX) –
5 UART3 P2-7 (TX), P2-23 (RX) / P2-24 (TX) –
6 UART4 P2-10 (RX), P1-7 (TX) –

USART0 and USART1 additionally support ISO7816, IrDA, RS-485, Manchester, and SPI modes. USART1 supports LON mode.

Communications

Bus Where
SPI0 SCK=P2-25, MISO=P2-27, MOSI=P2-28, NPCS0=P2-29, NPCS1=P2-40/P2-41, NPCS2=P2-30, NPCS3=P2-26
QSPI QSCK=P2-45, QCS=P2-48, QIO0=P2-43, QIO1=P2-47, QIO2=P2-8, QIO3=P2-24 (also usable as single-bit SPI)
TWI0 SDA=P2-39, SCL=P2-42
TWI1 SDA=P2-22, SCL=P2-12 (when P2_12_USE_B5 selected)
TWI2 SDA=P2-26, SCL=P2-23
CAN0 TX=P2-29, RX=P2-38
CAN1 TX=P1-6 / P2-30, RX=P2-6 / P2-23
USB P3 connector (USB device on SAM E70 HS USB)

Analog

Function Channels available at headers
AFE0 (12-bit ADC) AD0 (P2-21), AD1 (P2-7), AD3 (P2-9), AD5 (P2-29 alt / P2-34 alt), AD6 (P2-10 alt), AD8 (P1-44 alt), AD10 (P2-3 alt)
AFE1 (12-bit ADC) AD0 (P1-13), AD1 (P2-22), AD3 (P2-23), AD5 (P1-44 alt), AD6 (P2-10 alt)
DAC (12-bit) DAC0 = P2-15 (alt), DAC1 = (internal mux)
Analog comparator One ACC channel selectable across AFE inputs
Reference AD_VREFP on P2-5 (external optional), AD_VREFN on-module ground

For the complete AFE channel-to-pin map see the Hardware Design Guide.

Storage

  • On-module 2 MB parallel flash (memory-mapped via EBI; transparent to the application)
  • On-module 8 MB SDRAM (IS42S16400J, accessed transparently via EBI)
  • On-module 384 kB embedded multi-port SRAM (TCM/system RAM, inside the SAM E70)
  • External SD/MMC supported via the HSMCI controller on PA9/PA10/PA26/PA27/PA28/PA30 – on the dev board these pins land on P2-34, P2-35, P2-17, P2-18, P2-16, P2-36
  • External QSPI flash supported via the QSPI controller (P2 pins 8, 24, 43, 45, 47, 48)

Ethernet

  • One 10/100 Mbps port via on-module KSZ8081 RMII PHY
  • IEEE 1588 PTP support (GTSUCOMP signal on P2-4 alt or P2-37 alt)
  • IEEE 802.3az Energy-Efficient Ethernet supported
  • IEEE 802.1AS time-stamping and 802.1Qav AVB credit-based traffic shaping in hardware
  • 100-version: on-module RJ-45 (J2)
  • 200-version: 10-pin breakout header for external jack

Serial Port to Hardware-Module Mapping

The NetBurner software API numbers serial ports from 0 to 6. The SAM E70 has two USART blocks and five UART blocks; mapping is per Table 5 of the datasheet:

NetBurner Port Hardware Module Software open API
0 USART0 OpenSerial(0, baud, ...)
1 USART1 OpenSerial(1, baud, ...)
2 UART0 OpenSerial(2, baud, ...)
3 UART1 OpenSerial(3, baud, ...)
4 UART2 OpenSerial(4, baud, ...)
5 UART3 OpenSerial(5, baud, ...)
6 UART4 OpenSerial(6, baud, ...)

USART0 and USART1 (NetBurner ports 0 and 1) can additionally be configured as SPI masters via the USART SPI mode. USART1 (port 1) supports LON. The standard NetBurner serial driver covers asynchronous mode; for the special modes consult the SAM E70 documentation.

External Bus Interface (EBI)

The SAM E70's EBI controller manages the on-module SDRAM and is also brought out to P1 through external 16-bit buffer chips (Texas Instruments SN74LVTH16245A) so a carrier board can add memory-mapped external peripherals or extra memory.

Signal group P1 pins (data + address + control)
Data (buffered) EBI_BUF.D0 through EBI_BUF.D15 – P1 pins 12, 14, 13, 15, 16, 18, 17, 19, 20, 21, 22, 23, 24, 25, 26, 27
Address (buffered) EBI_BUF.A0/NSB0 through EBI_BUF.A14 – P1 pins 30, 32, 33, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46
Byte-select (buf) EBI_BUF.NWR1/NSB1 – P1 pin 11
Bus control NWE (P1-4, NWrite Enable), NRD (P1-8, NRead), NCS0..NCS3 (P1-6, P1-5, –, P1-7)
Buffer "in progress" TIP – P1 pin 9 (must be wired correctly when EBI is used)
Reset NRST – P1 pin 28

By default the buffer chips are disabled and the buffered P1 pins float at HiZ. Call EnableExtBusBuff(true) in your application to drive them, and EnableExtBusBuff(false) to release them when not in use (reduces EMI and lets NRD be repurposed as GPIO).

Important: when EBI buffers are enabled, every buffered P1 pin is committed to its EBI function. Plan your carrier-board signal usage accordingly.

Common Code Patterns

Blink an LED on P2 Pin 15

#include <pins.h>
#include <ucos.h>
void UserMain(void *pd)
{
init();
while (1)
{
P2[15] = 1; // drive high
OSTimeDly(TICKS_PER_SECOND / 2);
P2[15] = 0; // drive low
OSTimeDly(TICKS_PER_SECOND / 2);
}
}

If the application is targeting the DEV-MOD-105 dev board, bsp_devboard.h provides LED1 through LED8 macros so you can write LED1 = 1 / LED1 = 0 directly.

Read a GPIO Input on P2 Pin 13

#include <pins.h>
bool ReadInput()
{
P2[13].hiz(); // configure as input
return (bool)P2[13]; // read the line
}

Open a Serial Port (USART0 on P2-3 and P2-4)

#include <serial.h>
#include <pins.h>
#include <pinconstant.h>
void UserMain(void *pd)
{
init();
// Mux the pins onto USART0
P2[3].function(PINP2_3_RXD0);
P2[4].function(PINP2_4_TXD0);
int fd = OpenSerial(0, 115200, 1, 8, eParityNone);
writestring(fd, "Hello from MODM7AE70\r\n");
while (1) { OSTimeDly(TICKS_PER_SECOND); }
}

The pin-function constants come from pinconstant.h; each P-pin define lists its available Peripheral A/B/C/D options.

Read an ADC Channel (AFE0 input on P2 Pin 13)

#include <hal.h>
#include <pins.h>
void UserMain(void *pd)
{
init();
// P2[13] = PA8 is AFE0 external trigger; use a dedicated AFE-input pin instead
// For example, P2[34] = PA9 (URXD0) or P2[10] = PD18 carry AFE alt functions on
// the MODM7AE70. Consult the data sheet for AFE channel-to-pin mapping.
// The example below uses NetBurner's high-level ADC API:
StartADCConversion(0);
while (!ADCDoneFlag) {;}
uint32_t raw = ReadADCResult(0);
iprintf("AFE0 ch0 = %lu\r\n", raw);
}

For full AFE configuration including sample rate, gain, and differential mode see the SAM E70 reference manual.

Physical Specifications

Parameter Value
Module dimensions 2.60" x 2.00" (66.0 mm x 50.8 mm)
Weight 1 oz (28 g)
Mounting holes 2 x 0.125" (3.18 mm) dia
Operating temperature -40 C to +85 C
Headers Two 25x2 SIP, 0.1" (2.54 mm) pitch, S2011E-25-ND
Ethernet (100-ver.) On-module RJ-45
Ethernet (200-ver.) 10-pin 0.1" header for external RJ-45
USB connector 4-pin header (P3) -- mini-USB position depopulated
Part numbers MODM7AE70-100IR (RJ-45 version), MODM7AE70-200IR (header version)

Pin Index (Sorted by Function)

P1 Connector

Power / Ground

Pin Signal
3 Vcc 3.3 V
48 Vcc 3.3 V
1, 2, 47, 49, 50 GND

Reset

Pin Signal Note
28 NRST Active-low reset, 10 k pull-up to 3.3 V

General-Purpose I/O Pins (limited – the rest of P1 is committed to EBI)

Pin Port Notes
4 PC8 EBI NWE (alt A) / Timer 7 (alt B)
5 PA22 USART1 RK (alt A) / PWM ext-trigger (alt B) / EBI NCS2 (alt C)
6 PC14 EBI NCS0 (alt A) / Timer 8 clock (alt B) / CAN1 TX (alt C)
7 PD19 EBI NCS3 (alt A) / USART2 CTS (alt B) / Serial 6 TX (alt C)
8 PC11 EBI NRD (alt A) / Timer 8 line A (alt B)
9 TIP EBI buffer transfer-in-progress signal – output from the buffer logic
10 PD15 GPIO; available as a free pin
13 PC13 EBI NWAIT (alt A); pin is tied to SDRAM signal, see warning
31 PA6 PCK0 output (alt B) / UART1 TX (alt C) / Serial 3 TX (alt C)
33 PC19 EBI A1 (alt A) / PWM0 H2 (alt B)
44 PC30 EBI A12 (alt A) / Timer 5 line B (alt B)
47 PA19 PWM0 L0 (alt B) / EBI A15 (alt C) / I2SC1 MCK (alt D)

External Bus Interface (EBI) Buffered Signals

Pin Signal Pin Signal
11 EBI_BUF.NWR1/NSB1 30 EBI_BUF.A0/NSB0
12 EBI_BUF.D0 32 EBI_BUF.A2
13 EBI_BUF.D1 33 EBI_BUF.A3
14 EBI_BUF.D2 35 EBI_BUF.A4
15 EBI_BUF.D3 36 EBI_BUF.A5
16 EBI_BUF.D4 37 EBI_BUF.A6
17 EBI_BUF.D5 38 EBI_BUF.A7
18 EBI_BUF.D6 39 EBI_BUF.A8
19 EBI_BUF.D7 40 EBI_BUF.A9
20 EBI_BUF.D8 41 EBI_BUF.A10
21 EBI_BUF.D9 42 EBI_BUF.A11
22 EBI_BUF.D10 43 EBI_BUF.A12
23 EBI_BUF.D11 45 EBI_BUF.A13
24 EBI_BUF.D12 46 EBI_BUF.A14
25 EBI_BUF.D13
26 EBI_BUF.D14
27 EBI_BUF.D15

P2 Connector

Power / Ground

Pin Signal
2 Vcc 3.3 V
50 Vcc 3.3 V
1, 14, 46, 49 GND

Analog Reference

Pin Signal
5 AD_VREFP

GPIO Pins and Primary Alt Functions

Pin Port Primary alt (peripheral A / B / C / D) – selected highlights
3 PB0 PWM0_H0 / – / USART0 RX (Serial 0) / SSC TF
4 PB1 PWM0_H1 / GTSUCOMP / USART0 TX (Serial 0) / SSC TK
6 PC12 – / Timer 8 line B / CAN1 RX / –
7 PD30 UART3 TX (Serial 5) / – / – / ISI D10
8 PA17 QSPI IO2 / PCK1 / PWM0_H3 / –
9 PA2 PWM0_H1 / – / DAC trigger / –
10 PD18 – / – / UART4 RX (Serial 6) / –
11 PB13 PWM0_L2 / PCK0 / USART0 SCK / –
12 PA5 (or PB5) PWM1_L3 (PA5) / ISI D4 / UART1 RX (Serial 3); TWI1 SCL (alt A on PB5)
13 PA8 PWM1_H3 / AFE0 ADTRG / – / –
15 PD24 PWM0_L0 / SSC RF / Timer 11 clock / ISI HSYNC
16 PA28 USART1 DSR / Timer 1 clock / HSMCI CDA / PWM1_FI2
17 PA26 USART1 DCD / Timer 2 line A / HSMCI DA2 / PWM1_FI1
18 PA27 USART1 DTR / Timer 2 line B / HSMCI DA3 / ISI D7
19 PA1 PWM0_L0 / Timer 0 line B / EBI A18 / I2SC0 SCK
20 PA29 USART1 RI / Timer 2 clock / – / –
21 PA21 USART1 RX (Serial 1) / PCK1 / PWM1_FI0 / –
22 PB4 TWI1 SDA / PWM0_H2 / – / USART1 TX (Serial 1)
23 PD28 UART3 RX (Serial 5) / CAN1 RX / TWI2 SCL / ISI D9
24 PD31 QSPI IO3 / UART3 TX (Serial 5 alt) / PCK2 / ISI D11
25 PD22 PWM0_H2 / SPI0 SPCK / Timer 11 line B / ISI D0
26 PD27 PWM0_L3 / SPI0 NPCS3 / TWI2 SDA / ISI D8
27 PD20 PWM0_H0 / SPI0 MISO / GTSUCOMP / –
28 PD21 PWM0_H1 / SPI0 MOSI / Timer 11 line A / ISI D1
29 PB2 CAN0 TX / – / USART0 CTS / SPI0 NPCS0
30 PD12 GMAC GRX3 / CAN1 TX / SPI0 NPCS2 / ISI D6
31 PA23 USART1 SCK / PWM0_H0 / EBI A19 / PWM1_L2
32 PA24 USART1 RTS / PWM0_H1 / EBI A20 / ISI PCK
33 PA25 USART1 CTS / PWM0_H2 / EBI A23 / HSMCI MCCK
34 PA9 UART0 RX (Serial 2) / ISI D3 / PWM0_FI0 / –
35 PA10 UART0 TX (Serial 2) / PWM0 EXTRG0 / SSC RD / –
36 PA30 PWM0_L2 / PWM1 EXTRG0 / HSMCI DA0 / I2SC0 DO
37 PD11 GMAC GRX2 / PWM0_H0 / GTSUCOMP / ISI D5
38 PB3 CAN0 RX / PCK2 / USART0 RTS (Serial 0) / ISI D2
39 PA3 TWI0 SDA / LONCOL1 / PCK2 / –
40 PA31 SPI0 NPCS1 / PCK2 / HSMCI DA1 / PWM1_H2
41 PD25 PWM0_L1 / SPI0 NPCS1 / UART2 RX (Serial 4) / ISI VSYNC
42 PA4 TWI0 SCL / Timer 0 clock / UART1 TX (Serial 3) / –
43 PA13 QSPI IO0 / PWM0_H2 / PWM1_L1 / –
44 PD26 PWM0_L2 / SSC TD / UART2 TX (Serial 4) / UART1 TX (Serial 3 alt)
45 PA14 QSPI SCK / PWM0_H3 / PWM1_H1 / –
47 PA12 QSPI IO1 / PWM0_H1 / PWM1_H0 / –
48 PA11 QSPI CS / PWM0_H0 / PWM1_L0 / –

For the full set of alt functions on every pin, see the Hardware Design Guide Appendix A.