DEV-MOD-105 Development Board

The DEV-MOD-105 is the development carrier for the MODRT1171 system-on-module. Plug a MODRT1171 into the dev board's two 50-pin sockets and you have an immediately useful prototyping platform: power input, dual Ethernet (provided by the module itself), two configurable UARTs (RS-232, RS-485, or USB-Serial), a microSD socket, an SPI expansion header sized for a WiFi co-processor, a battery-backed RTC, eight status LEDs, an eight-position DIP switch, a reset push-button, and every module pin brought out to breakout headers for wiring access.

This guide walks through each feature, shows which module pins it uses, and notes the small number of co-existence rules you should keep in mind when combining features. Use it alongside the Hardware Design Guide and the Software Developer Guide.

Warning: Imporant Version Note This guide is specific to the MODRT1171 revision 1.5 and DEV-MOD-105 revision 1.1. These assemblies are for development only. The I2C and SPI primary pins will be modified in 1171 revision 1.6 to match the NetBurner MOD54417 module for compatibility. This guide will be updated when 1171 revision 1.6 is released.

Board Features

Feature	What It Provides
Power input	DC barrel jack + on-board 3.3V buck regulator
Reset push-button (SW1)	Drives module RSTI input through a debounce capacitor
UART0 (LPUART1)	RS-232 (DB-9 J7) and USB-Serial (USB Type-C J3) – jumper-selectable
UART1 (LPUART2)	RS-232 (DB-9 J8) and RS-485 (6-pin header P3) – jumper-selectable
microSD socket (J6)	SD card storage in 1-bit SPI mode
WiFi expansion header (P7)	7 signals + 3.3V + GND for an SPI WiFi co-processor (or any SPI device)
Real-Time Clock (U2)	RV-3032 with battery backup (BT1), 32.768 kHz oscillator, CLKOUT, INT
8 status LEDs (LED1-LED8)	General-purpose visual indicators
8-position DIP switch (SW2)	User input or configuration switches
Breakout headers (J1, J2)	Every module pin is brought out for prototyping wiring
12 configuration jumpers (JP1-JP12)	Power source, UART routing, RS-485 termination, ADC reference, etc.
Mounting holes	Four M3 holes for enclosure mounting

Module Sockets and Breakout Headers

The MODRT1171 plugs into the dev board's P1 (left, 50-pin) and P2 (right, 50-pin) sockets. Every signal on each module connector is duplicated onto a parallel breakout header:

Module side	Dev-board socket	Dev-board breakout
P1 (50-pin)	P1	J1
P2 (50-pin)	P2	J2

J1 and J2 are simple straight passthroughs of P1 and P2 – whatever the module presents on a P1 pin is available at the corresponding J1 pin (and likewise for P2/J2). This means you can probe, wire, or extend any module signal regardless of whether the dev board also taps it for an on-board peripheral.

Powering the Board

The DEV-MOD-105 has a single 3.3V buck regulator (U7 = AP64352) that supplies both the module and on-board peripherals.

Input options (selected by jumper JP1):

JP1 position	Source
1-2	VCC_EXT – external 3.3V via test pad
2-3 (default)	VIN – DC barrel jack J4 (5-24V)
3-... (USB)	VBUS_USB – USB Type-C J3 (5V)

A green power LED (LED9, 330 Ohm) lights when the 3.3V rail is alive.

Module power pins on the connectors:

P1-48, P2-2, P2-50 = +3.3V (all three are driven from the dev-board rail)
P1-3 = Vstby / VDD_SNVS_IN (SNVS domain, also tied to 3.3V on the dev board so the RTC inside the i.MX runs immediately)
P1-1, P1-2, P1-49, P1-50, P2-1, P2-49 = GND

For battery-backed SNVS retention on a production carrier board, see the section on power sequencing in the Hardware Design Guide. On the DEV-MOD-105 the SNVS rail simply tracks +3.3V.

Reset Button

Push-button SW1 (TS-1187) drives the module's reset input (P1-28, RSTI/POR):

Normally held high through a 10 kOhm pull-up to +3.3V
Pulled to ground while SW1 is pressed; a 1 nF debounce cap (C10) suppresses contact bounce
The same line is available at J1 pin 28 if you want to add an external supervisor IC or watchdog through the breakout header

Press SW1 any time to perform a hardware reset of the module.

Serial Communication

The DEV-MOD-105 wires both module UART0 and UART1 to multiple physical interfaces, with jumpers selecting which interface drives the receive direction. Transmit goes to all attached transceivers, so you can monitor on one while talking on another.

UART0: RS-232 and USB-Serial (LPUART1)

UART0 corresponds to the MODRT1171's LPUART1 peripheral, with its native TX/RX/RTS/CTS pins. The dev board wires it to:

DB-9 RS-232 connector J7 through MAX3232 transceiver U3
USB Type-C connector J3 through FTDI FT231X USB-UART bridge U6

LPUART1 signal	Module pin	Dev-board destination
TX	MOD_P2_04	MAX3232 T1IN + FTDI RXD (both at once)
RX	MOD_P2_03	Selected by JP2 (RS-232 or USB-Serial)
RTS	MOD_P2_38	MAX3232 T2IN + FTDI CTS# (both at once)
CTS	MOD_P2_29	Selected by JP3 (RS-232 or USB-Serial)

Selecting the receive source:

Jumper	1-2 (RS-232)	2-3 (USB-Serial)
JP2	RX from MAX3232 U3	RX from FTDI U6
JP3	CTS from MAX3232 U3	CTS from FTDI U6

Move both jumpers to the same side for a fully-routed connection. Because transmit drives both transceivers simultaneously, you can use the unselected interface as a passive monitor (read-only) of outgoing traffic if you wish.

Tx/Rx LEDs: LED10 and LED11 on the FTDI side blink with USB-Serial activity.

UART1: RS-232 and RS-485 (LPUART2)

UART1 corresponds to the MODRT1171's LPUART2 peripheral. The dev board wires it to:

DB-9 RS-232 connector J8 through MAX3232 transceiver U4
RS-485 6-pin header P3 through THVD1424 transceiver U8 (full or half-duplex, with optional bus termination)

LPUART2 signal	Module pin	Dev-board destination
TX	MOD_P2_22	MAX3232 T1IN + THVD1424 D (driver input)
RX	MOD_P2_21	Selected by JP4 (MAX3232 R1OUT or THVD1424 R)
RTS (GPIO-driven)	MOD_P2_32	MAX3232 T2IN + RS-485 DE/RE direction control
CTS (GPIO-driven)	MOD_P2_33	Selected by JP5 (RS-232 CTS path)

Selecting the receive source:

Jumper	1-2 (RS-232)	2-3 (RS-485)
JP4	RX from MAX3232 U4	RX from THVD1424

RS-485 configuration jumpers:

Jumper	Function	Install when
JP7	485_HF (half/full-duplex select on THVD1424)	Half-duplex 2-wire RS-485
JP8	Ties 485_RE to 485_DE (single-line direction control)	Always, for normal DE/RE driving
JP9	485_SLR (slew-rate limit)	Long lines / low baud (reduces emissions)
JP10	485_TERM_RX (120 Ohm receive termination)	This node is at the bus end (receiver)
JP11	485_TERM_TX (120 Ohm transmit termination)	This node is at the bus end (transmitter)

The RS-485 bus connector P3 exposes both A/B (data pair) and Z/Y (second pair, for full-duplex) terminals plus two GND pins.

Warning: Caution – LPUART2 hardware flow control: the dev board provides RTS/CTS via separate GPIO pins (MOD_P2_32/33), so the SDK driver toggles them in software. The i.MX RT1170's native LPUART2_RTS_B / LPUART2_CTS_B alternate functions live on MOD_P2_23 and MOD_P2_24 – those pins are used by LED4 and LED8 on this dev board. For most applications GPIO-controlled flow control is fine; if you need wire-speed hardware RTS/CTS, route those lines through a custom carrier or accept that LED4/LED8 will follow the flow-control state.

SD Card Storage

Note: MODRT1171 revision 1.5 routes the SDIO peripheral signals in single bit mode to the microSD card interface and P2 header pins, which is not compatible with the MOD54417 and will be changed in revision 1.6.

The microSD socket (J6 = TF-01A) is wired as a generic SPI device, with the chip-select and card-detect on dedicated pins and the SCK/MISO/MOSI signals on the SPI bus shared with the WiFi expansion header.

Function	Module pin	i.MX Pad	Notes
USDHC1_CLK	MOD_P2_25	GPIO_SD_B1_01	SPI SCK; shared with WiFi P7
USDHC1_CMD	MOD_P2_27	GPIO_SD_B1_00	SPI MISO; shared with WiFi P7
USDHC1_DATA0	MOD_P2_28	GPIO_SD_B1_02	SPI MOSI; shared with WiFi P7
GPIO	MOD_P2_35	GPIO_DISP_B2_09	SPI CS; dedicated to SD card
GPIO	MOD_P2_47	GPIO_EMC_B1_39	CD; Low when a card is inserted (pull-up)

Each MOSI/MISO/CS line has a 10 kOhm pull-up to 3.3V for SD-SPI idle behaviour (R1, R2, R3, R6) and the CD line has a 10 kOhm pull-up (R4).

Note: Sharing the SPI bus with the WiFi header: see the next section. Because the two devices have separate chip-select lines (MOD_P2_35 for SD, MOD_P2_30 for WiFi), the NetBurner SDK arbitrates between them automatically – you simply use the appropriate device handle and the driver asserts the right CS.; Mode note: the dev board uses the SD card in 1-bit SPI mode rather than 4-bit native SDIO. The i.MX RT1170's USDHC1 DATA1/2/3 pins are repurposed on this board (for UART1 RTS/CTS and WiFi CS), so 4-bit SDIO is not available here. If you need 4-bit SDIO performance, design a custom carrier that keeps those lines available.

WiFi and SPI Expansion Header (P7)

Warning: The DEV-MOD-105 WiFi header is compatible with MODRT1171 revision 1.6+ only. The revision 1.5 pinout will not work.

The 9-pin NetBurner Expansion Header P7 is sized to accept a WiFi co-processor module (or any SPI device that fits the pinout). It exposes a clean SPI bus plus enable, reset, and IRQ lines, alongside 3.3V (through filter inductor L2 = 10 uH for noise isolation) and GND.

P7 Pin	Signal	Module Pin	Direction	Use
1	W_EN	MOD_P2_34	Output	WiFi enable / power-down control
2	W_CS	MOD_P2_30	Output	SPI chip-select for the WiFi co-processor
3	W_CLK	MOD_P2_25	Output	SPI clock (shared with SD card)
4	W_MISO	MOD_P2_27	Input	SPI MISO (shared with SD card)
5	W_MOSI	MOD_P2_28	Output	SPI MOSI (shared with SD card)
6	W_RST	MOD_P2_42	Output	WiFi reset
7	W_IRQ	MOD_P2_26	Input	WiFi interrupt
8	VCC3VWiFi	–	Power	+3.3V through L2
9	GND	–	–	Ground

If no WiFi module is fitted, the entire header is free for any SPI peripheral that matches this pinout (or you can wire individual signals out through J2).^M

Coexistence with the SD card: the WiFi co-processor and SD card sit on the same SPI bus with separate chip-selects. Normal SPI arbitration in software lets both run, just not simultaneously full-duplex.

Coexistence with the RTC: MOD_P2_42 is also wired to the RTC's SCL line (the RTC uses bit-banged I2C). If your application both resets a WiFi module on P7 and reads the RTC, perform the WiFi reset before the first RTC access (or re-initialise the RTC after toggling W_RST). If you are not using the WiFi header, the RTC has the line entirely to itself.

Real-Time Clock

The Microcrystal RV-3032-C7 is a low-power I2C real-time clock with a built-in 32.768 kHz crystal, a programmable CLKOUT pin, an interrupt output, and battery-backed time retention.

Function	Module pin	Notes
SCL	MOD_P2_42	4.7 kOhm pull-up to +3.3V; bit-banged in software
SDA	MOD_P2_39	4.7 kOhm pull-up to +3.3V; bit-banged in software
INT	(P6 header, not directly on module)	Accessible via P6 pin 5
CLKOUT	(P6 header, not directly on module)	Accessible via P6 pin 4
VBACKUP	BAT1 (BS-02-A1AJ010 holder)	Coin-cell input via 330 Ohm R39

The dev board has a coin-cell holder (BAT1) so the RTC keeps time when main power is off. Plug in a CR-series cell to enable time retention.

Neither SCL nor SDA on this dev board uses a native LPI2C alternate function – the NetBurner SDK drives the bus through a bit-banged or FlexIO-based I2C implementation.

Header P6 breaks out SDA, INT, CLKOUT, and GND for connecting external I2C devices on the same bus, or for using the RTC's interrupt/clock output in your application.

Status LEDs

Eight red LEDs (LED1-LED8) are mounted along one side of the board. Each is wired with its anode through a 330 Ohm resistor to the module pin, cathode to GND – drive the pin high to light the LED.

LED	Module Pin	Driving Function	Recommended Use
LED1	MOD_P2_15	USB1 D- line (no GPIO mux on the i.MX)	USB1 D- activity indicator
LED2	MOD_P2_16	USB1 D+ line (no GPIO mux on the i.MX)	USB1 D+ activity indicator
LED3	MOD_P2_31	Plain GPIO (GPIO_AD_31)	General-purpose status
LED4	MOD_P2_23	Plain GPIO (GPIO_DISP_B2_13) – also LPUART2_RTS_B alt 3	General-purpose status, or UART RTS LED
LED5	MOD_P2_37	Plain GPIO (GPIO_DISP_B2_03)	General-purpose status
LED6	MOD_P2_19	USB2 VBUS-detect input (no GPIO mux)	USB2 VBUS-present indicator
LED7	MOD_P2_20	Plain GPIO (GPIO_AD_28)	General-purpose status
LED8	MOD_P2_24	Plain GPIO (GPIO_DISP_B2_12) – also LPUART2_CTS_B alt 3	General-purpose status, or UART CTS LED

Software-driven LEDs: LED3, LED4, LED5, LED7, and LED8 are connected to general-purpose GPIO pins – you can turn them on and off with a register write.

Hardware-activity LEDs: LED1, LED2, and LED6 are wired to USB pins whose function on the i.MX RT1170 is fixed (the datasheet marks them "No Muxing"). They are not arbitrary status LEDs but instead automatically reflect USB bus state – handy as live activity indicators when you bring USB1 or USB2 traffic out to the breakout header.

Bonus on LED4 / LED8: because they sit on the native LPUART2 RTS/CTS alternate-function pins, you can configure those alts and have the LEDs visually echo serial flow-control state.

User DIP Switches

A single 8-position DIP switch package (SW2 = SMQS-08B-TP) provides eight user inputs. Each switch connects its module pin to GND when closed; each line has a 4.7 kOhm pull-up to +3.3V (R18-R26), so the pin reads high when open, low when closed.

Switch	Module Pin	Module Function (alt 0)
SW2-1	MOD_P2_13	GPIO_AD_23 (ADC2_B2)
SW2-2	MOD_P2_12	GPIO_AD_22 (ADC2_A2)
SW2-3	MOD_P2_11	GPIO_AD_21 (ADC2_B1)
SW2-4	MOD_P2_09	DAC_OUT / ADC analog 1.8V supply
SW2-5	MOD_P2_10	GPIO_AD_20 (ADC2_A1)
SW2-6	MOD_P2_07	GPIO_AD_18 (ADC2_A0)
SW2-7	MOD_P2_06	GPIO_AD_17 (ADC12_B5)
SW2-8	MOD_P2_08	GPIO_AD_19 (ADC2_B0)

Tip: because every switch line is on an ADC-capable pin, you can read these inputs as analog if you ever need to mix-detect external voltages on the same pin. With the switch open the line sits at 3.3V; with it closed it sits at GND.

Warning: SW2-4: module pin P2-9 is also the DAC analog output. With SW2-4 closed, the line is pulled to GND through the switch – which would short the DAC if you enable it. Leave SW2-4 in the open position (or treat it as a switch you only use while the DAC peripheral is disabled).

Analog Outputs and Inputs

DAC

The MODRT1171 brings the DAC output (an internal 12-bit DAC routed through op-amp U21 on the module) to module pin P2-9, accessible at the dev board on J2 pin 9. Use the NetBurner SDK's DAC API to set an output voltage; the analog signal appears at J2-9.

The same pin is wired through SW2-4 on the dev board (see Switches above), so keep SW2-4 open when the DAC is active.

ADC

The MODRT1171 exposes many ADC channels on both P1 and P2 headers. The full pinout list (ADC1 vs ADC2, channels A0-B6, etc.) is in this document (Connector Pinout) and in the Hardware Design Guide.

On the DEV-MOD-105 specifically:

ADC inputs on P1 are entirely free (no on-board peripheral taps any P1 pin other than the reset switch on P1-28).
ADC inputs on P2 pins 6, 7, 8, 10-13 are shared with DIP switches – read these as analog when the corresponding switch is open (line floats at 3.3V through 4.7k) or use them as plain digital switch inputs.
The optional VREFP jumper JP12 can tie MOD_P2_05 to +3.3V if your application wants an external reference reading on that pin. Leave JP12 open for normal use of P2-5.

Breakout Headers J1 and J2

Two 50-pin (2x25) headers expose every module pin for prototyping. J1 mirrors P1; J2 mirrors P2. Whatever signal the module presents at a P1 or P2 pin is available at the corresponding J1/J2 pin – including pins that the dev board also uses for an on-board peripheral.

This gives you:

All 50 pins of P1 available with no on-board peripheral contention (only the reset switch SW1 taps P1-28 – everything else is clean).
All 50 pins of P2 available, including the 12 pins the dev board does not tap (listed in Free Module Pins below).
Free probing access to any signal the dev board uses, for debugging or for tapping into the on-board peripheral nets externally.

Probing on a tapped pin: if you wire to a J2 pin that is also used by an on-board peripheral (e.g. an LED, a switch, the RTC), remember that your wire shares the net with whatever the dev board has on that line – you may need to remove the dev-board's load (lift the corresponding 0 Ohm resistor or LED) for clean external use.

Jumper Reference

Jumper	Default*	Function
JP1	2-3 (VIN)	3.3V regulator input source: VCC_EXT / VIN (J4 barrel jack) / VBUS_USB (USB-C)
JP2	1-2 (RS-232)	UART0 RX source: RS-232 (1-2) or USB-Serial (2-3)
JP3	1-2 (RS-232)	UART0 CTS source: RS-232 (1-2) or USB-Serial (2-3)
JP4	1-2 (RS-232)	UART1 RX source: RS-232 (1-2) or RS-485 (2-3)
JP5	installed	UART1 CTS from RS-232 transceiver
JP6	depopulated	(Reserved; not fitted on rev 1.2)
JP7	open	RS-485 half-duplex enable on THVD1424 (install for 2-wire half-duplex operation)
JP8	installed	Ties 485_RE to 485_DE for single-signal direction control
JP9	open	RS-485 slew-rate limit (install to enable, recommended for long bus or low baud)
JP10	as needed	RS-485 RX termination (install at the bus-end node only)
JP11	as needed	RS-485 TX termination (install at the bus-end node only)
JP12	open	VREFP: when installed, ties MOD_P2_05 to +3.3V

Note: *Defaults reflect typical out-of-box configuration; verify against the printing on the silkscreen of your particular board.

Co-Existence Notes and Cautions

#	Situation	What to Do
1	Needing hardware-driven UART1 RTS/CTS (native LPUART2 RTS/CTS alt-3)	Those pins are LED4 and LED8 here. Use the dev board's software-driven RTS/CTS on MOD_P2_32/33 (which the SDK supports out of the box).
2	Treating LED1 / LED2 / LED6 as software-controllable status LEDs	They sit on fixed-function USB pins and only light from USB bus state. Use LED3, LED5, LED7 (and LED4/LED8) for software status.
3	DAC output is active and DIP switch SW2-4 is closed	SW2-4 grounds the DAC output. Open SW2-4 before enabling the DAC.

Module Pin to Dev-Board Feature (P2)

DEV-MOD-105 revision 1.5:

The table below lists every P2 pin and what the dev board does with it. (All P1 pins pass straight to J1 with no on-board peripheral, except P1-28 which is also driven by reset switch SW1.)

P2 Pin	Module Signal	i.MX Pad	Dev-Board Feature	Notes
1	GND	–	GND	–
2	Vcc 3.3V	–	3.3V supply	–
3	AD_25	GPIO_AD_25	U0_RX (via JP2)	LPUART1_RX (alt 0)
4	AD_24	GPIO_AD_24	U0_TX -> MAX3232 + FTDI	LPUART1_TX (alt 0)
5	AD_34	GPIO_AD_34	VREFP via JP12 (open by default)	Free unless JP12 installed
6	AD_17	GPIO_AD_17	Switch7 (DIP SW2-7)	4.7k pull-up
7	AD_18	GPIO_AD_18	Switch6 (DIP SW2-6)	4.7k pull-up
8	AD_19	GPIO_AD_19	Switch8 (DIP SW2-8)	4.7k pull-up
9	DAC_OUT	VDDA_ADC_1P8	DAC output + Switch4 (DIP SW2-4)	Keep SW2-4 open when DAC is active
10	AD_20	GPIO_AD_20	Switch5 (DIP SW2-5)	4.7k pull-up
11	AD_21	GPIO_AD_21	Switch3 (DIP SW2-3)	4.7k pull-up
12	AD_22	GPIO_AD_22	Switch2 (DIP SW2-2)	4.7k pull-up
13	AD_23	GPIO_AD_23	Switch1 (DIP SW2-1)	4.7k pull-up
14	USB1.VBUS_5V	USB1_VBUS	(free at J2)	–
15	USB1.D_N	USB1_DN	LED1 (USB1 D- activity)	No GPIO mux
16	USB1.D_P	USB1_DP	LED2 (USB1 D+ activity)	No GPIO mux
17	USB2.D_N	USB2_DN	(free at J2)	–
18	USB2.D_P	USB2_DP	(free at J2)	–
19	USB2.VBUS_5V	USB2_VBUS	LED6 (USB2 VBUS-present)	No GPIO mux
20	AD_28	GPIO_AD_28	LED7	–
21	DISP_B2_11	GPIO_DISP_B2_11	U1_RX (via JP4)	LPUART2_RX (alt 2)
22	DISP_B2_10	GPIO_DISP_B2_10	U1_TX -> MAX3232 + THVD1424	LPUART2_TX (alt 2)
23	DISP_B2_13	GPIO_DISP_B2_13	LED4	Also LPUART2_RTS_B (alt 3)
24	DISP_B2_12	GPIO_DISP_B2_12	LED8	Also LPUART2_CTS_B (alt 3)
25	SD_B1_1	GPIO_SD_B1_01	SPI SCK (SD card + WiFi P7)	USDHC1_CLK (alt 0)
26	AD_30	GPIO_AD_30	W_IRQ (WiFi interrupt)	–
27	SD_B1_0	GPIO_SD_B1_00	SPI MISO (SD card + WiFi P7)	USDHC1_CMD (alt 0)
28	SD_B1_2	GPIO_SD_B1_02	SPI MOSI (SD card + WiFi P7)	USDHC1_DATA0 (alt 0)
29	AD_26	GPIO_AD_26	U0_CTS (via JP3)	LPUART1_CTS_B (alt 0)
30	SD_B1_5	GPIO_SD_B1_05	W_CS (WiFi chip-select)	USDHC1_DATA3 (alt 0)
31	AD_31	GPIO_AD_31	LED3	–
32	SD_B1_4	GPIO_SD_B1_04	U1_RTS (GPIO software-driven)	USDHC1_DATA2 (alt 0)
33	SD_B1_3	GPIO_SD_B1_03	U1_CTS (GPIO software-driven, via JP5)	USDHC1_DATA1 (alt 0)
34	DISP_B2_1	GPIO_DISP_B2_01	W_EN (WiFi enable)	–
35	DISP_B2_9	GPIO_DISP_B2_09	SD card chip-select	–
36	DISP_B2_5	GPIO_DISP_B2_05	(free at J2)	–
37	DISP_B2_3	GPIO_DISP_B2_03	LED5	–
38	AD_27	GPIO_AD_27	U0_RTS -> MAX3232 + FTDI	LPUART1_RTS_B (alt 0)
39	DISP_B2_6	GPIO_DISP_B2_06	RTC SDA (bit-banged I2C)	–
40	DISP_B2_4	GPIO_DISP_B2_04	(free at J2)	–
41	DISP_B2_2	GPIO_DISP_B2_02	(free at J2)	–
42	DISP_B2_7	GPIO_DISP_B2_07	W_RST + RTC SCL	One pin shared between two functions
43	DISP_B2_15	GPIO_DISP_B2_15	(free at J2)	–
44	DISP_B2_0	GPIO_DISP_B2_00	(free at J2)	–
45	DISP_B2_8	GPIO_DISP_B2_08	(free at J2)	–
46	DISP_B2_14	GPIO_DISP_B2_14	(free at J2)	–
47	EMC_B1_39	GPIO_EMC_B1_39	SD card-detect (CD)	Low when card inserted
48	EMC_B1_40	GPIO_EMC_B1_40	(free at J2)	–
49	GND	–	GND	–
50	Vcc 3.3V	–	3.3V supply	–

Free Module Pins on the DEV-MOD-105

The following pins are not tapped by any on-board peripheral and are available cleanly at the breakout headers J1 / J2.

All P1 pins (1-50) – only P1-28 (RSTI) is also driven by the reset switch SW1. Every other P1 signal – including the LPI2C / LPSPI / CAN / FlexCAN / FlexIO / GPT / additional UART / LPSR / SNVS / ADC pin sets exposed on P1 – passes straight to J1.

P2 pins that pass straight through to J2 (no on-board peripheral tap):

P2 Pin	Module Signal	Note
P2-5	AD_34	Free when JP12 is open (default)
P2-14	USB1.VBUS_5V	USB1 VBUS input (fixed-function)
P2-17	USB2.D_N	USB2 D- (fixed-function)
P2-18	USB2.D_P	USB2 D+ (fixed-function)
P2-36	DISP_B2_5	Plain GPIO
P2-40	DISP_B2_4	Plain GPIO
P2-41	DISP_B2_2	Plain GPIO
P2-43	DISP_B2_15	Plain GPIO
P2-44	DISP_B2_0	Plain GPIO
P2-45	DISP_B2_8	Plain GPIO
P2-46	DISP_B2_14	Plain GPIO
P2-48	EMC_B1_40	Plain GPIO; SEMC_RDY available on alt 0

If you need any of the alternate functions (CAN, USDHC, FlexSPI, SAI, KPP, ENET 1G, XBAR, etc.) on these pins, the Quick Start Guide lists the full alt-function table.

Module-Internal Pin Allocation

A number of i.MX RT1170 pins are committed to functions internal to the MODRT1171 module and are not exposed at P1 or P2. They never appear on the DEV-MOD-105 and cannot conflict with anything you do on the carrier. For completeness:

SDRAM (W9825G6KH-5, 64 MB): 32 i.MX EMC_B1 / EMC_B2 pins
Boot Flash (GD25Q80CEIGR) and Application Flash (W25N01GVZEIG, 128 MB): 6 GPIO_SD_B1 / GPIO_SD_B2 pins
Ethernet PHY/Switch (KSZ9893): full RGMII bus plus MDIO/MDC; KSZ9893 reset and IRQ on SNVS GPIOs
24 MHz / 32.768 kHz crystals: internal XTAL inputs
JTAG mux: P1 LPSR pins 34-39 carry i.MX JTAG_MUX_* alternate functions; repurposable as GPIO/UART/SPI when JTAG is not in use – see the Hardware Design Guide for boot-time considerations

See the MODRT1171 Hardware Design Guide for the full module-internal allocation, plus the recovery-jumper, power-sequencing, and routing guidance that applies if you go on to build your own carrier board.