xdmac.h

#ifndef  __XDMAC_H
#define  __XDMAC_H
/*NB_REVISION*/
 
/*NB_COPYRIGHT*/
#include <same70.h>
#include <basictypes.h>
#include <nbrtos.h>
 
struct dma_descview_0;
struct dma_descview_1;
struct dma_descview_2;
struct dma_descview_3;
 
struct dma_transfer_desc_t
{
    union
    {
        dma_transfer_desc_t *pNext;
        dma_descview_0      *pNext_0;
        dma_descview_1      *pNext_1;
        dma_descview_2      *pNext_2;
        dma_descview_3      *pNext_3;
        uint32_t            nda;
    };
    uint32_t ubCtrl;
};
struct dma_descview_0 : public dma_transfer_desc_t
{
    uint32_t addr;
};
 
struct dma_descview_1 : public dma_transfer_desc_t
{
    uint32_t src;
    uint32_t dst;
};
 
struct dma_descview_2 : public dma_transfer_desc_t
{
    uint32_t src;
    uint32_t dst;
    uint32_t cfg;
};
 
struct dma_descview_3 : public dma_transfer_desc_t
{
    uint32_t src;
    uint32_t dst;
    uint32_t cfg;
    uint32_t blkCtrl;
    uint32_t stride;
    uint32_t srcuStride;
    uint32_t dstuStride;
};
 
#include <type_traits>
struct XdmaCh_t;
extern "C" XdmaCh_t * xdmacGetFreeCh();
extern "C" void xdmacReleaseCh(XdmaCh_t *xdmaCh);
 
 
struct XdmaChCtx_t
{
    uint32_t lastISR;
    uint32_t stickyISR;
    void (* isr) (XdmaCh_t *);
    void reset();
};
 
struct XdmaCh_t : public XdmacChid
{
    private:
    static XdmaChCtx_t      ctx[XDMACCHID_NUMBER];
    static uint32_t         bInUse;
    public:
    enum TransType_t
    {
        Mem2Mem         = XDMAC_CC_TYPE_MEM_TRAN_Val,
        Periph          = XDMAC_CC_TYPE_PER_TRAN_Val
    };
    enum MBSiz_t
    {
        MBSiz_1         = XDMAC_CC_MBSIZE_SINGLE_Val,
        MBSiz_4         = XDMAC_CC_MBSIZE_FOUR_Val,
        MBSiz_8         = XDMAC_CC_MBSIZE_EIGHT_Val,
        MBSiz_16        = XDMAC_CC_MBSIZE_SIXTEEN_Val
    };
    enum DSync_t
    {
        Periph2Mem      = XDMAC_CC_DSYNC_PER2MEM_Val,
        Mem2Periph      = XDMAC_CC_DSYNC_MEM2PER_Val
    };
    enum SWReq_t
    {
        Req_HW          = XDMAC_CC_SWREQ_HWR_CONNECTED_Val,
        Req_SW          = XDMAC_CC_SWREQ_SWR_CONNECTED_Val
    };
    enum ChunkSiz_t
    {
        ChunkSiz_1      = XDMAC_CC_CSIZE_CHK_1_Val,
        ChunkSiz_2      = XDMAC_CC_CSIZE_CHK_2_Val,
        ChunkSiz_4      = XDMAC_CC_CSIZE_CHK_4_Val,
        ChunkSiz_8      = XDMAC_CC_CSIZE_CHK_8_Val,
        ChunkSiz_16     = XDMAC_CC_CSIZE_CHK_16_Val
    };
    enum DWidth_t
    {
        DWidth_Byte     = XDMAC_CC_DWIDTH_BYTE_Val,
        DWidth_HalfWord = XDMAC_CC_DWIDTH_HALFWORD_Val,
        DWidth_Word     = XDMAC_CC_DWIDTH_WORD_Val
    };
    enum AHB_IF_t
    {
        AHB_IF_0        = XDMAC_CC_SIF_AHB_IF0_Val,
        AHB_IF_1        = XDMAC_CC_SIF_AHB_IF1_Val
    };
    enum AddrMode_t
    {
        AddrMode_Fixed  = XDMAC_CC_SAM_FIXED_AM_Val,
        AddrMode_Inc    = XDMAC_CC_SAM_INCREMENTED_AM_Val,
        AddrMode_uBS    = XDMAC_CC_SAM_UBS_AM_Val,
        AddrMode_uBS_DS = XDMAC_CC_SAM_UBS_DS_AM_Val
    };
    // Fetches the status from HW and stores to ctx
    inline uint32_t readyStatus()
    {
        ctx[getID()].stickyISR |= ctx[getID()].lastISR = XDMAC_CIS;
        return ctx[getID()].lastISR;
    }
    // Returns the status as stored in ctx
    inline uint32_t getStatus()     { return ctx[getID()].lastISR;}
    inline uint32_t getStickyStatus()     { return ctx[getID()].stickyISR;}
    inline void     clrStickyStatus(uint32_t mask = 0xFFFFFFFFul)
    {
        ctx[getID()].stickyISR &= ~mask;
    }
    inline uint32_t getID()         { return((XdmacChid *)this) - XDMAC->XDMAC_CHID;}
 
    inline void enableGIrq() { XDMAC->XDMAC_GIE = 1 << getID();}
    inline void disableGIrq() { XDMAC->XDMAC_GID = 1 << getID();}
 
    inline void suspRd()    { XDMAC->XDMAC_GRS |= 1 << getID();}
    inline void suspWr()    { XDMAC->XDMAC_GWS |= 1 << getID();}
    inline void suspRdWr()  { XDMAC->XDMAC_GRWS = 1 << getID();}
    inline void resRd()     { XDMAC->XDMAC_GRS &= ~(1 << getID());}
    inline void resWr()     { XDMAC->XDMAC_GWS &= ~(1 << getID());}
    inline void resRdWr()   { XDMAC->XDMAC_GRWR = 1 << getID();}
    inline void flush()     { XDMAC->XDMAC_GSWF = 1 << getID();}
    inline void disable()   { XDMAC->XDMAC_GD = 1 << getID();}
    inline void enable()    { XDMAC->XDMAC_GE = 1 << getID();}
    inline bool isEnabled() { return(XDMAC->XDMAC_GS) & (1 << getID());}
    inline void suspRdAndFlush()
    {
        /* For some reason the channel cannot flush the transfer FIFO if
         *  it is requesting to fetch the next descriptor and the read
         *  interface is suspended. So, if the channel is suspended *as*
         *  the previous configuration is depleted *and* it is configured to
         *  fetch a new descriptor, we need to renable the read interface,
         *  let the new descriptor be fetched, and *then* we can suspend the
         *  channel for the flush.
         *
         *  No, this isn't documented in the manual. */
        suspRd();
 
        readyStatus();
        flush();
        int i = 0;
        do
        {
            if (i < 25)
            {
                i++;
                asm("dsb");
                continue;
            }
            if ((XDMAC_CNDC & XDMAC_CNDC_NDE)
                && (guBLen() == 0))
            {
                resRd();
                asm("dsb");
                asm("dsb");
 
                while (!(readyStatus() & XDMAC_CIS_FIS))
                {
                }
                suspRd();
                flush();
            }
        } while (!(readyStatus() & XDMAC_CIS_FIS));
    }
 
    inline void sSrcAddr(uint32_t src)  { XDMAC_CSA = src;}
    inline void sDstAddr(uint32_t dst)  { XDMAC_CDA = dst;}
    inline uint32_t gSrcAddr()          { return XDMAC_CSA;}
    inline uint32_t gDstAddr()          { return XDMAC_CDA;}
    inline void suBLen(uint32_t uBLen)  { XDMAC_CUBC = uBLen;}
    inline void s_BLen(uint32_t BLen)   { XDMAC_CBC = BLen;}
    inline uint32_t guBLen()            { return XDMAC_CUBC;}
    dma_transfer_desc_t * getNextDesc(uint32_t *remDataRet);
    inline void *gNextDest()
    {
        dma_transfer_desc_t *desc = getNextDesc(NULL);
        if ((XDMAC_CNDA & XDMAC_CNDA_NDA_Msk) == 0)
        {
            return NULL;
        }
        return(XDMAC_CNDC >> 3)
        ? (void *)(((dma_descview_1 *)XDMAC_CNDA)->dst)
        : (void *)(((dma_descview_0 *)XDMAC_CNDA)->addr);
    }
    inline uint32_t gNextuBLen()
    {
        return((XDMAC_CNDA & XDMAC_CNDA_NDA_Msk) == 0)
        ? 0
        : (((dma_descview_0 *)XDMAC_CNDA)->ubCtrl) & 0xFFFFFF;
    }
    void sNextDescAddr(dma_transfer_desc_t *pDesc);
    inline uint32_t gXfrWidth()
    { return(XDMAC_CC & XDMAC_CC_DWIDTH_Msk) >> (XDMAC_CC_DWIDTH_Pos - 1);}
 
    inline void sConfig(TransType_t type, MBSiz_t mbsiz, DSync_t dir,
                        SWReq_t reqSrc, ChunkSiz_t chunksiz, DWidth_t dataWidth,
                        AHB_IF_t srcIF, AHB_IF_t dstIF, AddrMode_t srcAddrMode,
                        AddrMode_t dstAddrMode, uint8_t periphID)
    {
 
        // The following is a fix for a SAME70 XDMAC errata
        /***** BEGIN ERRATA FIX *****/
        if (dataWidth != DWidth_Word)
        {
            if (srcAddrMode == AddrMode_Fixed)
            {
                srcAddrMode = AddrMode_uBS_DS;
                // set source data stride stride to -1
                XDMAC_CDS_MSP |= (0xFFFF);
                // ERRATA IS WRONG!
                //  We need to set the microstride to -1 as well.
                XDMAC_CSUS = 0xFFFFFF;
            }
            if (dstAddrMode == AddrMode_Fixed)
            {
                dstAddrMode = AddrMode_uBS_DS;
                // set dest data stride stride to -1
                XDMAC_CDS_MSP |= (0xFFFF << 16);
                // ERRATA IS WRONG!
                //  We need to set the microstride to -1 as well.
                XDMAC_CDUS = 0xFFFFFF;
            }
        }
        /***** END ERRATA FIX *****/
        XDMAC_CC = (type << XDMAC_CC_TYPE_Pos) | (mbsiz << XDMAC_CC_MBSIZE_Pos)
                   | (dir << XDMAC_CC_DSYNC_Pos) | (chunksiz << XDMAC_CC_CSIZE_Pos)
                   | (dataWidth << XDMAC_CC_DWIDTH_Pos)
                   | (srcIF << XDMAC_CC_SIF_Pos) | (dstIF << XDMAC_CC_DIF_Pos)
                   | (srcAddrMode << XDMAC_CC_SAM_Pos)
                   | (dstAddrMode << XDMAC_CC_DAM_Pos)
                   | (periphID << XDMAC_CC_PERID_Pos);
    }
 
 
 
    inline void RegisterIsr(void (*isr)(XdmaCh_t *)) { ctx[getID()].isr = isr;}
    // First Descriptor is only used to declare initial loading conditions
 
    friend void XDMAC_Handler();
    friend XdmaCh_t * xdmacGetFreeCh();
    friend void xdmacReleaseCh(XdmaCh_t *xdmaCh);
};
 
XdmaCh_t::AHB_IF_t xdmacGetIntfForAddr(uint32_t addr);
 
inline void XdmaCh_t::sNextDescAddr(dma_transfer_desc_t *pDesc)
{
    XDMAC_CNDA = (((uint32_t)pDesc) & ~0x3)
                 | xdmacGetIntfForAddr((uint32_t)pDesc);
}
 
#define XDMA_BD_INUSE           (0x1)
#define XDMA_BD_SWEEP_MARK      (0x2)
#define XDMA_BD_BUFFER_DONE_Msk (XDMA_BD_SWEEP_MARK | XDMA_BD_INUSE)
#define XDMA_BD_BUFFER_DONE     (XDMA_BD_INUSE)
 
struct Desc0Ring
{
    XdmaCh_t       *xdmaCh;
    dma_descview_0 *descs;
    dma_descview_0 *queueHead;
    dma_descview_0 *modRelease;
    uint32_t       *BDFlag;
    uint32_t        ringLen;
    uint32_t        spinLength;
    uint32_t        spinBuf;
    int             xfrIncSiz;
    uint8_t         ubCtrlBits;
    bool            spinOnLastNotNext;
 
    uint32_t        nConfigFirst;
    uint32_t        nAddXfr;
    uint32_t        nModNext;
    uint32_t        nBDUsed;
    uint32_t        nBDFreed;
 
    int GetFreeDesc(dma_descview_0 *next);
    dma_descview_0 * ModifyNextActive(uint32_t addr, uint32_t unumXfrs, uint32_t suspThresh);
    void ConfigFirstAndEnableCh(uint32_t addr, uint32_t numXfrs);
    dma_descview_0 * AddXfr(uint32_t addr, uint32_t numXfrs, uint32_t suspThresh);
 
    void PrintCounts();
    void PrintDescChain();
};
 
 
 
 
#endif   /* ----- #ifndef __XDMAC_H  ----- */