NetBurner 3.5.7
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usb_host_config.h
1/*
2 * USB Host Stack Configuration for SOMRT1061
3 *
4 * Configures the NXP USB Host stack for Mass Storage Device support
5 */
6
7#ifndef _USB_HOST_CONFIG_H_
8#define _USB_HOST_CONFIG_H_
9
10/*******************************************************************************
11 * Cache / DMA Configuration for Cortex-M7
12 *
13 * The i.MX RT1061 has D-cache enabled. USB DMA requires cache maintenance:
14 * - Clean cache before DMA writes (CPU -> device)
15 * - Invalidate cache after DMA reads (device -> CPU)
16 *
17 * NetBurner's linker doesn't have special NonCacheable/CacheLineData sections,
18 * so we override the NXP section macros to be empty. This keeps USB data in
19 * normal BSS while still enabling cache maintenance functions.
20 ******************************************************************************/
21
22/* Override NXP section macros BEFORE usb_misc.h is included.
23 * This puts USB DMA data in normal BSS instead of special sections.
24 * These must be defined before usb_misc.h because it uses #ifndef guards.
25 */
26#define USB_LINK_DMA_NONINIT_DATA
27#define USB_LINK_NONCACHE_NONINIT_DATA
28#define USB_LINK_DMA_INIT_DATA(sec)
29#define USB_LINK_USB_GLOBAL
30#define USB_LINK_USB_BDT
31#define USB_LINK_USB_GLOBAL_BSS
32#define USB_LINK_USB_BDT_BSS
33
34/* Data section is cacheable (normal RAM with D-cache) */
35#define DATA_SECTION_IS_CACHEABLE (1U)
36
37/* Cache line size for Cortex-M7 (must be defined before usb_misc.h) */
38#define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (32U)
39
40/*******************************************************************************
41 * Host Controller Selection
42 ******************************************************************************/
43
44/* Disable KHCI (Full-Speed controller) */
45#define USB_HOST_CONFIG_KHCI (0U)
46
47/* Enable EHCI (High-Speed controller) - using USB2/OTG2 */
48#define USB_HOST_CONFIG_EHCI (1U)
49
50/* Disable OHCI */
51#define USB_HOST_CONFIG_OHCI (0U)
52
53/* Disable IP3516HS */
54#define USB_HOST_CONFIG_IP3516HS (0U)
55
56/*******************************************************************************
57 * Common Configuration
58 ******************************************************************************/
59
60/* Total number of host controller instances */
61#define USB_HOST_CONFIG_MAX_HOST \
62 (USB_HOST_CONFIG_KHCI + USB_HOST_CONFIG_EHCI + USB_HOST_CONFIG_OHCI + USB_HOST_CONFIG_IP3516HS)
63
64/* Maximum number of pipes (one per endpoint) */
65#define USB_HOST_CONFIG_MAX_PIPES (8U)
66
67/* Maximum number of concurrent transfers */
68#define USB_HOST_CONFIG_MAX_TRANSFERS (8U)
69
70/* Maximum endpoints per interface */
71#define USB_HOST_CONFIG_INTERFACE_MAX_EP (4U)
72
73/* Maximum interfaces per configuration */
74#define USB_HOST_CONFIG_CONFIGURATION_MAX_INTERFACE (5U)
75
76/* Maximum power (mA / 2) the host can provide */
77#define USB_HOST_CONFIG_MAX_POWER (250U)
78
79/* Maximum enumeration retry attempts */
80#define USB_HOST_CONFIG_ENUMERATION_MAX_RETRIES (3U)
81
82/* Maximum stall retries during enumeration */
83#define USB_HOST_CONFIG_ENUMERATION_MAX_STALL_RETRIES (1U)
84
85/* Maximum NAK count before failing a transaction */
86#define USB_HOST_CONFIG_MAX_NAK (3000U)
87
88/* Buffer cache configuration.
89 * Set to 1 to enable cache maintenance (clean/invalidate) around DMA transfers.
90 * This is required because D-cache is enabled and USB DMA operates on RAM directly.
91 * The cache functions are provided by nxp_fsl_cache.h.
92 */
93#define USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE (1U)
94
95/* Note: USB_CACHE_LINESIZE is computed by usb_misc.h from FSL_FEATURE_L1DCACHE_LINESIZE_BYTE */
96
97/* Disable USB compliance testing */
98#define USB_HOST_CONFIG_COMPLIANCE_TEST (0U)
99
100/* Don't auto-clear stalls in class driver */
101#define USB_HOST_CONFIG_CLASS_AUTO_CLEAR_STALL (0U)
102
103/*******************************************************************************
104 * EHCI-Specific Configuration
105 ******************************************************************************/
106
107#if (USB_HOST_CONFIG_EHCI > 0U)
108
109/* Periodic frame list size (must be power of 2: 8, 16, 32, 64, 128, 256, 512, 1024) */
110#define USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE (256U)
111
112/* Maximum Queue Heads */
113#define USB_HOST_CONFIG_EHCI_MAX_QH (8U)
114
115/* Maximum Queue Transfer Descriptors */
116#define USB_HOST_CONFIG_EHCI_MAX_QTD (16U)
117
118/* Maximum Isochronous Transfer Descriptors (not used for MSD) */
119#define USB_HOST_CONFIG_EHCI_MAX_ITD (0U)
120
121/* Maximum Split Isochronous Transfer Descriptors (not used for MSD) */
122#define USB_HOST_CONFIG_EHCI_MAX_SITD (0U)
123
124#endif /* USB_HOST_CONFIG_EHCI */
125
126/*******************************************************************************
127 * Class Driver Configuration
128 ******************************************************************************/
129
130/* Disable HUB class - direct connection only */
131#define USB_HOST_CONFIG_HUB (0U)
132
133/* Disable HID class */
134#define USB_HOST_CONFIG_HID (0U)
135
136/* Enable MSD class */
137#define USB_HOST_CONFIG_MSD (1U)
138
139/* Disable CDC class */
140#define USB_HOST_CONFIG_CDC (0U)
141
142/* Disable Audio class */
143#define USB_HOST_CONFIG_AUDIO (0U)
144
145/* Disable PHDC class */
146#define USB_HOST_CONFIG_PHDC (0U)
147
148/* Disable Printer class */
149#define USB_HOST_CONFIG_PRINTER (0U)
150
151/*******************************************************************************
152 * Platform-Specific Defines for SOMRT1061
153 ******************************************************************************/
154
155/*
156 * USB Controller Selection:
157 * USB1 (OTG1) - kUSB_ControllerEhci0 - Base 0x402E0000 - USBPHY1 - USB_OTG1_IRQn
158 * USB2 (OTG2) - kUSB_ControllerEhci1 - Base 0x402E0200 - USBPHY2 - USB_OTG2_IRQn
159 *
160 * Using USB2 for this project
161 */
162
163/* USB2 controller base addresses */
164#define USB_HOST_EHCI_BASE_ADDRESS (0x402E0200U) /* USB2 register base */
165#define USB_HOST_PHY_BASE_ADDRESS (0x400DA000U) /* USBPHY2 base */
166
167/*
168 * CRITICAL: Override USBHS_BASE_ADDRS to ensure USB2 is included
169 * The NXP USB stack uses this array to get the controller base address.
170 * Index 0 = USB1 (kUSB_ControllerEhci0)
171 * Index 1 = USB2 (kUSB_ControllerEhci1)
172 */
173#ifndef USBHS_BASE_ADDRS
174#define USBHS_BASE_ADDRS { 0x402E0000U, 0x402E0200U }
175#endif
176
177/* Also define the count */
178#ifndef FSL_FEATURE_SOC_USBHS_COUNT
179#define FSL_FEATURE_SOC_USBHS_COUNT (2)
180#endif
181
182
183/* USB2 IRQ number */
184#define USB_HOST_EHCI_IRQ (USB_OTG2_IRQn)
185
186/* USB interrupt priority */
187#if defined(__NVIC_PRIO_BITS) && (__NVIC_PRIO_BITS >= 3)
188#define USB_HOST_INTERRUPT_PRIORITY (6U)
189#else
190#define USB_HOST_INTERRUPT_PRIORITY (3U)
191#endif
192
193/* Controller ID for USB2 (EHCI1) */
194#define USB_HOST_CONTROLLER_ID (kUSB_ControllerEhci1)
195
196/* PHY calibration values (from SOMRT1061 board configuration) */
197#define USB_HOST_PHY_D_CAL (0x0CU)
198#define USB_HOST_PHY_TXCAL45DP (0x06U)
199#define USB_HOST_PHY_TXCAL45DM (0x06U)
200
201/* External crystal frequency */
202#define USB_HOST_XTAL_CLK_HZ (24000000U)
203
204/*******************************************************************************
205 * DMA Buffer Alignment
206 ******************************************************************************/
207
208/* Note: USB_DATA_ALIGN_SIZE, USB_CACHE_LINESIZE, and USB_DMA_NONINIT_DATA_ALIGN
209 * are defined in usb_misc.h based on the cache configuration settings above.
210 * Do not define them here to avoid conflicts.
211 */
212
213#endif /* _USB_HOST_CONFIG_H_ */