usb_MIMXRT.h

/*NB_REVISION*/
 
/*NB_COPYRIGHT*/
 
#ifndef  __USB_MIMXRT_H
#define  __USB_MIMXRT_H
#ifdef SOMRT1061
#include <predef.h>
#include <buffers.h>
#include <usb.h>
#include <sim.h>
 
#define USB_DTD_POOL_SIZE 128
 
void DumpUSBPHY();
void UserMain(void *pd);
namespace nbrtos {
namespace USB {
 
#define dTD_PNEXT_TERMINATE     0x00000001 // Transfer descriptor chain Terminate bit
 
#define dTD_STAT_Halted         0x40  //Checks the Halt status bit in a dQH
#define dTD_STAT_Active         0x80  //Clears the Active Status bit in a dQH
#define dTD_STAT_clrActiveHaltBits   0x3F  //Clears the Active and Halt Status bits in a dQH
#define dTD_BUF_PAGE_SIZE       0x1000
#define dTD_BUF_PAGE_MASK       0xFFFFF000
 
// USB Transfer Descriptor
struct dTD;
typedef dTD * pdTD;
struct dTD {
    union {
        pdTD   pNext;
        uint32_t nextdTDptr;
    };
    union {
        struct {
            uint8_t  flag;
            uint8_t  stat;
            uint16_t totLen;
        };
        uint32_t dTDToken;
    };
    uint32_t bufPtr[5]; // whenever the buffer crosses a 4K page boundary,
                        // buf[n+1] must be set to the next buffer address
                        // regardless of whether the next buffer address
                        // is physically contiguous with the previous one
    union {
        uint8_t  RESERVED[4];
        PoolPtr  pp;
    };
    void Init(uint8_t *buf, uint32_t size, bool irqOnComplete, uint8_t multOverride = 0);
} __attribute__((packed));
 
// USB Endpoint Queue Head
// 48 byte hw struct, needs 64 byte alignment
struct dQH {
    uint8_t  RESERVED0[1];
    uint8_t  irqOnSetup;
    uint16_t flagAndMaxLen;
    union {
        pdTD     pCurr;
        uint32_t currdTDptr;
    };
    union {
        pdTD     pNext;
        uint32_t nextdTDptr;
    };
    union {
        struct {
            uint8_t  flag;
            uint8_t  stat;
            uint16_t totLen;
        };
        uint32_t dTDToken;
    };
    uint32_t bufPtr[5]; // See dTD bufPtr comment
    uint8_t  RESERVED1[4];
    uint8_t  setupBuf[8];
    uint8_t  RESERVED2[16];
 
    void Init(eEndPt_t type, uint8_t isoMult, uint16_t wMaxPacketSize, bool irqOnSetup);
} __attribute__((packed));
 
struct USB_dQ {
    dTD     *pool;
    dTD     *head;
    dTD     *tail;
    OS_SEM   sem;
    uint8_t  poolLen;
    uint8_t  next;
    uint8_t  last;
};
 
struct HW_SetupBuf : public OS_FIFO_EL {
    usb_setup_pkt_t pkt;
    uint8_t hwID;
    uint8_t epnum;
    bool    inUse;
};
 
 
class UDC_MIMXRT : public UDC {
protected:
    volatile USB_Type &usb;
    dQH     *qHeads;
    USB_dQ  dTDs[USB_ENDPTCTRL_COUNT*2];
    HW_SetupBuf setupBuf[USB_ENDPTCTRL_COUNT];
    bool     resetInProgress;
    uint32_t ctlEPs;
    uint32_t epBits;
    uint32_t nIsr;
    uint32_t nIsr_usb;
    uint32_t nIsr_setup[USB_ENDPTCTRL_COUNT];
    uint32_t nIsr_OUT[USB_ENDPTCTRL_COUNT];
    uint32_t nIsr_IN[USB_ENDPTCTRL_COUNT];
    uint32_t nIsr_RST;
    uint32_t nIsr_PortChange;
    uint32_t nIsr_Err;
    uint32_t nIsr_Susp;
 
    void getSetupPkt(uint8_t epnum);
 
    int readOutTransfer(uint8_t epnum, uint8_t *dataBuf, uint16_t maxLen);
 
    void QueueTD(uint8_t epidx, dTD* dtd);
    void QueueTD_Empty(uint8_t epidx, dTD* dtd);
    void PrimeEP(uint8_t epidx);
    void FlushEP(uint8_t epidx);
    void TDCleanup(uint8_t epidx, bool canceled);
    void AbortTransfer(uint8_t epnum, eDir_t dir);
    void busReset();
 
    virtual void StallEP(uint8_t epnum, eDir_t dir);
    void isr_usb();
    void isr();
    void isr_phy(USBPHY_Type &uphy);
    static void usb1_isr();
    static void usb2_isr();
    static void usbphy1_isr();
    static void usbphy2_isr();
    friend void ::DumpUSBPHY();
    friend void ::UserMain(void *pd);
 
    virtual int initInTransfer(uint8_t epnum, uint8_t* data, uint16_t length, bool irqOnComplete, bool dontblock = false);
    virtual int initInTransfer(uint8_t epnum, PoolPtr pp, bool irqOnComplete, bool dontblock = false);
    virtual int initOutTransfer(uint8_t epnum, bool irqOnComplete, bool dontblock = false);
 
    virtual void StallEP(uint8_t devAddr, uint8_t epnum, eDir_t dir);
    virtual void FlushEP(uint8_t devAddr, uint8_t epnum);
public:
    UDC_MIMXRT(USB_Type *hwusb, dQH *qHeads, dTD *tdPool, int poolLen);
    virtual void Init(Device *dev);
 
    virtual int TransmitBuffer(uint8_t devAddr, uint8_t ep, PoolPtr pp);
    virtual int TransmitData(uint8_t devAddr, uint8_t ep, uint8_t *pData, uint16_t length);
 
    virtual int sendControlPkt(uint8_t epnum, uint8_t *buf, uint16_t bufLen);
    virtual int sendControlPkt(uint8_t epnum, PoolPtr pp);
    virtual int SendZLP(uint8_t devAddr, uint8_t epnum);
 
    virtual int InAvail(uint8_t epnum);
    virtual int OutAvail(uint8_t epnum);
 
    virtual int RegisterEP(uint8_t devAddr, uint8_t epnum, eDir_t dir, eEndPt_t type,
                            uint16_t maxPktSize, endPtCB_t fnCB);
    virtual int SetDevAddr(uint8_t devAddr, Device *dev);
    virtual int ReleaseEP(uint8_t devAddr, uint8_t epnum, eDir_t dir);
};
 
// USB Host Controller
class UHC_MIMXRT : public UHC {
    volatile USB_Type &usb;
 
public:
    UHC_MIMXRT(USB_Type *usb);
    virtual void Init();
    int SendToDevice(uint8_t devAddr, uint8_t endpt, void *buf, int datLen);
};
 
class UOTGC_MIMXRT : public UOTGC {
    volatile USB_Type &usb;
 
public:
    UOTGC_MIMXRT(USB_Type *usb);
    virtual void Init();
};
 
}
}
#endif
#endif   /* ----- #ifndef __USB_MIMXRT_H  ----- */