Developer/html/tpiu_8h_source.html

#define TPIU_STMR_MULT2_Pos 0U

#define TPIU_STMR_MULT2_Msk (0x1UL << TPIU_STMR_MULT2_Pos)

#define TPIU_STMR_MULT2(_mrval) ((_mrval << TPIU_STMR_MULT2_Pos) & TPIU_STMR_MULT2_Msk)

#define TPIU_STMR_MULT2_NOT_SUPPORTED (0x0UL << TPIU_STMR_MULT2_Pos)

#define TPIU_STMR_MULT2_IS_SUPPORTED (0x1UL << TPIU_STMR_MULT2_Pos)


#define TPIU_STMR_MULT4_Pos 1U

#define TPIU_STMR_MULT4_Msk (0x1UL << TPIU_STMR_MULT4_Pos)

#define TPIU_STMR_MULT4(_mrval) ((_mrval << TPIU_STMR_MULT4_Pos) & TPIU_STMR_MULT4_Msk)

#define TPIU_STMR_MULT4_NOT_SUPPORTED (0x0UL << TPIU_STMR_MULT4_Pos)

#define TPIU_STMR_MULT4_IS_SUPPORTED (0x1UL << TPIU_STMR_MULT4_Pos)


#define TPIU_STMR_MULT16_Pos 2U

#define TPIU_STMR_MULT16_Msk (0x1UL << TPIU_STMR_MULT16_Pos)

#define TPIU_STMR_MULT16(_mrval) ((_mrval << TPIU_STMR_MULT16_Pos) & TPIU_STMR_MULT16_Msk)

#define TPIU_STMR_MULT16_NOT_SUPPORTED (0x0UL << TPIU_STMR_MULT16_Pos)

#define TPIU_STMR_MULT16_IS_SUPPORTED (0x1UL << TPIU_STMR_MULT16_Pos)


#define TPIU_STMR_MULT256_Pos 3U

#define TPIU_STMR_MULT256_Msk (0x1UL << TPIU_STMR_MULT256_Pos)

#define TPIU_STMR_MULT256(_mrval) ((_mrval << TPIU_STMR_MULT256_Pos) & TPIU_STMR_MULT256_Msk)

#define TPIU_STMR_MULT256_NOT_SUPPORTED (0x0UL << TPIU_STMR_MULT256_Pos)

#define TPIU_STMR_MULT256_IS_SUPPORTED (0x1UL << TPIU_STMR_MULT256_Pos)


#define TPIU_STMR_MULT64K_Pos 4U

#define TPIU_STMR_MULT64K_Msk (0x1UL << TPIU_STMR_MULT64K_Pos)

#define TPIU_STMR_MULT64K(_mrval) ((_mrval << TPIU_STMR_MULT64K_Pos) & TPIU_STMR_MULT64K_Msk)

#define TPIU_STMR_MULT64K_NOT_SUPPORTED (0x0UL << TPIU_STMR_MULT64K_Pos)

#define TPIU_STMR_MULT64K_IS_SUPPORTED (0x1UL << TPIU_STMR_MULT64K_Pos)


#define TPIU_STMR_TCOUNT8_Pos 8U

#define TPIU_STMR_TCOUNT8_Msk (0x1UL << TPIU_STMR_TCOUNT8_Pos)

#define TPIU_STMR_TCOUNT8(_mrval) ((_mrval << TPIU_STMR_TCOUNT8_Pos) & TPIU_STMR_TCOUNT8_Msk)

#define TPIU_STMR_TCOUNT8_NOT_SUPPORTED (0x0UL << TPIU_STMR_TCOUNT8_Pos)

#define TPIU_STMR_TCOUNT8_IS_SUPPORTED (0x1UL << TPIU_STMR_TCOUNT8_Pos)


#define TPIU_STMR_TRIGGERED_Pos 16U

#define TPIU_STMR_TRIGGERED_Msk (0x1UL << TPIU_STMR_TRIGGERED_Pos)

#define TPIU_STMR_TRIGGERED(_mrval) ((_mrval << TPIU_STMR_TRIGGERED_Pos) & TPIU_STMR_TRIGGERED_Msk)

#define TPIU_STMR_TRIGGERED_NOT_OCCURRED (0x0UL << TPIU_STMR_TRIGGERED_Pos)

#define TPIU_STMR_TRIGGERED_HAS_OCCURRED (0x1UL << TPIU_STMR_TRIGGERED_Pos)


#define TPIU_STMR_TrgRun_Pos 17U

#define TPIU_STMR_TrgRun_Msk (0x1UL << TPIU_STMR_TrgRun_Pos)

#define TPIU_STMR_TrgRun(_mrval) ((_mrval << TPIU_STMR_TrgRun_Pos) & TPIU_STMR_TrgRun_Msk)

#define TPIU_STMR_TrgRun_NO (0x0UL << TPIU_STMR_TrgRun_Pos)

#define TPIU_STMR_TrgRun_WHILE_RUNNING (0x1UL << TPIU_STMR_TrgRun_Pos)


#define TPIU_TRCVR_TrigCount_Pos 0U

#define TPIU_TRCVR_TrigCount_Msk (0xffUL << TPIU_TRCVR_TrigCount_Pos)

#define TPIU_TRCVR_TrigCount(_mrval) ((_mrval << TPIU_TRCVR_TrigCount_Pos) & TPIU_TRCVR_TrigCount_Msk)


#define TPIU_TRMR_MULT2_Pos 0U

#define TPIU_TRMR_MULT2_Msk (0x1UL << TPIU_TRMR_MULT2_Pos)

#define TPIU_TRMR_MULT2(_mrval) ((_mrval << TPIU_TRMR_MULT2_Pos) & TPIU_TRMR_MULT2_Msk)

#define TPIU_TRMR_MULT2_DISABLED (0x0UL << TPIU_TRMR_MULT2_Pos)

#define TPIU_TRMR_MULT2_ENABLED (0x1UL << TPIU_TRMR_MULT2_Pos)


#define TPIU_TRMR_MULT4_Pos 1U

#define TPIU_TRMR_MULT4_Msk (0x1UL << TPIU_TRMR_MULT4_Pos)

#define TPIU_TRMR_MULT4(_mrval) ((_mrval << TPIU_TRMR_MULT4_Pos) & TPIU_TRMR_MULT4_Msk)

#define TPIU_TRMR_MULT4_DISABLED (0x0UL << TPIU_TRMR_MULT4_Pos)

#define TPIU_TRMR_MULT4_ENABLED (0x1UL << TPIU_TRMR_MULT4_Pos)


#define TPIU_TRMR_MULT16_Pos 2U

#define TPIU_TRMR_MULT16_Msk (0x1UL << TPIU_TRMR_MULT16_Pos)

#define TPIU_TRMR_MULT16(_mrval) ((_mrval << TPIU_TRMR_MULT16_Pos) & TPIU_TRMR_MULT16_Msk)

#define TPIU_TRMR_MULT16_DISABLED (0x0UL << TPIU_TRMR_MULT16_Pos)

#define TPIU_TRMR_MULT16_ENABLED (0x1UL << TPIU_TRMR_MULT16_Pos)


#define TPIU_TRMR_MULT256_Pos 3U

#define TPIU_TRMR_MULT256_Msk (0x1UL << TPIU_TRMR_MULT256_Pos)

#define TPIU_TRMR_MULT256(_mrval) ((_mrval << TPIU_TRMR_MULT256_Pos) & TPIU_TRMR_MULT256_Msk)

#define TPIU_TRMR_MULT256_DISABLED (0x0UL << TPIU_TRMR_MULT256_Pos)

#define TPIU_TRMR_MULT256_ENABLED (0x1UL << TPIU_TRMR_MULT256_Pos)


#define TPIU_TRMR_MULT64K_Pos 4U

#define TPIU_TRMR_MULT64K_Msk (0x1UL << TPIU_TRMR_MULT64K_Pos)

#define TPIU_TRMR_MULT64K(_mrval) ((_mrval << TPIU_TRMR_MULT64K_Pos) & TPIU_TRMR_MULT64K_Msk)

#define TPIU_TRMR_MULT64K_DISABLED (0x0UL << TPIU_TRMR_MULT64K_Pos)

#define TPIU_TRMR_MULT64K_ENABLED (0x1UL << TPIU_TRMR_MULT64K_Pos)


#define TPIU_STPMR_PATW1_Pos 0U

#define TPIU_STPMR_PATW1_Msk (0x1UL << TPIU_STPMR_PATW1_Pos)

#define TPIU_STPMR_PATW1(_mrval) ((_mrval << TPIU_STPMR_PATW1_Pos) & TPIU_STPMR_PATW1_Msk)

#define TPIU_STPMR_PATW1_NOT_SUPPORTED (0x0UL << TPIU_STPMR_PATW1_Pos)

#define TPIU_STPMR_PATW1_IS_SUPPORTED (0x1UL << TPIU_STPMR_PATW1_Pos)


#define TPIU_STPMR_PATW0_Pos 1U

#define TPIU_STPMR_PATW0_Msk (0x1UL << TPIU_STPMR_PATW0_Pos)

#define TPIU_STPMR_PATW0(_mrval) ((_mrval << TPIU_STPMR_PATW0_Pos) & TPIU_STPMR_PATW0_Msk)

#define TPIU_STPMR_PATW0_NOT_SUPPORTED (0x0UL << TPIU_STPMR_PATW0_Pos)

#define TPIU_STPMR_PATW0_IS_SUPPORTED (0x1UL << TPIU_STPMR_PATW0_Pos)


#define TPIU_STPMR_PATA5_Pos 2U

#define TPIU_STPMR_PATA5_Msk (0x1UL << TPIU_STPMR_PATA5_Pos)

#define TPIU_STPMR_PATA5(_mrval) ((_mrval << TPIU_STPMR_PATA5_Pos) & TPIU_STPMR_PATA5_Msk)

#define TPIU_STPMR_PATA5_NOT_SUPPORTED (0x0UL << TPIU_STPMR_PATA5_Pos)

#define TPIU_STPMR_PATA5_IS_SUPPORTED (0x1UL << TPIU_STPMR_PATA5_Pos)


#define TPIU_STPMR_PATF0_Pos 3U

#define TPIU_STPMR_PATF0_Msk (0x1UL << TPIU_STPMR_PATF0_Pos)

#define TPIU_STPMR_PATF0(_mrval) ((_mrval << TPIU_STPMR_PATF0_Pos) & TPIU_STPMR_PATF0_Msk)

#define TPIU_STPMR_PATF0_NOT_SUPPORTED (0x0UL << TPIU_STPMR_PATF0_Pos)

#define TPIU_STPMR_PATF0_IS_SUPPORTED (0x1UL << TPIU_STPMR_PATF0_Pos)


#define TPIU_STPMR_PTIMEN_Pos 16U

#define TPIU_STPMR_PTIMEN_Msk (0x1UL << TPIU_STPMR_PTIMEN_Pos)

#define TPIU_STPMR_PTIMEN(_mrval) ((_mrval << TPIU_STPMR_PTIMEN_Pos) & TPIU_STPMR_PTIMEN_Msk)

#define TPIU_STPMR_PTIMEN_NOT_SUPPORTED (0x0UL << TPIU_STPMR_PTIMEN_Pos)

#define TPIU_STPMR_PTIMEN_IS_SUPPORTED (0x1UL << TPIU_STPMR_PTIMEN_Pos)


#define TPIU_STPMR_PCONTEN_Pos 17U

#define TPIU_STPMR_PCONTEN_Msk (0x1UL << TPIU_STPMR_PCONTEN_Pos)

#define TPIU_STPMR_PCONTEN(_mrval) ((_mrval << TPIU_STPMR_PCONTEN_Pos) & TPIU_STPMR_PCONTEN_Msk)

#define TPIU_STPMR_PCONTEN_NOT_SUPPORTED (0x0UL << TPIU_STPMR_PCONTEN_Pos)

#define TPIU_STPMR_PCONTEN_IS_SUPPORTED (0x1UL << TPIU_STPMR_PCONTEN_Pos)


#define TPIU_CTPMR_PATW1_Pos 0U

#define TPIU_CTPMR_PATW1_Msk (0x1UL << TPIU_CTPMR_PATW1_Pos)

#define TPIU_CTPMR_PATW1(_mrval) ((_mrval << TPIU_CTPMR_PATW1_Pos) & TPIU_CTPMR_PATW1_Msk)

#define TPIU_CTPMR_PATW1_DISABLED (0x0UL << TPIU_CTPMR_PATW1_Pos)

#define TPIU_CTPMR_PATW1_ENABLED (0x1UL << TPIU_CTPMR_PATW1_Pos)


#define TPIU_CTPMR_PATW0_Pos 1U

#define TPIU_CTPMR_PATW0_Msk (0x1UL << TPIU_CTPMR_PATW0_Pos)

#define TPIU_CTPMR_PATW0(_mrval) ((_mrval << TPIU_CTPMR_PATW0_Pos) & TPIU_CTPMR_PATW0_Msk)

#define TPIU_CTPMR_PATW0_DISABLED (0x0UL << TPIU_CTPMR_PATW0_Pos)

#define TPIU_CTPMR_PATW0_ENABLED (0x1UL << TPIU_CTPMR_PATW0_Pos)


#define TPIU_CTPMR_PATA5_Pos 2U

#define TPIU_CTPMR_PATA5_Msk (0x1UL << TPIU_CTPMR_PATA5_Pos)

#define TPIU_CTPMR_PATA5(_mrval) ((_mrval << TPIU_CTPMR_PATA5_Pos) & TPIU_CTPMR_PATA5_Msk)

#define TPIU_CTPMR_PATA5_DISABLED (0x0UL << TPIU_CTPMR_PATA5_Pos)

#define TPIU_CTPMR_PATA5_ENABLED (0x1UL << TPIU_CTPMR_PATA5_Pos)


#define TPIU_CTPMR_PATF0_Pos 3U

#define TPIU_CTPMR_PATF0_Msk (0x1UL << TPIU_CTPMR_PATF0_Pos)

#define TPIU_CTPMR_PATF0(_mrval) ((_mrval << TPIU_CTPMR_PATF0_Pos) & TPIU_CTPMR_PATF0_Msk)

#define TPIU_CTPMR_PATF0_DISABLED (0x0UL << TPIU_CTPMR_PATF0_Pos)

#define TPIU_CTPMR_PATF0_ENABLED (0x1UL << TPIU_CTPMR_PATF0_Pos)


#define TPIU_CTPMR_PTIMEN_Pos 16U

#define TPIU_CTPMR_PTIMEN_Msk (0x1UL << TPIU_CTPMR_PTIMEN_Pos)

#define TPIU_CTPMR_PTIMEN(_mrval) ((_mrval << TPIU_CTPMR_PTIMEN_Pos) & TPIU_CTPMR_PTIMEN_Msk)

#define TPIU_CTPMR_PTIMEN_DISABLED (0x0UL << TPIU_CTPMR_PTIMEN_Pos)

#define TPIU_CTPMR_PTIMEN_ENABLED (0x1UL << TPIU_CTPMR_PTIMEN_Pos)


#define TPIU_CTPMR_PCONTEN_Pos 17U

#define TPIU_CTPMR_PCONTEN_Msk (0x1UL << TPIU_CTPMR_PCONTEN_Pos)

#define TPIU_CTPMR_PCONTEN(_mrval) ((_mrval << TPIU_CTPMR_PCONTEN_Pos) & TPIU_CTPMR_PCONTEN_Msk)

#define TPIU_CTPMR_PCONTEN_DISABLED (0x0UL << TPIU_CTPMR_PCONTEN_Pos)

#define TPIU_CTPMR_PCONTEN_ENABLED (0x1UL << TPIU_CTPMR_PCONTEN_Pos)


#define TPIU_TPRCR_PATTCOUNT_Pos 0U

#define TPIU_TPRCR_PATTCOUNT_Msk (0xffUL << TPIU_TPRCR_PATTCOUNT_Pos)

#define TPIU_TPRCR_PATTCOUNT(_mrval) ((_mrval << TPIU_TPRCR_PATTCOUNT_Pos) & TPIU_TPRCR_PATTCOUNT_Msk)


#define TPIU_FFSR_FlInProg_Pos 0U

#define TPIU_FFSR_FlInProg_Msk (0x1UL << TPIU_FFSR_FlInProg_Pos)

#define TPIU_FFSR_FlInProg(_mrval) ((_mrval << TPIU_FFSR_FlInProg_Pos) & TPIU_FFSR_FlInProg_Msk)

#define TPIU_FFSR_FlInProg_NOT_FLUSHING (0x0UL << TPIU_FFSR_FlInProg_Pos)

#define TPIU_FFSR_FlInProg_FLUSH_IN_PROGRESS (0x1UL << TPIU_FFSR_FlInProg_Pos)


#define TPIU_FFSR_FtStopped_Pos 1U

#define TPIU_FFSR_FtStopped_Msk (0x1UL << TPIU_FFSR_FtStopped_Pos)

#define TPIU_FFSR_FtStopped(_mrval) ((_mrval << TPIU_FFSR_FtStopped_Pos) & TPIU_FFSR_FtStopped_Msk)

#define TPIU_FFSR_FtStopped_NOT_STOPPED (0x0UL << TPIU_FFSR_FtStopped_Pos)

#define TPIU_FFSR_FtStopped_IS_STOPPED (0x1UL << TPIU_FFSR_FtStopped_Pos)


#define TPIU_FFSR_TCPresent_Pos 2U

#define TPIU_FFSR_TCPresent_Msk (0x1UL << TPIU_FFSR_TCPresent_Pos)

#define TPIU_FFSR_TCPresent(_mrval) ((_mrval << TPIU_FFSR_TCPresent_Pos) & TPIU_FFSR_TCPresent_Msk)

#define TPIU_FFSR_TCPresent_NOT_PRESENT (0x0UL << TPIU_FFSR_TCPresent_Pos)

#define TPIU_FFSR_TCPresent_IS_PRESENT (0x1UL << TPIU_FFSR_TCPresent_Pos)


#define TPIU_FFCR_EnFTC_Pos 0U

#define TPIU_FFCR_EnFTC_Msk (0x1UL << TPIU_FFCR_EnFTC_Pos)

#define TPIU_FFCR_EnFTC(_mrval) ((_mrval << TPIU_FFCR_EnFTC_Pos) & TPIU_FFCR_EnFTC_Msk)

#define TPIU_FFCR_EnFTC_DISABLED (0x0UL << TPIU_FFCR_EnFTC_Pos)

#define TPIU_FFCR_EnFTC_ENABLED (0x1UL << TPIU_FFCR_EnFTC_Pos)


#define TPIU_FFCR_EnFCont_Pos 1U

#define TPIU_FFCR_EnFCont_Msk (0x1UL << TPIU_FFCR_EnFCont_Pos)

#define TPIU_FFCR_EnFCont(_mrval) ((_mrval << TPIU_FFCR_EnFCont_Pos) & TPIU_FFCR_EnFCont_Msk)

#define TPIU_FFCR_EnFCont_DISABLED (0x0UL << TPIU_FFCR_EnFCont_Pos)

#define TPIU_FFCR_EnFCont_ENABLED (0x1UL << TPIU_FFCR_EnFCont_Pos)


#define TPIU_FFCR_FOnFlIn_Pos 4U

#define TPIU_FFCR_FOnFlIn_Msk (0x1UL << TPIU_FFCR_FOnFlIn_Pos)

#define TPIU_FFCR_FOnFlIn(_mrval) ((_mrval << TPIU_FFCR_FOnFlIn_Pos) & TPIU_FFCR_FOnFlIn_Msk)

#define TPIU_FFCR_FOnFlIn_DISABLED (0x0UL << TPIU_FFCR_FOnFlIn_Pos)

#define TPIU_FFCR_FOnFlIn_ENABLED (0x1UL << TPIU_FFCR_FOnFlIn_Pos)


#define TPIU_FFCR_FOnTrig_Pos 5U

#define TPIU_FFCR_FOnTrig_Msk (0x1UL << TPIU_FFCR_FOnTrig_Pos)

#define TPIU_FFCR_FOnTrig(_mrval) ((_mrval << TPIU_FFCR_FOnTrig_Pos) & TPIU_FFCR_FOnTrig_Msk)

#define TPIU_FFCR_FOnTrig_DISABLED (0x0UL << TPIU_FFCR_FOnTrig_Pos)

#define TPIU_FFCR_FOnTrig_ENABLED (0x1UL << TPIU_FFCR_FOnTrig_Pos)


#define TPIU_FFCR_FOnMan_Pos 6U

#define TPIU_FFCR_FOnMan_Msk (0x1UL << TPIU_FFCR_FOnMan_Pos)

#define TPIU_FFCR_FOnMan(_mrval) ((_mrval << TPIU_FFCR_FOnMan_Pos) & TPIU_FFCR_FOnMan_Msk)

#define TPIU_FFCR_FOnMan_DISABLED (0x0UL << TPIU_FFCR_FOnMan_Pos)

#define TPIU_FFCR_FOnMan_ENABLED (0x1UL << TPIU_FFCR_FOnMan_Pos)


#define TPIU_FFCR_TrigIn_Pos 8U

#define TPIU_FFCR_TrigIn_Msk (0x1UL << TPIU_FFCR_TrigIn_Pos)

#define TPIU_FFCR_TrigIn(_mrval) ((_mrval << TPIU_FFCR_TrigIn_Pos) & TPIU_FFCR_TrigIn_Msk)

#define TPIU_FFCR_TrigIn_DISABLED (0x0UL << TPIU_FFCR_TrigIn_Pos)

#define TPIU_FFCR_TrigIn_ENABLED (0x1UL << TPIU_FFCR_TrigIn_Pos)


#define TPIU_FFCR_TrigEvt_Pos 9U

#define TPIU_FFCR_TrigEvt_Msk (0x1UL << TPIU_FFCR_TrigEvt_Pos)

#define TPIU_FFCR_TrigEvt(_mrval) ((_mrval << TPIU_FFCR_TrigEvt_Pos) & TPIU_FFCR_TrigEvt_Msk)

#define TPIU_FFCR_TrigEvt_DISABLED (0x0UL << TPIU_FFCR_TrigEvt_Pos)

#define TPIU_FFCR_TrigEvt_ENABLED (0x1UL << TPIU_FFCR_TrigEvt_Pos)


#define TPIU_FFCR_TrigFl_Pos 10U

#define TPIU_FFCR_TrigFl_Msk (0x1UL << TPIU_FFCR_TrigFl_Pos)

#define TPIU_FFCR_TrigFl(_mrval) ((_mrval << TPIU_FFCR_TrigFl_Pos) & TPIU_FFCR_TrigFl_Msk)

#define TPIU_FFCR_TrigFl_DISABLED (0x0UL << TPIU_FFCR_TrigFl_Pos)

#define TPIU_FFCR_TrigFl_ENABLED (0x1UL << TPIU_FFCR_TrigFl_Pos)


#define TPIU_FFCR_StopFl_Pos 12U

#define TPIU_FFCR_StopFl_Msk (0x1UL << TPIU_FFCR_StopFl_Pos)

#define TPIU_FFCR_StopFl(_mrval) ((_mrval << TPIU_FFCR_StopFl_Pos) & TPIU_FFCR_StopFl_Msk)

#define TPIU_FFCR_StopFl_DISABLED (0x0UL << TPIU_FFCR_StopFl_Pos)

#define TPIU_FFCR_StopFl_ENABLED (0x1UL << TPIU_FFCR_StopFl_Pos)


#define TPIU_FFCR_StopTrig_Pos 13U

#define TPIU_FFCR_StopTrig_Msk (0x1UL << TPIU_FFCR_StopTrig_Pos)

#define TPIU_FFCR_StopTrig(_mrval) ((_mrval << TPIU_FFCR_StopTrig_Pos) & TPIU_FFCR_StopTrig_Msk)

#define TPIU_FFCR_StopTrig_DISABLED (0x0UL << TPIU_FFCR_StopTrig_Pos)

#define TPIU_FFCR_StopTrig_ENABLED (0x1UL << TPIU_FFCR_StopTrig_Pos)


#define TPIU_FSCR_CycCount_Pos 0U

#define TPIU_FSCR_CycCount_Msk (0xfffUL << TPIU_FSCR_CycCount_Pos)

#define TPIU_FSCR_CycCount(_mrval) ((_mrval << TPIU_FSCR_CycCount_Pos) & TPIU_FSCR_CycCount_Msk)


#define TPIU_EXTCTL_In_Port_EXTCTLIN_Pos 0U

#define TPIU_EXTCTL_In_Port_EXTCTLIN_Msk (0xffUL << TPIU_EXTCTL_In_Port_EXTCTLIN_Pos)

#define TPIU_EXTCTL_In_Port_EXTCTLIN(_mrval) ((_mrval << TPIU_EXTCTL_In_Port_EXTCTLIN_Pos) & TPIU_EXTCTL_In_Port_EXTCTLIN_Msk)


#define TPIU_EXTCTL_Out_Port_EXTCTLOUT_Pos 0U

#define TPIU_EXTCTL_Out_Port_EXTCTLOUT_Msk (0xffUL << TPIU_EXTCTL_Out_Port_EXTCTLOUT_Pos)

#define TPIU_EXTCTL_Out_Port_EXTCTLOUT(_mrval) ((_mrval << TPIU_EXTCTL_Out_Port_EXTCTLOUT_Pos) & TPIU_EXTCTL_Out_Port_EXTCTLOUT_Msk)


#define TPIU_CLAIMSET_SET_Pos 0U

#define TPIU_CLAIMSET_SET_Msk (0xfUL << TPIU_CLAIMSET_SET_Pos)

#define TPIU_CLAIMSET_SET(_mrval) ((_mrval << TPIU_CLAIMSET_SET_Pos) & TPIU_CLAIMSET_SET_Msk)


#define TPIU_CLAIMCLR_CLR_Pos 0U

#define TPIU_CLAIMCLR_CLR_Msk (0xfUL << TPIU_CLAIMCLR_CLR_Pos)

#define TPIU_CLAIMCLR_CLR(_mrval) ((_mrval << TPIU_CLAIMCLR_CLR_Pos) & TPIU_CLAIMCLR_CLR_Msk)


#define TPIU_LAR_KEY_Pos 0U

#define TPIU_LAR_KEY_Msk (0xffffffffUL << TPIU_LAR_KEY_Pos)

#define TPIU_LAR_KEY(_mrval) ((_mrval << TPIU_LAR_KEY_Pos) & TPIU_LAR_KEY_Msk)

#define TPIU_LAR_KEY_UNLOCK (0xc5acce55UL << TPIU_LAR_KEY_Pos)


#define TPIU_LSR_SLI_Pos 0U

#define TPIU_LSR_SLI_Msk (0x1UL << TPIU_LSR_SLI_Pos)

#define TPIU_LSR_SLI(_mrval) ((_mrval << TPIU_LSR_SLI_Pos) & TPIU_LSR_SLI_Msk)

#define TPIU_LSR_SLI_NOT_PRESENT (0x0UL << TPIU_LSR_SLI_Pos)

#define TPIU_LSR_SLI_IS_PRESENT (0x1UL << TPIU_LSR_SLI_Pos)


#define TPIU_LSR_SLK_Pos 1U

#define TPIU_LSR_SLK_Msk (0x1UL << TPIU_LSR_SLK_Pos)

#define TPIU_LSR_SLK(_mrval) ((_mrval << TPIU_LSR_SLK_Pos) & TPIU_LSR_SLK_Msk)

#define TPIU_LSR_SLK_IS_CLEAR (0x0UL << TPIU_LSR_SLK_Pos)

#define TPIU_LSR_SLK_IS_SET (0x1UL << TPIU_LSR_SLK_Pos)


#define TPIU_LSR_NTT_Pos 2U

#define TPIU_LSR_NTT_Msk (0x1UL << TPIU_LSR_NTT_Pos)

#define TPIU_LSR_NTT(_mrval) ((_mrval << TPIU_LSR_NTT_Pos) & TPIU_LSR_NTT_Msk)


#define TPIU_AUTHSTATUS_NSID_Pos 0U

#define TPIU_AUTHSTATUS_NSID_Msk (0x3UL << TPIU_AUTHSTATUS_NSID_Pos)

#define TPIU_AUTHSTATUS_NSID(_mrval) ((_mrval << TPIU_AUTHSTATUS_NSID_Pos) & TPIU_AUTHSTATUS_NSID_Msk)


#define TPIU_AUTHSTATUS_NSNID_Pos 2U

#define TPIU_AUTHSTATUS_NSNID_Msk (0x3UL << TPIU_AUTHSTATUS_NSNID_Pos)

#define TPIU_AUTHSTATUS_NSNID(_mrval) ((_mrval << TPIU_AUTHSTATUS_NSNID_Pos) & TPIU_AUTHSTATUS_NSNID_Msk)


#define TPIU_AUTHSTATUS_SID_Pos 4U

#define TPIU_AUTHSTATUS_SID_Msk (0x3UL << TPIU_AUTHSTATUS_SID_Pos)

#define TPIU_AUTHSTATUS_SID(_mrval) ((_mrval << TPIU_AUTHSTATUS_SID_Pos) & TPIU_AUTHSTATUS_SID_Msk)


#define TPIU_AUTHSTATUS_SNID_Pos 6U

#define TPIU_AUTHSTATUS_SNID_Msk (0x3UL << TPIU_AUTHSTATUS_SNID_Pos)

#define TPIU_AUTHSTATUS_SNID(_mrval) ((_mrval << TPIU_AUTHSTATUS_SNID_Pos) & TPIU_AUTHSTATUS_SNID_Msk)


#define TPIU_DEVID_MAXNUM_Pos 0U

#define TPIU_DEVID_MAXNUM_Msk (0xfUL << TPIU_DEVID_MAXNUM_Pos)

#define TPIU_DEVID_MAXNUM(_mrval) ((_mrval << TPIU_DEVID_MAXNUM_Pos) & TPIU_DEVID_MAXNUM_Msk)


#define TPIU_DEVID_CLKRELAT_Pos 5U

#define TPIU_DEVID_CLKRELAT_Msk (0x1UL << TPIU_DEVID_CLKRELAT_Pos)

#define TPIU_DEVID_CLKRELAT(_mrval) ((_mrval << TPIU_DEVID_CLKRELAT_Pos) & TPIU_DEVID_CLKRELAT_Msk)


#define TPIU_DEVID_FIFOSIZE_Pos 6U

#define TPIU_DEVID_FIFOSIZE_Msk (0x7UL << TPIU_DEVID_FIFOSIZE_Pos)

#define TPIU_DEVID_FIFOSIZE(_mrval) ((_mrval << TPIU_DEVID_FIFOSIZE_Pos) & TPIU_DEVID_FIFOSIZE_Msk)


#define TPIU_DEVID_TCLKDATA_Pos 9U

#define TPIU_DEVID_TCLKDATA_Msk (0x1UL << TPIU_DEVID_TCLKDATA_Pos)

#define TPIU_DEVID_TCLKDATA(_mrval) ((_mrval << TPIU_DEVID_TCLKDATA_Pos) & TPIU_DEVID_TCLKDATA_Msk)


#define TPIU_DEVID_SWOMAN_Pos 10U

#define TPIU_DEVID_SWOMAN_Msk (0x1UL << TPIU_DEVID_SWOMAN_Pos)

#define TPIU_DEVID_SWOMAN(_mrval) ((_mrval << TPIU_DEVID_SWOMAN_Pos) & TPIU_DEVID_SWOMAN_Msk)


#define TPIU_DEVID_SWOUARTNRZ_Pos 11U

#define TPIU_DEVID_SWOUARTNRZ_Msk (0x1UL << TPIU_DEVID_SWOUARTNRZ_Pos)

#define TPIU_DEVID_SWOUARTNRZ(_mrval) ((_mrval << TPIU_DEVID_SWOUARTNRZ_Pos) & TPIU_DEVID_SWOUARTNRZ_Msk)


#define TPIU_DEVTYPE_MAJOR_Pos 0U

#define TPIU_DEVTYPE_MAJOR_Msk (0xfUL << TPIU_DEVTYPE_MAJOR_Pos)

#define TPIU_DEVTYPE_MAJOR(_mrval) ((_mrval << TPIU_DEVTYPE_MAJOR_Pos) & TPIU_DEVTYPE_MAJOR_Msk)

#define TPIU_DEVTYPE_MAJOR_TRACE_SINK (0x1UL << TPIU_DEVTYPE_MAJOR_Pos)


#define TPIU_DEVTYPE_SUB_Pos 4U

#define TPIU_DEVTYPE_SUB_Msk (0xfUL << TPIU_DEVTYPE_SUB_Pos)

#define TPIU_DEVTYPE_SUB(_mrval) ((_mrval << TPIU_DEVTYPE_SUB_Pos) & TPIU_DEVTYPE_SUB_Msk)

#define TPIU_DEVTYPE_SUB_TRACE_PORT (0x1UL << TPIU_DEVTYPE_SUB_Pos)