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sim5441x.h
1/*NB_REVISION*/
2
3/*NB_COPYRIGHT*/
4
5#ifndef _SIM54418_H_
6#define _SIM54418_H_
7
8/* #define ENHANCED_ETHER_BD */ // Enable enhanced buffer descriptors
9
10typedef volatile unsigned char vubyte;
11typedef volatile unsigned short vuword;
12typedef volatile unsigned long vudword;
13
14/*
15 * RAPID GPIO
16 */
17typedef struct
18{
19 vuword dir0; /* 0x8C00_0000 -> 0x8C00_0001 - (Read) Data Direction Register
20 (Write) Data Direction Register */
21 vuword data; /* 0x8C00_0002 -> 0x8C00_0003 - (Read) Write Data Register
22 (Write) Write Data Register */
23 vuword enb; /* 0x8C00_0004 -> 0x8C00_0005 - (Read) Pin Enable Register
24 (Write) Pin Enable Register */
25 vuword clr; /* 0x8C00_0006 -> 0x8C00_0007 - (Read) Write Data Register
26 (Write) Write Data Clear Register */
27 vuword dir1; /* 0x8C00_0008 -> 0x8C00_0009 - (Read) Data Direction Register */
28 vuword set; /* 0x8C00_000A -> 0x8C00_000B - (Read) Write Data Register
29 (Write) Write Data Set Register */
30 vuword dir2; /* 0x8C00_000C -> 0x8C00_000D - (Read) Data Direction Register */
31 vuword tog; /* 0x8C00_000E -> 0x8C00_000F - (Read) Write Data Register
32 (Write) Write Data Toggle Register */
33} rgpiostruct;
34
35/*
36 * 1-WIRE MODULE
37 */
38typedef struct
39{
40 vubyte cr; /* 0xEC00_8000 -> 0xEC00_8000 - Control Register */
41 vubyte pack00[3]; /* 0xEC00_8001 -> 0xEC00_8003 - RESERVED */
42 vubyte div; /* 0xEC00_8004 -> 0xEC00_8004 - Time Divider Register */
43 vubyte pack01[3]; /* 0xEC00_8005 -> 0xEC00_8007 - RESERVED */
44 vubyte rst; /* 0xEC00_8008 -> 0xEC00_8008 - Reset Register */
45 vubyte pack02[3]; /* 0xEC00_8009 -> 0xEC00_800B - RESERVED */
46 vubyte cmd; /* 0xEC00_800C -> 0xEC00_800C - Command Register */
47 vubyte pack03[3]; /* 0xEC00_800D -> 0xEC00_800F - RESERVED */
48 vubyte txrx; /* 0xEC00_8010 -> 0xEC00_8010 - Transmit/Receive Register */
49 vubyte pack04[3]; /* 0xEC00_8011 -> 0xEC00_8013 - RESERVED */
50 vubyte isr; /* 0xEC00_8014 -> 0xEC00_8014 - Interrupt Status Register */
51 vubyte pack05[3]; /* 0xEC00_8015 -> 0xEC00_8017 - RESERVED */
52 vubyte ier; /* 0xEC00_8018 -> 0xEC00_8018 - Interrupt Enable Register */
53 vubyte pack06[3]; /* 0xEC00_8019 -> 0xEC00_801B - RESERVED */
54} owstruct;
55
56/*
57 * I2C MODULE 2-5 (i2c25[4] = 0xEC01_0000 -> 0xEC01_FFFF)
58 */
59typedef struct
60{
61 vubyte i2adr; /* 0x0000 -> 0x0000 - I2C Address Register */
62 vubyte pack00[3]; /* 0x0001 -> 0x0003 - RESERVED */
63 vubyte i2fdr; /* 0x0004 -> 0x0004 - I2C Frequency Divider Register */
64 vubyte pack01[3]; /* 0x0005 -> 0x0007 - RESERVED */
65 vubyte i2cr; /* 0x0008 -> 0x0008 - I2C Control Register */
66 vubyte pack02[3]; /* 0x0009 -> 0x000B - RESERVED */
67 vubyte i2sr; /* 0x000C -> 0x000C - I2C Status Register */
68 vubyte pack03[3]; /* 0x000D -> 0x000F - RESERVED */
69 vubyte i2dr; /* 0x0010 -> 0x0010 - I2C Data I/O Register */
70 vubyte pack04[16367]; /* 0x0011 -> 0x3FFF - RESERVED */
71} i2cstruct;
72//} i2c25struct;
73
74// These typedefs are to prevent issues with code that used references to the old
75// i2c#struct structures, prior to unifying the type definitions.
76typedef i2cstruct i2c25struct;
77typedef i2cstruct i2c1struct;
78typedef i2cstruct i2c0struct;
79
80/*
81 * DMA SERIAL PERIPHERAL INTERFACE 2
82 */
83typedef struct
84{
85 vudword mcr; /* 0xEC03_8000 -> 0xEC03_8003 - Module Configuration Register */
86 vubyte pack00[4]; /* 0xEC03_8004 -> 0xEC03_8007 - RESERVED */
87 vudword tcr; /* 0xEC03_8008 -> 0xEC03_800B - Transfer Count Register */
88 vudword ctar[8]; /* 0xEC03_800C -> 0xEC03_802B - Clock and Transfer Attributes Register 0-7 */
89 vudword sr; /* 0xEC03_802C -> 0xEC03_802F - Status Register */
90 vudword rser; /* 0xEC03_8030 -> 0xEC03_8033 - DMA/Interrupt Request Select and Enable Register */
91 vudword pushr; /* 0xEC03_8034 -> 0xEC03_8037 - Push Tx FIFO Register */
92 vudword popr; /* 0xEC03_8038 -> 0xEC03_803B - Pop Rx FIFO Register */
93 vudword txfr[16]; /* 0xEC03_803C -> 0xEC03_807B - Transmit FIFO Register 0-15 */
94 vudword rxfr[16]; /* 0xEC03_807C -> 0xEC03_80BB - Receive FIFO Register 0-15 */
95} dspistruct;
96//} dspi2struct;
97
98// These typedefs are to prevent issues with code that used references to the old
99// dspi#struct structures, prior to unifying the type definitions.
100typedef dspistruct dspi0struct;
101typedef dspistruct dspi1struct;
102typedef dspistruct dspi2struct;
103typedef dspistruct dspi3struct;
104
105/*
106 * DMA SERIAL PERIPHERAL INTERFACE 3
107 */
108// typedef struct {
109// vudword mcr; /* 0xEC03_C000 -> 0xEC03_C003 - Module Configuration Register */
110// vubyte pack00[4]; /* 0xEC03_C004 -> 0xEC03_C007 - RESERVED */
111// vudword tcr; /* 0xEC03_C008 -> 0xEC03_C00B - Transfer Count Register */
112// vudword ctar[8]; /* 0xEC03_C00C -> 0xEC03_C02B - Clock and Transfer Attributes Register 0-7 */
113// vudword sr; /* 0xEC03_C02C -> 0xEC03_C02F - Status Register */
114// vudword rser; /* 0xEC03_C030 -> 0xEC03_C033 - DMA/Interrupt Request Select and Enable Register */
115// vudword pushr; /* 0xEC03_C034 -> 0xEC03_C037 - Push Tx FIFO Register */
116// vudword popr; /* 0xEC03_C038 -> 0xEC03_C03B - Pop Rx FIFO Register */
117// vudword txfr[16]; /* 0xEC03_C03C -> 0xEC03_C07B - Transmit FIFO Register 0-15 */
118// vudword rxfr[16]; /* 0xEC03_C07C -> 0xEC03_C0BB - Receive FIFO Register 0-15 */
119// } dspi3struct;
120
121/*
122 * UART MODULE 4-9 (uarts[6] = 0xEC06_0000 -> 0xEC07_7FFF)
123 * Same as uartstruct.
124 */
125
126/*
127 * MOTOR CONTROL PULSE-WIDTH MODULATOR SUBMODULE 0-3 (sm[4] = 0xEC08_8000 -> 0xEC08_813F)
128 */
129typedef struct
130{
131 vuword cnt; /* 0x00 -> 0x01 - Counter Register */
132 vuword init; /* 0x02 -> 0x03 - Initial Count Register */
133 vuword cr2; /* 0x04 -> 0x05 - Control Register 2 */
134 vuword cr1; /* 0x06 -> 0x07 - Control Register 1 */
135 vuword val[6]; /* 0x08 -> 0x13 - Value Register 0-5 */
136 vubyte pack00[4]; /* 0x14 -> 0x17 - RESERVED */
137 vuword ocr; /* 0x18 -> 0x19 - Output Control Register */
138 vuword sr; /* 0x1A -> 0x1B - Status Register */
139 vuword ier; /* 0x1C -> 0x1D - Interrupt Enable Register */
140 vuword dmaen; /* 0x1E -> 0x1F - DMA Enable Register */
141 vuword otcr; /* 0x20 -> 0x21 - Output Trigger Control Register */
142 vuword dismap; /* 0x22 -> 0x23 - Fault Disable Mapping Register */
143 vuword dtcnt0; /* 0x24 -> 0x25 - Deadtime Count Register 0 */
144 vuword dtcnt1; /* 0x26 -> 0x27 - Deadtime Count Register 1 */
145 vuword ccra; /* 0x28 -> 0x29 - Capture Control Register A */
146 vuword ccmpa; /* 0x2A -> 0x2B - Capture Compare Register A */
147 vuword ccrb; /* 0x2C -> 0x2D - Capture Control Register B */
148 vuword ccmpb; /* 0x2E -> 0x2F - Capture Compare Register B */
149 vuword ccrx; /* 0x30 -> 0x31 - Capture Control Register X */
150 vuword ccmpx; /* 0x32 -> 0x33 - Capture Compare Register X */
151 vuword cval0; /* 0x34 -> 0x35 - Capture Value 0 Register */
152 vuword ccyc0; /* 0x36 -> 0x37 - Capture Value 0 Cycle Register */
153 vuword cval1; /* 0x38 -> 0x39 - Capture Value 1 Register */
154 vuword ccyc1; /* 0x3A -> 0x3B - Capture Value 1 Cycle Register */
155 vuword cval2; /* 0x3C -> 0x3D - Capture Value 2 Register */
156 vuword ccyc2; /* 0x3E -> 0x3F - Capture Value 2 Cycle Register */
157 vuword cval3; /* 0x40 -> 0x41 - Capture Value 3 Register */
158 vuword ccyc3; /* 0x42 -> 0x43 - Capture Value 3 Cycle Register */
159 vuword cval4; /* 0x44 -> 0x45 - Capture Value 4 Register */
160 vuword ccyc4; /* 0x46 -> 0x47 - Capture Value 4 Cycle Register */
161 vuword cval5; /* 0x48 -> 0x49 - Capture Value 5 Register */
162 vuword ccyc5; /* 0x4A -> 0x4B - Capture Value 5 Cycle Register */
163 vubyte pack01[4]; /* 0x4C -> 0x4F - RESERVED */
164} mcpwm_smstruct;
165
166/*
167 * MOTOR CONTROL PULSE-WIDTH MODULATOR
168 */
169typedef struct
170{
171 mcpwm_smstruct sm[4]; /* 0xEC08_8000 -> 0xEC08_813F - Submodule 0-3 */
172 vuword outen; /* 0xEC08_8140 -> 0xEC08_8141 - Output Enable Register */
173 vuword mask; /* 0xEC08_8142 -> 0xEC08_8143 - Output Mask Register */
174 vuword swcout; /* 0xEC08_8144 -> 0xEC08_8145 - Software Controlled Output Register */
175 vuword dtss; /* 0xEC08_8146 -> 0xEC08_8147 - Deadtime Source Select Register */
176 vuword mcr; /* 0xEC08_8148 -> 0xEC08_8149 - Master Control Register */
177 vubyte pack00[2]; /* 0xEC08_814A -> 0xEC08_814B - RESERVED */
178 vuword fcr; /* 0xEC08_814C -> 0xEC08_814D - Fault Control Register */
179 vuword fsr; /* 0xEC08_814E -> 0xEC08_814F - Fault Status Register */
180 vuword ffilt; /* 0xEC08_8150 -> 0xEC08_8151 - Fault Filter Register */
181 vubyte pack01[2]; /* 0xEC08_8152 -> 0xEC08_8153 - RESERVED */
182} mcpwmstruct;
183
184/*
185 * RESET CONTROLLER
186 */
187typedef struct
188{
189 vubyte rcr; /* 0xEC09_0000 -> 0xEC09_0000 - Reset Control Register */
190 vubyte rsr; /* 0xEC09_0001 -> 0xEC09_0001 - Reset Status Register */
191 vubyte pack00[2]; /* 0xEC09_0002 -> 0xEC09_0003 - RESERVED */
192} resetstruct;
193
194#define CPUID_MCF_54410 0x09F
195#define CPUID_MCF_54415 0x0A0
196#define CPUID_MCF_54416 0x0A1
197#define CPUID_MCF_54417 0x0A2
198#define CPUID_MCF_54418 0x0A3
199
200/*
201 * CHIP CONFIGURATION MODULE
202 */
203typedef struct
204{
205 vuword ccr; /* 0xEC09_0004 -> 0xEC09_0005 - Chip Configuration Register */
206 vubyte pack00; /* 0xEC09_0006 -> 0xEC09_0006 - RESERVED */
207 vubyte lpcr; /* 0xEC09_0007 -> 0xEC09_0007 - Low-Power Control Register */
208 vuword rcon; /* 0xEC09_0008 -> 0xEC09_0009 - Reset Configuration Register */
209 vuword cir; /* 0xEC09_000A -> 0xEC09_000B - Chip Identification Register */
210 vubyte pack01[2]; /* 0xEC09_000C -> 0xEC09_000D - RESERVED */
211 vuword misccr; /* 0xEC09_000E -> 0xEC09_000F - Miscellaneous Control Register */
212 vuword cdrh; /* 0xEC09_0010 -> 0xEC09_0011 - Clock Divider Register High */
213 vuword cdrl; /* 0xEC09_0012 -> 0xEC09_0013 - Clock Divider Register Low */
214 vuword uocsr; /* 0xEC09_0014 -> 0xEC09_0015 - USB On-the-Go Controller Status Register */
215 vuword uhcsr; /* 0xEC09_0016 -> 0xEC09_0017 - USB Host Controller Status Register */
216 vuword misccr3; /* 0xEC09_0018 -> 0xEC09_0019 - Miscellaneous Control Register 3 */
217 vuword misccr2; /* 0xEC09_001A -> 0xEC09_001B - Miscellaneous Control Register 2 */
218 vuword adctsr; /* 0xEC09_001C -> 0xEC09_001D - ADC Trigger Select Register */
219 vuword dactsr; /* 0xEC09_001E -> 0xEC09_001F - DAC Trigger Select Register */
220 vuword sbfsr; /* 0xEC09_0020 -> 0xEC09_0021 - Serial Boot Facility Status Register */
221 vuword sbfcr; /* 0xEC09_0022 -> 0xEC09_0023 - Serial Boot Facility Control Register */
222 vudword fnacr; /* 0xEC09_0024 -> 0xEC09_0027 - FlexBus/NAND Flash Arbiter Control Register */
223} ccmstruct;
224
225/*
226 * PIN-MULTIPLEXING AND CONTROL (GPIO)
227 */
228typedef struct
229{
230 vubyte podr_a; /* 0xEC09_4000 -> 0xEC09_4000 - Port Output Data Register A */
231 vubyte podr_b; /* 0xEC09_4001 -> 0xEC09_4001 - Port Output Data Register B */
232 vubyte podr_c; /* 0xEC09_4002 -> 0xEC09_4002 - Port Output Data Register C */
233 vubyte podr_d; /* 0xEC09_4003 -> 0xEC09_4003 - Port Output Data Register D */
234 vubyte podr_e; /* 0xEC09_4004 -> 0xEC09_4004 - Port Output Data Register E */
235 vubyte podr_f; /* 0xEC09_4005 -> 0xEC09_4005 - Port Output Data Register F */
236 vubyte podr_g; /* 0xEC09_4006 -> 0xEC09_4006 - Port Output Data Register G */
237 vubyte podr_h; /* 0xEC09_4007 -> 0xEC09_4007 - Port Output Data Register H */
238 vubyte podr_i; /* 0xEC09_4008 -> 0xEC09_4008 - Port Output Data Register I */
239 vubyte podr_j; /* 0xEC09_4009 -> 0xEC09_4009 - Port Output Data Register J */
240 vubyte podr_k; /* 0xEC09_400A -> 0xEC09_400A - Port Output Data Register K */
241 vubyte pack00; /* 0xEC09_400B -> 0xEC09_400B - RESERVED */
242 vubyte pddr_a; /* 0xEC09_400C -> 0xEC09_400C - Port Data Direction Register A */
243 vubyte pddr_b; /* 0xEC09_400D -> 0xEC09_400D - Port Data Direction Register B */
244 vubyte pddr_c; /* 0xEC09_400E -> 0xEC09_400E - Port Data Direction Register C */
245 vubyte pddr_d; /* 0xEC09_400F -> 0xEC09_400F - Port Data Direction Register D */
246 vubyte pddr_e; /* 0xEC09_4010 -> 0xEC09_4010 - Port Data Direction Register E */
247 vubyte pddr_f; /* 0xEC09_4011 -> 0xEC09_4011 - Port Data Direction Register F */
248 vubyte pddr_g; /* 0xEC09_4012 -> 0xEC09_4012 - Port Data Direction Register G */
249 vubyte pddr_h; /* 0xEC09_4013 -> 0xEC09_4013 - Port Data Direction Register H */
250 vubyte pddr_i; /* 0xEC09_4014 -> 0xEC09_4014 - Port Data Direction Register I */
251 vubyte pddr_j; /* 0xEC09_4015 -> 0xEC09_4015 - Port Data Direction Register J */
252 vubyte pddr_k; /* 0xEC09_4016 -> 0xEC09_4016 - Port Data Direction Register K */
253 vubyte pack01; /* 0xEC09_4017 -> 0xEC09_4017 - RESERVED */
254 vubyte ppdsdr_a; /* 0xEC09_4018 -> 0xEC09_4018 - Port Pin Data/Set Data Register A */
255 vubyte ppdsdr_b; /* 0xEC09_4019 -> 0xEC09_4019 - Port Pin Data/Set Data Register B */
256 vubyte ppdsdr_c; /* 0xEC09_401A -> 0xEC09_401A - Port Pin Data/Set Data Register C */
257 vubyte ppdsdr_d; /* 0xEC09_401B -> 0xEC09_401B - Port Pin Data/Set Data Register D */
258 vubyte ppdsdr_e; /* 0xEC09_401C -> 0xEC09_401C - Port Pin Data/Set Data Register E */
259 vubyte ppdsdr_f; /* 0xEC09_401D -> 0xEC09_401D - Port Pin Data/Set Data Register F */
260 vubyte ppdsdr_g; /* 0xEC09_401E -> 0xEC09_401E - Port Pin Data/Set Data Register G */
261 vubyte ppdsdr_h; /* 0xEC09_401F -> 0xEC09_401F - Port Pin Data/Set Data Register H */
262 vubyte ppdsdr_i; /* 0xEC09_4020 -> 0xEC09_4020 - Port Pin Data/Set Data Register I */
263 vubyte ppdsdr_j; /* 0xEC09_4021 -> 0xEC09_4021 - Port Pin Data/Set Data Register J */
264 vubyte ppdsdr_k; /* 0xEC09_4022 -> 0xEC09_4022 - Port Pin Data/Set Data Register K */
265 vubyte pack02; /* 0xEC09_4023 -> 0xEC09_4023 - RESERVED */
266 vubyte pclrr_a; /* 0xEC09_4024 -> 0xEC09_4024 - Port Clear Output Data Register A */
267 vubyte pclrr_b; /* 0xEC09_4025 -> 0xEC09_4025 - Port Clear Output Data Register B */
268 vubyte pclrr_c; /* 0xEC09_4026 -> 0xEC09_4026 - Port Clear Output Data Register C */
269 vubyte pclrr_d; /* 0xEC09_4027 -> 0xEC09_4027 - Port Clear Output Data Register D */
270 vubyte pclrr_e; /* 0xEC09_4028 -> 0xEC09_4028 - Port Clear Output Data Register E */
271 vubyte pclrr_f; /* 0xEC09_4029 -> 0xEC09_4029 - Port Clear Output Data Register F */
272 vubyte pclrr_g; /* 0xEC09_402A -> 0xEC09_402A - Port Clear Output Data Register G */
273 vubyte pclrr_h; /* 0xEC09_402B -> 0xEC09_402B - Port Clear Output Data Register H */
274 vubyte pclrr_i; /* 0xEC09_402C -> 0xEC09_402C - Port Clear Output Data Register I */
275 vubyte pclrr_j; /* 0xEC09_402D -> 0xEC09_402D - Port Clear Output Data Register J */
276 vubyte pclrr_k; /* 0xEC09_402E -> 0xEC09_402E - Port Clear Output Data Register K */
277 vubyte pack03; /* 0xEC09_402F -> 0xEC09_402F - RESERVED */
278 vuword pcr_a; /* 0xEC09_4030 -> 0xEC09_4031 - Pull Control Register A */
279 vuword pcr_b; /* 0xEC09_4032 -> 0xEC09_4033 - Pull Control Register B */
280 vuword pcr_c; /* 0xEC09_4034 -> 0xEC09_4035 - Pull Control Register C */
281 vuword pcr_d; /* 0xEC09_4036 -> 0xEC09_4037 - Pull Control Register D */
282 vuword pcr_e; /* 0xEC09_4038 -> 0xEC09_4039 - Pull Control Register E */
283 vuword pcr_f; /* 0xEC09_403A -> 0xEC09_403B - Pull Control Register F */
284 vuword pcr_g; /* 0xEC09_403C -> 0xEC09_403D - Pull Control Register G */
285 vuword pcr_h; /* 0xEC09_403E -> 0xEC09_403F - Pull Control Register H */
286 vuword pcr_i; /* 0xEC09_4040 -> 0xEC09_4041 - Pull Control Register I */
287 vuword pcr_j; /* 0xEC09_4042 -> 0xEC09_4043 - Pull Control Register J */
288 vuword pcr_k; /* 0xEC09_4044 -> 0xEC09_4045 - Pull Control Register K */
289 vubyte pack04[2]; /* 0xEC09_4046 -> 0xEC09_4047 - RESERVED */
290 vubyte par_fbctl; /* 0xEC09_4048 -> 0xEC09_4048 - Pin Assignment Register - FlexBus Control */
291 vubyte par_be; /* 0xEC09_4049 -> 0xEC09_4049 - Pin Assignment Register - Byte Enable */
292 vubyte par_cs; /* 0xEC09_404A -> 0xEC09_404A - Pin Assignment Register - Chip Select */
293 vubyte par_cani2c; /* 0xEC09_404B -> 0xEC09_404B - Pin Assignment Register - CAN1 and I2C0 */
294 vubyte par_irq0h; /* 0xEC09_404C -> 0xEC09_404C - Pin Assignment Register - Edge Port 0 High */
295 vubyte par_irq0l; /* 0xEC09_404D -> 0xEC09_404D - Pin Assignment Register - Edge Port 0 Low */
296 vubyte par_dspiowh; /* 0xEC09_404E -> 0xEC09_404E - Pin Assignment Register - DSPI0 and One-Wire High */
297 vubyte par_dspiowl; /* 0xEC09_404F -> 0xEC09_404F - Pin Assignment Register - DSPI0 and One-Wire Low */
298 vubyte par_timer; /* 0xEC09_4050 -> 0xEC09_4050 - Pin Assignment Register - Timer */
299 vubyte par_uart2; /* 0xEC09_4051 -> 0xEC09_4051 - Pin Assignment Register - UART 2 */
300 vubyte par_uart1; /* 0xEC09_4052 -> 0xEC09_4052 - Pin Assignment Register - UART 1 */
301 vubyte par_uart0; /* 0xEC09_4053 -> 0xEC09_4053 - Pin Assignment Register - UART 0 */
302 vubyte par_sdhch; /* 0xEC09_4054 -> 0xEC09_4054 - Pin Assignment Register - eSDHC High */
303 vubyte par_sdhcl; /* 0xEC09_4055 -> 0xEC09_4055 - Pin Assignment Register - eSDHC Low */
304 vubyte par_simp0h; /* 0xEC09_4056 -> 0xEC09_4056 - Pin Assignment Register - SIM Port 0 High */
305 vubyte par_simp0l; /* 0xEC09_4057 -> 0xEC09_4057 - Pin Assignment Register - SIM Port 0 Low */
306 vubyte par_ssi0h; /* 0xEC09_4058 -> 0xEC09_4058 - Pin Assignment Register - SSI0 High */
307 vubyte par_ssi0l; /* 0xEC09_4059 -> 0xEC09_4059 - Pin Assignment Register - SSI0 Low */
308 vubyte par_debugh1; /* 0xEC09_405A -> 0xEC09_405A - Pin Assignment Register - Debug High 1 */
309 vubyte par_debugh0; /* 0xEC09_405B -> 0xEC09_405B - Pin Assignment Register - Debug High 0 */
310 vubyte par_debugl; /* 0xEC09_405C -> 0xEC09_405C - Pin Assignment Register - Debug Low */
311 vubyte pack05; /* 0xEC09_405D -> 0xEC09_405D - RESERVED */
312 vubyte par_fec; /* 0xEC09_405E -> 0xEC09_405E - Pin Assignment Register - Fast Ethernet Channel */
313 vubyte pack06; /* 0xEC09_405F -> 0xEC09_405F - RESERVED */
314 vubyte mscr_sdramc; /* 0xEC09_4060 -> 0xEC09_4060 - Mode Select Control Register - SDRAM Controller */
315 vubyte pack07[3]; /* 0xEC09_4061 -> 0xEC09_4063 - RESERVED */
316 vubyte srcr_fb1; /* 0xEC09_4064 -> 0xEC09_4064 - Slew Rate Control Register - FlexBus 1 */
317 vubyte srcr_fb2; /* 0xEC09_4065 -> 0xEC09_4065 - Slew Rate Control Register - FlexBus 2 */
318 vubyte srcr_fb3; /* 0xEC09_4066 -> 0xEC09_4066 - Slew Rate Control Register - FlexBus 3 */
319 vubyte srcr_fb4; /* 0xEC09_4067 -> 0xEC09_4067 - Slew Rate Control Register - FlexBus 4 */
320 vubyte srcr_dspiow; /* 0xEC09_4068 -> 0xEC09_4068 - Slew Rate Control Register - DSPI0 and One-Wire */
321 vubyte srcr_cani2c; /* 0xEC09_4069 -> 0xEC09_4069 - Slew Rate Control Register - CAN1 and I2C0 */
322 vubyte srcr_irq0; /* 0xEC09_406A -> 0xEC09_406A - Slew Rate Control Register - Edge Port 0 */
323 vubyte srcr_timer; /* 0xEC09_406B -> 0xEC09_406B - Slew Rate Control Register - Timer */
324 vubyte srcr_uart; /* 0xEC09_406C -> 0xEC09_406C - Slew Rate Control Register - UART */
325 vubyte srcr_fec; /* 0xEC09_406D -> 0xEC09_406D - Slew Rate Control Register - Fast Ethernet Channel */
326 vubyte srcr_sdhc; /* 0xEC09_406E -> 0xEC09_406E - Slew Rate Control Register - eSDHC */
327 vubyte srcr_simp0; /* 0xEC09_406F -> 0xEC09_406F - Slew Rate Control Register - SIM Port 0 */
328 vubyte srcr_ssi0; /* 0xEC09_4070 -> 0xEC09_4070 - Slew Rate Control Register - SSI0 */
329 vubyte pack08[3]; /* 0xEC09_4071 -> 0xEC09_4073 - RESERVED */
330 vuword urts_pol; /* 0xEC09_4074 -> 0xEC09_4075 - Miscellaneous UART Register - RTS Polarity Control */
331 vuword ucts_pol; /* 0xEC09_4076 -> 0xEC09_4077 - Miscellaneous UART Register - CTS Polarity Control */
332 vuword utxd_wom; /* 0xEC09_4078 -> 0xEC09_4079 - Miscellaneous UART Register - Tx Wired-Or Mode Control */
333 vubyte pack09[2]; /* 0xEC09_407A -> 0xEC09_407B - RESERVED */
334 vudword urxd_wom; /* 0xEC09_407C -> 0xEC09_407F - Miscellaneous UART Register - Rx Wired-Or Mode Control */
335 vudword hcr1; /* 0xEC09_4080 -> 0xEC09_4083 - Hysteresis Control Register 1 */
336 vudword hcr0; /* 0xEC09_4084 -> 0xEC09_4087 - Hysteresis Control Register 0 */
337} gpiostruct;
338
339/*
340 * CROSSBAR SWITCH (XBS)
341 */
342typedef struct
343{
344 vudword prs0; /* 0xFC00_4000 -> 0xFC00_4003 - Priority Register Slave 0 */
345 vubyte pack00[12]; /* 0xFC00_4004 -> 0xFC00_400F - RESERVED */
346 vudword crs0; /* 0xFC00_4010 -> 0xFC00_4013 - Control Register Slave 0 */
347 vubyte pack01[236]; /* 0xFC00_4014 -> 0xFC00_40FF - RESERVED */
348 vudword prs1; /* 0xFC00_4100 -> 0xFC00_4103 - Priority Register Slave 1 */
349 vubyte pack02[12]; /* 0xFC00_4104 -> 0xFC00_410F - RESERVED */
350 vudword crs1; /* 0xFC00_4110 -> 0xFC00_4113 - Control Register Slave 1 */
351 vubyte pack03[236]; /* 0xFC00_4114 -> 0xFC00_41FF - RESERVED */
352 vudword prs2; /* 0xFC00_4200 -> 0xFC00_4203 - Priority Register Slave 2 */
353 vubyte pack04[12]; /* 0xFC00_4204 -> 0xFC00_420F - RESERVED */
354 vudword crs2; /* 0xFC00_4210 -> 0xFC00_4213 - Control Register Slave 2 */
355 vubyte pack05[492]; /* 0xFC00_4214 -> 0xFC00_43FF - RESERVED */
356 vudword prs4; /* 0xFC00_4400 -> 0xFC00_4403 - Priority Register Slave 4 */
357 vubyte pack06[12]; /* 0xFC00_4404 -> 0xFC00_440F - RESERVED */
358 vudword crs4; /* 0xFC00_4410 -> 0xFC00_4413 - Control Register Slave 4 */
359 vubyte pack07[492]; /* 0xFC00_4414 -> 0xFC00_45FF - RESERVED */
360 vudword prs6; /* 0xFC00_4600 -> 0xFC00_4603 - Priority Register Slave 6 */
361 vubyte pack08[12]; /* 0xFC00_4604 -> 0xFC00_460F - RESERVED */
362 vudword crs6; /* 0xFC00_4610 -> 0xFC00_4613 - Control Register Slave 6 */
363 vubyte pack09[236]; /* 0xFC00_4614 -> 0xFC00_46FF - RESERVED */
364 vudword prs7; /* 0xFC00_4700 -> 0xFC00_4703 - Priority Register Slave 7 */
365 vubyte pack10[12]; /* 0xFC00_4704 -> 0xFC00_470F - RESERVED */
366 vudword crs7; /* 0xFC00_4710 -> 0xFC00_4713 - Control Register Slave 7 */
367} xbsstruct;
368
369/*
370 * CHIP SELECT 0-5 (cs[6] = 0xFC00_8000 -> 0xFC00_8047)
371 */
372typedef struct
373{
374 vudword csar; /* 0x0000 -> 0x0003 - Chip Select Address Register */
375 vudword csmr; /* 0x0004 -> 0x0007 - Chip Select Mask Register */
376 vudword cscr; /* 0x0008 -> 0x000B - Chip Select Control Register */
377} csstruct;
378
379/*
380 * CONTROLLER AREA NETWORK MESSAGE BUFFER
381 */
382typedef struct
383{
384 vuword bStatus; /* 0x00 -> 0x01 - Code[11:8]; SRR[6]; IDE[5]; RTR[4]; Length[3:0] */
385 vuword bTimeStamp; /* 0x02 -> 0x03 - Time Stamp */
386 vudword id; /* 0x04 -> 0x07 - Standard ID[28:18]; Extended ID[17:0] */
387 vubyte data[8]; /* 0x08 -> 0x0F - Data Bytes 0-7 */
388} can_mbstruct;
389
390/*
391 * CONTROLLER AREA NETWORK (FLEXCAN) 0-1 (can[2] = 0xFC02_0000 -> 0xFC02_7FFF)
392 */
393typedef struct
394{
395 vudword canmcr; /* 0x0000 -> 0x0003 - Module Configuration Register */
396 vudword canctrl; /* 0x0004 -> 0x0007 - Control Register */
397 vudword timer; /* 0x0008 -> 0x000B - Free Running Timer */
398 vubyte pack00[4]; /* 0x000C -> 0x000F - RESERVED */
399 vudword rxgmask; /* 0x0010 -> 0x0013 - Rx Global Mask */
400 vudword rx14mask; /* 0x0014 -> 0x0017 - Rx Buffer 14 Mask */
401 vudword rx15mask; /* 0x0018 -> 0x001B - Rx Buffer 15 Mask */
402 vudword errcnt; /* 0x001C -> 0x001F - Error Counter Register */
403 vudword errstat; /* 0x0020 -> 0x0023 - Error and Status Register */
404 vubyte pack01[4]; /* 0x0024 -> 0x0027 - RESERVED */
405 vudword imask; /* 0x0028 -> 0x002B - Interrupt Mask Register */
406 vubyte pack02[4]; /* 0x002C -> 0x002F - RESERVED */
407 vudword iflag; /* 0x0030 -> 0x0033 - Interrupt Flag Register */
408 vubyte pack03[76]; /* 0x0034 -> 0x007F - RESERVED */
409 can_mbstruct mbs[16]; /* 0x0080 -> 0x017F - Message Buffers 0-15 */
410 vubyte pack04[1792]; /* 0x0180 -> 0x087F - RESERVED */
411 vudword rximr[16]; /* 0x0880 -> 0x08BF - Rx Individual Mask Registers 0-15 */
412 vubyte pack05[14144]; /* 0x08C0 -> 0x3FFF - RESERVED */
413} canstruct;
414
415/*
416 * I2C MODULE 1
417 */
418// typedef struct {
419// vubyte i2adr; /* 0xFC03_8000 -> 0xFC03_8000 - I2C Address Register */
420// vubyte pack00[3]; /* 0xFC03_8001 -> 0xFC03_8003 - RESERVED */
421// vubyte i2fdr; /* 0xFC03_8004 -> 0xFC03_8004 - I2C Frequency Divider Register */
422// vubyte pack01[3]; /* 0xFC03_8005 -> 0xFC03_8007 - RESERVED */
423// vubyte i2cr; /* 0xFC03_8008 -> 0xFC03_8008 - I2C Control Register */
424// vubyte pack02[3]; /* 0xFC03_8009 -> 0xFC03_800B - RESERVED */
425// vubyte i2sr; /* 0xFC03_800C -> 0xFC03_800C - I2C Status Register */
426// vubyte pack03[3]; /* 0xFC03_800D -> 0xFC03_800F - RESERVED */
427// vubyte i2dr; /* 0xFC03_8010 -> 0xFC03_8010 - I2C Data I/O Register */
428// vubyte pack04[3]; /* 0xFC03_8011 -> 0xFC03_8013 - RESERVED */
429// } i2c1struct;
430
431/*
432 * DMA SERIAL PERIPHERAL INTERFACE 1
433 */
434// typedef struct {
435// vudword mcr; /* 0xFC03_C000 -> 0xFC03_C003 - Module Configuration Register */
436// vubyte pack00[4]; /* 0xFC03_C004 -> 0xFC03_C007 - RESERVED */
437// vudword tcr; /* 0xFC03_C008 -> 0xFC03_C00B - Transfer Count Register */
438// vudword ctar[8]; /* 0xFC03_C00C -> 0xFC03_C02B - Clock and Transfer Attributes Register 0-7 */
439// vudword sr; /* 0xFC03_C02C -> 0xFC03_C02F - Status Register */
440// vudword rser; /* 0xFC03_C030 -> 0xFC03_C033 - DMA/Interrupt Request Select and Enable Register */
441// vudword pushr; /* 0xFC03_C034 -> 0xFC03_C037 - Push Tx FIFO Register */
442// vudword popr; /* 0xFC03_C038 -> 0xFC03_C03B - Pop Rx FIFO Register */
443// vudword txfr[16]; /* 0xFC03_C03C -> 0xFC03_C07B - Transmit FIFO Register 0-15 */
444// vudword rxfr[16]; /* 0xFC03_C07C -> 0xFC03_C0BB - Receive FIFO Register 0-15 */
445// } dspi1struct;
446
447/*
448 * SYSTEM CONTROL MODULE AND POWER MANAGEMENT
449 */
450typedef struct
451{
452 vubyte pack00[3]; /* 0xFC04_0010 -> 0xFC04_0012 - RESERVED */
453 vubyte wcr; /* 0xFC04_0013 -> 0xFC04_0013 - Wakeup Control Register */
454 vubyte pack01[2]; /* 0xFC04_0014 -> 0xFC04_0015 - RESERVED */
455 vuword cwcr; /* 0xFC04_0016 -> 0xFC04_0017 - Core Watchdog Control Register */
456 vubyte pack02[3]; /* 0xFC04_0018 -> 0xFC04_001A - RESERVED */
457 vubyte cwsr; /* 0xFC04_001B -> 0xFC04_001B - Core Watchdog Service Register */
458 vubyte pack03[3]; /* 0xFC04_001C -> 0xFC04_001E - RESERVED */
459 vubyte scmisr; /* 0xFC04_001F -> 0xFC04_001F - SCM Interrupt Status Register */
460 vubyte pack04[4]; /* 0xFC04_0020 -> 0xFC04_0023 - RESERVED */
461 vudword bcr; /* 0xFC04_0024 -> 0xFC04_0027 - Burst Configuration Register */
462 vubyte pack05[4]; /* 0xFC04_0028 -> 0xFC04_002B - RESERVED */
463 vubyte ppmsr0; /* 0xFC04_002C -> 0xFC04_002C - Peripheral Power Management Set Register 0 */
464 vubyte ppmcr0; /* 0xFC04_002D -> 0xFC04_002D - Peripheral Power Management Clear Register 0 */
465 vubyte ppmsr1; /* 0xFC04_002E -> 0xFC04_002E - Peripheral Power Management Set Register 1 */
466 vubyte ppmcr1; /* 0xFC04_002F -> 0xFC04_002F - Peripheral Power Management Clear Register 1 */
467 vudword ppmhr0; /* 0xFC04_0030 -> 0xFC04_0033 - Peripheral Power Management High Register 0 */
468 vudword ppmlr0; /* 0xFC04_0034 -> 0xFC04_0037 - Peripheral Power Management Low Register 0 */
469 vudword ppmhr1; /* 0xFC04_0038 -> 0xFC04_003B - Peripheral Power Management High Register 1 */
470 vudword ppmlr1; /* 0xFC04_003C -> 0xFC04_003F - Peripheral Power Management Low Register 1 */
471 vubyte pack06[48]; /* 0xFC04_0040 -> 0xFC04_006F - RESERVED */
472 vudword cfadr; /* 0xFC04_0070 -> 0xFC04_0073 - Core Fault Address Register */
473 vubyte pack07; /* 0xFC04_0074 -> 0xFC04_0074 - RESERVED */
474 vubyte cfier; /* 0xFC04_0075 -> 0xFC04_0075 - Core Fault Interrupt Enable Register */
475 vubyte cfloc; /* 0xFC04_0076 -> 0xFC04_0076 - Core Fault Location Register */
476 vubyte cfatr; /* 0xFC04_0077 -> 0xFC04_0077 - Core Fault Attributes Register */
477 vubyte pack08[4]; /* 0xFC04_0078 -> 0xFC04_007B - RESERVED */
478 vudword cfdtr; /* 0xFC04_007C -> 0xFC04_007F - Core Fault Data Register */
479} scmstruct;
480
481/*
482 * EDMA TRANSFER CONTROL DESCRIPTOR (tcd[16] = 0xFC04_5000 -> 0xFC04_51FF)
483 */
484typedef struct
485{
486 vudword saddr; /* 0x0000 -> 0x0003 - Source Address */
487 vuword attr; /* 0x0004 -> 0x0005 - Transfer Attributes */
488 vuword soff; /* 0x0006 -> 0x0007 - Signed Source Address Offset */
489 vudword nbytes; /* 0x0008 -> 0x000B - Signed Minor Loop Offset/Minor Byte Count */
490 vudword slast; /* 0x000C -> 0x000F - Last Source Address Adjustment */
491 vudword daddr; /* 0x0010 -> 0x0013 - Destination Address */
492 vuword citer; /* 0x0014 -> 0x0015 - Current Minor Loop Link/Major Loop Count */
493 vuword doff; /* 0x0016 -> 0x0017 - Signed Destination Address Offset */
494 vudword dlast_sga; /* 0x0018 -> 0x001B - Last Destination Addr. Adjustment/Scatter Gather Addr. */
495 vuword biter; /* 0x001C -> 0x001D - Beginning Minor Loop Link/Major Loop Count */
496 vuword csr; /* 0x001E -> 0x001F - Control and Status */
497} edma_tcdstruct;
498
499/*
500 * ENHANCED DIRECT MEMORY ACCESS (EDMA) CONTROLLER
501 */
502typedef struct
503{
504 vudword cr; /* 0xFC04_4000 -> 0xFC04_4003 - eDMA Control Register */
505 vudword es; /* 0xFC04_4004 -> 0xFC04_4007 - eDMA Error Status Register */
506 vudword erqh; /* 0xFC04_4008 -> 0xFC04_400B - eDMA Enable Request High Register */
507 vudword erql; /* 0xFC04_400C -> 0xFC04_400F - eDMA Enable Request Register */
508 vudword eeih; /* 0xFC04_4010 -> 0xFC04_4013 - eDMA Enable Error Interrupt High Register */
509 vudword eeil; /* 0xFC04_4014 -> 0xFC04_4017 - eDMA Enable Error Interrupt Low Register */
510 vubyte serq; /* 0xFC04_4018 -> 0xFC04_4018 - eDMA Set Enable Request */
511 vubyte cerq; /* 0xFC04_4019 -> 0xFC04_4019 - eDMA Clear Enable Request */
512 vubyte seei; /* 0xFC04_401A -> 0xFC04_401A - eDMA Set Enable Error Interrupt Register */
513 vubyte ceei; /* 0xFC04_401B -> 0xFC04_401B - eDMA Clear Enable Error Interrupt Register */
514 vubyte cint; /* 0xFC04_401C -> 0xFC04_401C - eDMA Clear Interrupt Request Register */
515 vubyte cerr; /* 0xFC04_401D -> 0xFC04_401D - eDMA Clear Error Register */
516 vubyte ssrt; /* 0xFC04_401E -> 0xFC04_401E - eDMA Set START Bit Register */
517 vubyte cdne; /* 0xFC04_401F -> 0xFC04_401F - eDMA Clear DONE Status Bit Register */
518 vudword inth; /* 0xFC04_4020 -> 0xFC04_4023 - eDMA Interrupt Request High Register */
519 vudword intl; /* 0xFC04_4024 -> 0xFC04_4027 - eDMA Interrupt Request Low Register */
520 vudword errh; /* 0xFC04_4028 -> 0xFC04_402B - eDMA Error High Register */
521 vudword errl; /* 0xFC04_402C -> 0xFC04_402F - eDMA Error Low Register */
522 vudword rsh; /* 0xFC04_4030 -> 0xFC04_4033 - eDMA Hardware Request Status High */
523 vudword rsl; /* 0xFC04_4034 -> 0xFC04_4037 - eDMA Hardware Request Status Low */
524 vubyte pack00[200]; /* 0xFC04_4038 -> 0xFC04_40FF - RESERVED */
525 vubyte dchpri[64]; /* 0xFC04_4100 -> 0xFC04_413F - eDMA Channel 0-64 Priority Registers */
526 vubyte pack05[3776]; /* 0xFC04_4140 -> 0xFC04_4FFF - RESERVED */
527 edma_tcdstruct tcd[64]; /* 0xFC04_5000 -> 0xFC04_57FF - Transfer Control Descriptor 0-64 */
528} edmastruct;
529
530/*
531 * INTERRUPT CONTROLLER 0-2 (intc[3] = 0xFC04_8000 -> 0xFC05_3FFF)
532 */
533typedef struct
534{
535 vudword iprh; /* 0x0000 -> 0x0003 - Interrupt Pending Register High */
536 vudword iprl; /* 0x0004 -> 0x0007 - Interrupt Pending Register Low */
537 vudword imrh; /* 0x0008 -> 0x000B - Interrupt Mask Register High */
538 vudword imrl; /* 0x000C -> 0x000F - Interrupt Mask Register Low */
539 vudword intfrch; /* 0x0010 -> 0x0013 - Interrupt Force Register High */
540 vudword intfrcl; /* 0x0014 -> 0x0017 - Interrupt Force Register Low */
541 vubyte pack00[2]; /* 0x0018 -> 0x0019 - RESERVED */
542 vuword iconfig; /* 0x001A -> 0x001B - Interrupt Configuration Register */
543 vubyte simr; /* 0x001C -> 0x001C - Set Interrupt Mask */
544 vubyte cimr; /* 0x001D -> 0x001D - Clear Interrupt Mask */
545 vubyte clmask; /* 0x001E -> 0x001E - Current Level Mask */
546 vubyte slmask; /* 0x001F -> 0x001F - Saved Level Mask */
547 vubyte pack01[32]; /* 0x0020 -> 0x003F - RESERVED */
548 vubyte icrn[64]; /* 0x0040 -> 0x007F - Interrupt Control Registers (0-63) */
549 vubyte pack02[96]; /* 0x0080 -> 0x00DF - RESERVED */
550 vubyte swackr; /* 0x00E0 -> 0x00E0 - Software IACK Register */
551 vubyte pack03[3]; /* 0x00E1 -> 0x00E3 - RESERVED */
552 vubyte l1ackr; /* 0x00E4 -> 0x00E4 - Level 1 IACK Register */
553 vubyte pack04[3]; /* 0x00E5 -> 0x00E7 - RESERVED */
554 vubyte l2ackr; /* 0x00E8 -> 0x00E8 - Level 2 IACK Register */
555 vubyte pack05[3]; /* 0x00E9 -> 0x00EB - RESERVED */
556 vubyte l3ackr; /* 0x00EC -> 0x00EC - Level 3 IACK Register */
557 vubyte pack06[3]; /* 0x00ED -> 0x00EF - RESERVED */
558 vubyte l4ackr; /* 0x00F0 -> 0x00F0 - Level 4 IACK Register */
559 vubyte pack07[3]; /* 0x00F1 -> 0x00F3 - RESERVED */
560 vubyte l5ackr; /* 0x00F4 -> 0x00F4 - Level 5 IACK Register */
561 vubyte pack08[3]; /* 0x00F5 -> 0x00F7 - RESERVED */
562 vubyte l6ackr; /* 0x00F8 -> 0x00F8 - Level 6 IACK Register */
563 vubyte pack09[3]; /* 0x00F9 -> 0x00FB - RESERVED */
564 vubyte l7ackr; /* 0x00FC -> 0x00FC - Level 7 IACK Register */
565 vubyte pack10[16131]; /* 0x00FD -> 0x3FFF - RESERVED */
566} intcstruct;
567
568/*
569 * GLOBAL INTERRUPT ACKNOWLEDGE CYCLES
570 */
571typedef struct
572{
573 vubyte gswiack; /* 0xFC05_40E0 -> 0xFC05_40E0 - Global Software Interrupt Acknowledge */
574 vubyte pack00[3]; /* 0xFC05_40E1 -> 0xFC05_40E3 - RESERVED */
575 vubyte gl1iack; /* 0xFC05_40E4 -> 0xFC05_40E4 - Global Level 1 Interrupt Acknowledge Register */
576 vubyte pack01[3]; /* 0xFC05_40E5 -> 0xFC05_40E7 - RESERVED */
577 vubyte gl2iack; /* 0xFC05_40E8 -> 0xFC05_40E8 - Global Level 2 Interrupt Acknowledge Register */
578 vubyte pack02[3]; /* 0xFC05_40E9 -> 0xFC05_40EB - RESERVED */
579 vubyte gl3iack; /* 0xFC05_40EC -> 0xFC05_40EC - Global Level 3 Interrupt Acknowledge Register */
580 vubyte pack03[3]; /* 0xFC05_40ED -> 0xFC05_40EF - RESERVED */
581 vubyte gl4iack; /* 0xFC05_40F0 -> 0xFC05_40F0 - Global Level 4 Interrupt Acknowledge Register */
582 vubyte pack04[3]; /* 0xFC05_40F1 -> 0xFC05_40F3 - RESERVED */
583 vubyte gl5iack; /* 0xFC05_40F4 -> 0xFC05_40F4 - Global Level 5 Interrupt Acknowledge Register */
584 vubyte pack05[3]; /* 0xFC05_40F5 -> 0xFC05_40F7 - RESERVED */
585 vubyte gl6iack; /* 0xFC05_40F8 -> 0xFC05_40F8 - Global Level 6 Interrupt Acknowledge Register */
586 vubyte pack06[3]; /* 0xFC05_40F9 -> 0xFC05_40FB - RESERVED */
587 vubyte gl7iack; /* 0xFC05_40FC -> 0xFC05_40FC - Global Level 7 Interrupt Acknowledge Register */
588 vubyte pack07[3]; /* 0xFC05_40FD -> 0xFC05_40FF - RESERVED */
589} intc_iackstruct;
590
591/*
592 * I2C MODULE 0
593 */
594// typedef struct {
595// vubyte i2adr; /* 0xFC05_8000 -> 0xFC05_8000 - I2C Address Register */
596// vubyte pack00[3]; /* 0xFC05_8001 -> 0xFC05_8003 - RESERVED */
597// vubyte i2fdr; /* 0xFC05_8004 -> 0xFC05_8004 - I2C Frequency Divider Register */
598// vubyte pack01[3]; /* 0xFC05_8005 -> 0xFC05_8007 - RESERVED */
599// vubyte i2cr; /* 0xFC05_8008 -> 0xFC05_8008 - I2C Control Register */
600// vubyte pack02[3]; /* 0xFC05_8009 -> 0xFC05_800B - RESERVED */
601// vubyte i2sr; /* 0xFC05_800C -> 0xFC05_800C - I2C Status Register */
602// vubyte pack03[3]; /* 0xFC05_800D -> 0xFC05_800F - RESERVED */
603// vubyte i2dr; /* 0xFC05_8010 -> 0xFC05_8010 - I2C Data I/O Register */
604// vubyte pack04[3]; /* 0xFC05_8011 -> 0xFC05_8013 - RESERVED */
605// } i2c0struct;
606
607/*
608 * DMA SERIAL PERIPHERAL INTERFACE 0
609 */
610// typedef struct {
611// vudword mcr; /* 0xFC05_C000 -> 0xFC05_C003 - Module Configuration Register */
612// vubyte pack00[4]; /* 0xFC05_C004 -> 0xFC05_C007 - RESERVED */
613// vudword tcr; /* 0xFC05_C008 -> 0xFC05_C00B - Transfer Count Register */
614// vudword ctar[8]; /* 0xFC05_C00C -> 0xFC05_C02B - Clock and Transfer Attributes Register 0-7 */
615// vudword sr; /* 0xFC05_C02C -> 0xFC05_C02F - Status Register */
616// vudword rser; /* 0xFC05_C030 -> 0xFC05_C033 - DMA/Interrupt Request Select and Enable Register */
617// vudword pushr; /* 0xFC05_C034 -> 0xFC05_C037 - Push Tx FIFO Register */
618// vudword popr; /* 0xFC05_C038 -> 0xFC05_C03B - Pop Rx FIFO Register */
619// vudword txfr[16]; /* 0xFC05_C03C -> 0xFC05_C07B - Transmit FIFO Register 0-15 */
620// vudword rxfr[16]; /* 0xFC05_C07C -> 0xFC05_C0BB - Receive FIFO Register 0-15 */
621// } dspi0struct;
622
623/*
624 * UART MODULE 0-3 (uarts[4] = 0xFC06_0000 -> 0xFC06_FFFF)
625 */
626typedef struct
627{
628 vubyte umr; /* 0x0000 -> 0x0000 - UART Mode Registers */
629 vubyte pack00[3]; /* 0x0001 -> 0x0003 - RESERVED */
630 vubyte usr; /* 0x0004 -> 0x0004 - (Read) UART Status Register
631 (Write) UART Clock Select Register */
632 vubyte pack01[3]; /* 0x0005 -> 0x0007 - RESERVED */
633 vubyte ucr; /* 0x0008 -> 0x0008 - (Read) Do Not Access
634 (Write) UART Command Register */
635 vubyte pack02[3]; /* 0x0009 -> 0x000B - RESERVED */
636 vubyte utb; /* 0x000C -> 0x000C - (Read) UART Receive Buffer
637 (Write) UART Transmit Buffer */
638 vubyte pack03[3]; /* 0x000D -> 0x000F - RESERVED */
639 vubyte uipcr; /* 0x0010 -> 0x0010 - (Read) UART Input Port Change Register
640 (Write) UART Auxiliary Control Register */
641 vubyte pack04[3]; /* 0x0011 -> 0x0013 - RESERVED */
642 vubyte uisr; /* 0x0014 -> 0x0014 - (Read) UART Interrupt Status Register
643 (Write) UART Interrupt Mask Register */
644 vubyte pack05[3]; /* 0x0015 -> 0x0017 - RESERVED */
645 vubyte dur; /* 0x0018 -> 0x0018 - (Read) Do Not Access
646 (Write) UART Divider Upper Register */
647 vubyte pack06[3]; /* 0x0019 -> 0x001B - RESERVED */
648 vubyte dlr; /* 0x001C -> 0x001C - (Read) Do Not Access
649 (Write) UART Divider Lower Register */
650 vubyte pack07[23]; /* 0x001D -> 0x0033 - RESERVED */
651 vubyte uip; /* 0x0034 -> 0x0034 - (Read) UART Input Port Register
652 (Write) Do Not Access */
653 vubyte pack08[3]; /* 0x0035 -> 0x0037 - RESERVED */
654 vubyte ops; /* 0x0038 -> 0x0038 - (Read) Do Not Access
655 (Write) UART Output Port Bit Set Command Register */
656 vubyte pack09[3]; /* 0x0039 -> 0x003B - RESERVED */
657 vubyte opr; /* 0x003C -> 0x003C - (Read) Do Not Access
658 (Write) UART Output Port Bit Reset Command Register */
659 vubyte pack10[16323]; /* 0x003D -> 0x3FFF - RESERVED */
660} uartstruct;
661
662/*
663 * DMA TIMER MODULE 0-3 (timer[4] = 0xFC07_0000 -> 0xFC07_FFFF)
664 */
665typedef struct
666{
667 vuword tmr; /* 0x0000 -> 0x0001 - DMA Timer Mode Register */
668 vubyte txmr; /* 0x0002 -> 0x0002 - DMA Timer Extended Mode Register */
669 vubyte ter; /* 0x0003 -> 0x0003 - DMA Timer Event Register */
670 vudword trr; /* 0x0004 -> 0x0007 - DMA Timer Reference Register */
671 vudword tcr; /* 0x0008 -> 0x000B - DMA Timer Capture Register */
672 vudword tcn; /* 0x000C -> 0x000F - DMA Timer Counter Register */
673 vubyte pack00[16368]; /* 0x0010 -> 0x3FFF - RESERVED */
674} timerstruct;
675
676/*
677 * PROGRAMMABLE INTERRUPT TIMER MODULE 0-3 (pit[4] = 0xFC08_0000 -> 0xFC08_FFFF)
678 */
679typedef struct
680{
681 vuword pcsr; /* 0x0000 -> 0x0001 - PIT Control and Status Register */
682 vuword pmr; /* 0x0002 -> 0x0003 - PIT Modulus Register */
683 vuword pcntr; /* 0x0004 -> 0x0005 - PIT Count Register */
684 vubyte pack00[16378]; /* 0x0006 -> 0x3FFF - RESERVED */
685} pitstruct;
686
687/*
688 * EDGE PORT MODULE
689 */
690typedef struct
691{
692 vuword eppar; /* 0xFC09_0000 -> 0xFC09_0001 - EPORT Pin Assignment Register */
693 vubyte epddr; /* 0xFC09_0002 -> 0xFC09_0002 - EPORT Data Direction Register */
694 vubyte epier; /* 0xFC09_0003 -> 0xFC09_0003 - EPORT Interrupt Enable Register */
695 vubyte epdr; /* 0xFC09_0004 -> 0xFC09_0004 - EPORT Data Register */
696 vubyte eppdr; /* 0xFC09_0005 -> 0xFC09_0005 - EPORT Pin Data Register */
697 vubyte epfr; /* 0xFC09_0006 -> 0xFC09_0006 - EPORT Flag Register */
698 vubyte pack00; /* 0xFC09_0007 -> 0xFC09_0007 - RESERVED */
699} eportstruct;
700
701/*
702 * ANALOG-TO-DIGITAL CONVERTER
703 */
704typedef struct
705{
706 vuword cr1; /* 0xFC09_4000 -> 0xFC09_4001 - Control Register 1 */
707 vuword cr2; /* 0xFC09_4002 -> 0xFC09_4003 - Control Register 2 */
708 vuword zccr; /* 0xFC09_4004 -> 0xFC09_4005 - Zero Crossing Control Register */
709 vuword lst1; /* 0xFC09_4006 -> 0xFC09_4007 - Channel List Register 1 */
710 vuword lst2; /* 0xFC09_4008 -> 0xFC09_4009 - Channel List Register 2 */
711 vuword sdis; /* 0xFC09_400A -> 0xFC09_400B - Sample Disable Register */
712 vuword sr; /* 0xFC09_400C -> 0xFC09_400D - Status Register */
713 vuword lsr; /* 0xFC09_400E -> 0xFC09_400F - Limit Status Register */
714 vuword zcsr; /* 0xFC09_4010 -> 0xFC09_4011 - Zero Crossing Status Register */
715 vuword rslt[8]; /* 0xFC09_4012 -> 0xFC09_4021 - Result Register 0-7 */
716 vuword llmt[8]; /* 0xFC09_4022 -> 0xFC09_4031 - Low Limit Register 0-7 */
717 vuword hlmt[8]; /* 0xFC09_4032 -> 0xFC09_4041 - High Limit Register 0-7 */
718 vuword ofs[8]; /* 0xFC09_4042 -> 0xFC09_4051 - Offset Register 0-7 */
719 vuword pwr; /* 0xFC09_4052 -> 0xFC09_4053 - Power Control Register */
720 vuword cal; /* 0xFC09_4054 -> 0xFC09_4055 - Calibration Register */
721 vuword pwr2; /* 0xFC09_4056 -> 0xFC09_4057 - Power Control Register 2 */
722 vuword div; /* 0xFC09_4058 -> 0xFC09_4059 - Conversion Divisor Register */
723 vuword asdiv; /* 0xFC09_405A -> 0xFC09_405B - Auto-Standby Divisor Register */
724} adcstruct;
725
726/*
727 * DIGITAL-TO-ANALOG CONVERTER 0-1 (dac[2] = 0xFC09_8000 -> 0xFC09_FFFF)
728 */
729typedef struct
730{
731 vuword cr; /* 0x0000 -> 0x0001 - Control Register */
732 vuword data; /* 0x0002 -> 0x0003 - Buffered Data Register */
733 vuword step; /* 0x0004 -> 0x0005 - Step Size Register */
734 vuword min; /* 0x0006 -> 0x0007 - Minimum Value Register */
735 vuword max; /* 0x0008 -> 0x0009 - Maximum Value Register */
736 vuword sr; /* 0x000A -> 0x000B - Status Register */
737 vuword filtcnt; /* 0x000C -> 0x000D - Filter Count Register */
738 vubyte pack00[16370]; /* 0x000E -> 0x3FFF - RESERVED */
739} dacstruct;
740
741/*
742 * SERIAL BOOT FACILITY (SBF)
743 */
744typedef struct
745{
746 vuword sbfsr; /* 0xFC0A_0020 -> 0xFC0A_0021 - Serial Boot Facility Status Register */
747 vuword sbfcr; /* 0xFC0A_0022 -> 0xFC0A_0023 - Serial Boot Facility Control Register */
748} sbfstruct;
749
750/*
751 * REAL-TIME CLOCK
752 */
753typedef struct
754{
755 vuword yearmon; /* 0xFC0A_8000 -> 0xFC0A_8001 - Month and Year Counter Register */
756 vuword days; /* 0xFC0A_8002 -> 0xFC0A_8003 - Day and Day-of-Week Counter Register */
757 vuword hourmin; /* 0xFC0A_8004 -> 0xFC0A_8005 - Hour and Minute Counter Register */
758 vuword seconds; /* 0xFC0A_8006 -> 0xFC0A_8007 - Second Counter Register */
759 vuword alm_yrmon; /* 0xFC0A_8008 -> 0xFC0A_8009 - Year and Month Alarm Register */
760 vuword alm_days; /* 0xFC0A_800A -> 0xFC0A_800B - Day Alarm Register */
761 vuword alm_hm; /* 0xFC0A_800C -> 0xFC0A_800D - Hour and Minute Alarm Register */
762 vuword alm_sec; /* 0xFC0A_800E -> 0xFC0A_800F - Second Alarm Register */
763 vuword cr; /* 0xFC0A_8010 -> 0xFC0A_8011 - Control Register */
764 vuword sr; /* 0xFC0A_8012 -> 0xFC0A_8013 - Status Register */
765 vuword isr; /* 0xFC0A_8014 -> 0xFC0A_8015 - Interrupt Status Register */
766 vuword ier; /* 0xFC0A_8016 -> 0xFC0A_8017 - Interrupt Enable Register */
767 vuword count_dn; /* 0xFC0A_8018 -> 0xFC0A_8019 - Countdown Timer Register */
768 vubyte pack00[6]; /* 0xFC0A_801A -> 0xFC0A_8019 - RESERVED */
769 vuword cfg; /* 0xFC0A_8020 -> 0xFC0A_8021 - RTC config register */
770 vuword dst_hour; /* 0xFC0A_8022 -> 0xFC0A_8023 - Daylight Saving Time Hour Register */
771 vuword dst_mon; /* 0xFC0A_8024 -> 0xFC0A_8025 - Daylight Saving Time Month Register */
772 vuword dst_day; /* 0xFC0A_8026 -> 0xFC0A_8027 - Daylight Saving Time Day Register */
773 vuword compen; /* 0xFC0A_8028 -> 0xFC0A_8029 - Compensation Register */
774 vubyte pack01[8]; /* 0xFC0A_802A -> 0xFC0A_8031 - RESERVED */
775 vuword cntrh; /* 0xFC0A_8032 -> 0xFC0A_8033 - Count Up High Register */
776 vuword cntrl; /* 0xFC0A_8034 -> 0xFC0A_8035 - Count Up Low Register */
777 vubyte pack02[10]; /* 0xFC0A_8036 -> 0xFC0A_803F - RESERVED */
778 vudword stdbyram[512]; /* 0xFC0A_8040 -> 0xFC0A_883F - Standby RAM */
779} rtcstruct;
780
781/*
782 * SUBSCRIBER IDENTIFICATION MODULE
783 */
784typedef struct
785{
786 vudword cr1; /* 0xFC0A_C000 -> 0xFC0A_C003 - SIM Port 1 Control Register */
787 vudword setup; /* 0xFC0A_C004 -> 0xFC0A_C007 - SIM Setup Register */
788 vudword detect1; /* 0xFC0A_C008 -> 0xFC0A_C00B - SIM Port 1 Detect Register */
789 vudword tbuf1; /* 0xFC0A_C00C -> 0xFC0A_C00F - SIM Port 1 Transmit Buffer Register */
790 vudword rbuf1; /* 0xFC0A_C010 -> 0xFC0A_C013 - SIM Port 1 Receive Buffer Register */
791 vudword cr0; /* 0xFC0A_C014 -> 0xFC0A_C017 - SIM Port 0 Control Register */
792 vudword cr; /* 0xFC0A_C018 -> 0xFC0A_C01B - SIM Control Register */
793 vudword pre; /* 0xFC0A_C01C -> 0xFC0A_C01F - SIM Clock Prescaler Register */
794 vudword rthr; /* 0xFC0A_C020 -> 0xFC0A_C023 - SIM Receive Threshold Register */
795 vudword en; /* 0xFC0A_C024 -> 0xFC0A_C027 - SIM Enable Register */
796 vudword tsr; /* 0xFC0A_C028 -> 0xFC0A_C02B - SIM Transmit Status Register */
797 vudword rsr; /* 0xFC0A_C02C -> 0xFC0A_C02F - SIM Receive Status Register */
798 vudword imr; /* 0xFC0A_C030 -> 0xFC0A_C033 - SIM Interrupt Mask Register */
799 vudword tbuf0; /* 0xFC0A_C034 -> 0xFC0A_C037 - SIM Port 0 Transmit Buffer Register */
800 vudword rbuf0; /* 0xFC0A_C038 -> 0xFC0A_C03B - SIM Port 0 Receive Buffer Reigster */
801 vudword detect0; /* 0xFC0A_C03C -> 0xFC0A_C03F - SIM Port 0 Detect Register */
802 vudword format0; /* 0xFC0A_C040 -> 0xFC0A_C043 - SIM Data Format Register */
803 vudword tthr; /* 0xFC0A_C044 -> 0xFC0A_C047 - SIM Transmit Threshold Register */
804 vudword tgcr; /* 0xFC0A_C048 -> 0xFC0A_C04B - SIM Transmit Guard Control Register */
805 vudword odcr; /* 0xFC0A_C04C -> 0xFC0A_C04F - SIM Open Drain Configuration Control Register */
806 vudword rcr; /* 0xFC0A_C050 -> 0xFC0A_C053 - SIM Reset Control Register */
807 vudword cwtr; /* 0xFC0A_C054 -> 0xFC0A_C057 - SIM Character Wait Time Register */
808 vudword gpcnt; /* 0xFC0A_C058 -> 0xFC0A_C05B - SIM General Purpose Counter Register */
809 vudword div; /* 0xFC0A_C05C -> 0xFC0A_C05F - SIM Divisor Register */
810 vudword bwt; /* 0xFC0A_C060 -> 0xFC0A_C063 - SIM Block Wait Time Register */
811 vudword bgt; /* 0xFC0A_C064 -> 0xFC0A_C067 - SIM Block Guard Time Register */
812 vudword bwth; /* 0xFC0A_C068 -> 0xFC0A_C06B - SIM Block Wait Time Register High */
813 vudword tfsr; /* 0xFC0A_C06C -> 0xFC0A_C06F - SIM Transmit FIFO Status Register */
814 vudword rfcr; /* 0xFC0A_C070 -> 0xFC0A_C073 - SIM Receive FIFO Counter Register */
815 vudword rfwp; /* 0xFC0A_C074 -> 0xFC0A_C077 - SIM Receive FIFO Write Pointer Register */
816 vudword rfrp; /* 0xFC0A_C078 -> 0xFC0A_C07B - SIM Receive FIFO Read Pointer Register */
817} simstruct;
818
819/*
820 * USB ON-THE-GO
821 */
822typedef struct
823{
824 vudword id; /* 0xFC0B_0000 -> 0xFC0B_0003 - Identification Register */
825 vudword hwgeneral; /* 0xFC0B_0004 -> 0xFC0B_0007 - General Hardware Parameters */
826 vudword hwhost; /* 0xFC0B_0008 -> 0xFC0B_000B - Host Hardware Parameters */
827 vudword hwdevice; /* 0xFC0B_000C -> 0xFC0B_000F - Device Hardware Parameters */
828 vudword hwtxbuf; /* 0xFC0B_0010 -> 0xFC0B_0013 - Tx Buffer Hardware Parameters */
829 vudword hwrxbuf; /* 0xFC0B_0014 -> 0xFC0B_0017 - Rx Buffer Hardware Parameters */
830 vubyte pack00[104]; /* 0xFC0B_0018 -> 0xFC0B_007F - RESERVED */
831 vudword gptimer0ld; /* 0xFC0B_0080 -> 0xFC0B_0083 - General Purpose Timer 0 Load */
832 vudword gptimer0ctl; /* 0xFC0B_0084 -> 0xFC0B_0087 - General Purpose Timer 0 Control */
833 vudword gptimer1ld; /* 0xFC0B_0088 -> 0xFC0B_008B - General Purpose Timer 1 Load */
834 vudword gptimer1ctl; /* 0xFC0B_008C -> 0xFC0B_008F - General Purpose Timer 1 Control */
835 vubyte pack01[112]; /* 0xFC0B_0090 -> 0xFC0B_00FF - RESERVED */
836 vuword hciversion; /* 0xFC0B_0100 -> 0xFC0B_0101 - Host Interface Version Number */
837 vubyte pack02; /* 0xFC0B_0102 -> 0xFC0B_0102 - RESERVED */
838 vubyte caplength; /* 0xFC0B_0103 -> 0xFC0B_0103 - Capability Register Length */
839 vudword hcsparams; /* 0xFC0B_0104 -> 0xFC0B_0107 - Host Structural Parameters */
840 vudword hccparams; /* 0xFC0B_0108 -> 0xFC0B_010B - Host Capability Parameters */
841 vubyte pack03[22]; /* 0xFC0B_010C -> 0xFC0B_0121 - RESERVED */
842 vuword dciversion; /* 0xFC0B_0122 -> 0xFC0B_0123 - Device Interface Version Number */
843 vudword dccparams; /* 0xFC0B_0124 -> 0xFC0B_0127 - Device Capability Parameters */
844 vubyte pack04[24]; /* 0xFC0B_0128 -> 0xFC0B_013F - RESERVED */
845 vudword usbcmd; /* 0xFC0B_0140 -> 0xFC0B_0143 - USB Command */
846 vudword usbsts; /* 0xFC0B_0144 -> 0xFC0B_0147 - USB Status */
847 vudword usbintr; /* 0xFC0B_0148 -> 0xFC0B_014B - USB Interrupt Enable */
848 vudword frindex; /* 0xFC0B_014C -> 0xFC0B_014F - USB Frame Index */
849 vubyte pack05[4]; /* 0xFC0B_0150 -> 0xFC0B_0153 - RESERVED */
850 vudword periodiclstbase; /* 0xFC0B_0154 -> 0xFC0B_0157 - (Host Mode) Periodic Frame List Base Address
851 - (Device Mode) Device Address */
852 vudword asynclistaddr; /* 0xFC0B_0158 -> 0xFC0B_015B - (Host Mode) Current Asynchronous List Address
853 - (Device Mode) Address at Endpoint List */
854 vudword ttctrl; /* 0xFC0B_015C -> 0xFC0B_015F - Host TT Asynchronous Buffer Control */
855 vudword burstsize; /* 0xFC0B_0160 -> 0xFC0B_0163 - Master Interface Data Burst Size */
856 vudword txfilltuning; /* 0xFC0B_0164 -> 0xFC0B_0167 - Host Transmit FIFO Tuning Control */
857 vubyte pack06[8]; /* 0xFC0B_0168 -> 0xFC0B_016F - RESERVED */
858 vudword ulpi_viewport; /* 0xFC0B_0170 -> 0xFC0B_0173 - ULPI Register Access */
859 vubyte pack07[12]; /* 0xFC0B_0174 -> 0xFC0B_017F - RESERVED */
860 vudword configflag; /* 0xFC0B_0180 -> 0xFC0B_0183 - Configure Flag Register */
861 vudword portsc1; /* 0xFC0B_0184 -> 0xFC0B_0187 - Port Status/Control */
862 vubyte pack08[28]; /* 0xFC0B_0188 -> 0xFC0B_01A3 - RESERVED */
863 vudword otgsc; /* 0xFC0B_01A4 -> 0xFC0B_01A7 - On-the-Go Status and Control */
864 vudword mode; /* 0xFC0B_01A8 -> 0xFC0B_01AB - USB Mode Register */
865 vudword epsetupsr; /* 0xFC0B_01AC -> 0xFC0B_01AF - Endpoint Setup Status Register */
866 vudword epprime; /* 0xFC0B_01B0 -> 0xFC0B_01B3 - Endpoint Initialization */
867 vudword epflush; /* 0xFC0B_01B4 -> 0xFC0B_01B7 - Endpoint De-initialize */
868 vudword epsr; /* 0xFC0B_01B8 -> 0xFC0B_01BB - Endpoint Status Register */
869 vudword epcomplete; /* 0xFC0B_01BC -> 0xFC0B_01BF - Endpoint Complete */
870 vudword epcr0; /* 0xFC0B_01C0 -> 0xFC0B_01C3 - Endpoint Control Register 0 */
871 vudword epcr1; /* 0xFC0B_01C4 -> 0xFC0B_01C7 - Endpoint Control Register 1 */
872 vudword epcr2; /* 0xFC0B_01C8 -> 0xFC0B_01CB - Endpoint Control Register 2 */
873 vudword epcr3; /* 0xFC0B_01CC -> 0xFC0B_01CF - Endpoint Control Register 3 */
874} usb_otgstruct;
875
876/*
877 * USB HOST CONTROLLER
878 */
879typedef struct
880{
881 vudword id; /* 0xFC0B_4000 -> 0xFC0B_4003 - Identification Register */
882 vudword hwgeneral; /* 0xFC0B_4004 -> 0xFC0B_4007 - General Hardware Parameters */
883 vudword hwhost; /* 0xFC0B_4008 -> 0xFC0B_400B - Host Hardware Parameters */
884 vubyte pack00[4]; /* 0xFC0B_400C -> 0xFC0B_400F - RESERVED */
885 vudword hwtxbuf; /* 0xFC0B_4010 -> 0xFC0B_4013 - Tx Buffer Hardware Parameters */
886 vudword hwrxbuf; /* 0xFC0B_4014 -> 0xFC0B_4017 - Rx Buffer Hardware Parameters */
887 vubyte pack01[232]; /* 0xFC0B_4018 -> 0xFC0B_40FF - RESERVED */
888 vuword hciversion; /* 0xFC0B_4100 -> 0xFC0B_4101 - Host Interface Version Number */
889 vubyte pack02; /* 0xFC0B_4102 -> 0xFC0B_4102 - RESERVED */
890 vubyte caplength; /* 0xFC0B_4103 -> 0xFC0B_4103 - Capability Register Length */
891 vudword hcsparams; /* 0xFC0B_4104 -> 0xFC0B_4107 - Host Structural Parameters */
892 vudword hccparams; /* 0xFC0B_4108 -> 0xFC0B_410B - Host Capability Parameters */
893 vubyte pack03[52]; /* 0xFC0B_410C -> 0xFC0B_413F - RESERVED */
894 vudword usbcmd; /* 0xFC0B_4140 -> 0xFC0B_4143 - USB Command */
895 vudword usbsts; /* 0xFC0B_4144 -> 0xFC0B_4147 - USB Status */
896 vudword usbintr; /* 0xFC0B_4148 -> 0xFC0B_414B - USB Interrupt Enable */
897 vudword frindex; /* 0xFC0B_414C -> 0xFC0B_414F - USB Frame Index */
898 vubyte pack04[4]; /* 0xFC0B_4150 -> 0xFC0B_4153 - RESERVED */
899 vudword periodiclstbase; /* 0xFC0B_4154 -> 0xFC0B_4157 - Periodic Frame List Base Address */
900 vudword asynclistaddr; /* 0xFC0B_4158 -> 0xFC0B_415B - Current Asynchronous List Address */
901 vudword ttctrl; /* 0xFC0B_415C -> 0xFC0B_415F - Host TT Asynchronous Buffer Control */
902 vudword burstsize; /* 0xFC0B_4160 -> 0xFC0B_4163 - Master Interface Data Burst Size */
903 vudword txfilltuning; /* 0xFC0B_4164 -> 0xFC0B_4167 - Host Transmit FIFO Tuning Control */
904 vubyte pack05[24]; /* 0xFC0B_4168 -> 0xFC0B_417F - RESERVED */
905 vudword configflag; /* 0xFC0B_4180 -> 0xFC0B_4183 - Configure Flag Register */
906 vudword portsc1; /* 0xFC0B_4184 -> 0xFC0B_4187 - Port Status/Control */
907 vubyte pack06[32]; /* 0xFC0B_4188 -> 0xFC0B_41A7 - RESERVED */
908 vudword mode; /* 0xFC0B_41A8 -> 0xFC0B_41AB - USB Mode Register */
909} usb_hoststruct;
910
911/*
912 * DDR1/2 SDRAM MEMORY CONTROLLER
913 */
914typedef struct
915{
916 vudword cr[64]; /* 0xFC0B_8000 -> 0xFC0B_80FF - Control Register 0-63 (46-52, 54, 61-63 reserved) */
917 vubyte pack00[172]; /* 0xFC0B_8100 -> 0xFC0B_81AB - RESERVED */
918 vudword padcr; /* 0xFC0B_81AC -> 0xFC0B_81AF - I/O Pad Control Register */
919} ddrmcstruct;
920
921/*
922 * SYNCHRONOUS SERIAL INTERFACE 0
923 */
924typedef struct
925{
926 vudword tx0; /* 0xFC0B_C000 -> 0xFC0B_C003 - Transmit Data Register 0 */
927 vudword tx1; /* 0xFC0B_C004 -> 0xFC0B_C007 - Transmit Data Register 1 */
928 vudword rx0; /* 0xFC0B_C008 -> 0xFC0B_C00B - Receive Data Register 0 */
929 vudword rx1; /* 0xFC0B_C00C -> 0xFC0B_C00F - Receive Data Register 1 */
930 vudword cr; /* 0xFC0B_C010 -> 0xFC0B_C013 - Control Register */
931 vudword isr; /* 0xFC0B_C014 -> 0xFC0B_C017 - Interrupt Status Register */
932 vudword ier; /* 0xFC0B_C018 -> 0xFC0B_C01B - Interrupt Enable Register */
933 vudword tcr; /* 0xFC0B_C01C -> 0xFC0B_C01F - Transmit Configuration Register */
934 vudword rcr; /* 0xFC0B_C020 -> 0xFC0B_C023 - Receive Configuration Register */
935 vudword ccr; /* 0xFC0B_C024 -> 0xFC0B_C027 - Clock Control Register */
936 vubyte pack00[4]; /* 0xFC0B_C028 -> 0xFC0B_C02B - RESERVED */
937 vudword fcsr; /* 0xFC0B_C02C -> 0xFC0B_C02F - FIFO Control/Status Register */
938 vubyte pack01[8]; /* 0xFC0B_C030 -> 0xFC0B_C037 - RESERVED */
939 vudword acr; /* 0xFC0B_C038 -> 0xFC0B_C03B - AC97 Control Register */
940 vudword acadd; /* 0xFC0B_C03C -> 0xFC0B_C03F - AC97 Command Address Register */
941 vudword acdat; /* 0xFC0B_C040 -> 0xFC0B_C043 - AC97 Command Data Register */
942 vudword atag; /* 0xFC0B_C044 -> 0xFC0B_C047 - AC97 Tag Register */
943 vudword tmask; /* 0xFC0B_C048 -> 0xFC0B_C04B - Transmit Time Slot Mask Register */
944 vudword rmask; /* 0xFC0B_C04C -> 0xFC0B_C04F - Receive Time Slot Mask Register */
945 vudword accsr; /* 0xFC0B_C050 -> 0xFC0B_C053 - AC97 Channel Status Register */
946 vudword accen; /* 0xFC0B_C054 -> 0xFC0B_C057 - AC97 Channel Enable Register */
947 vudword accdis; /* 0xFC0B_C058 -> 0xFC0B_C05B - AC97 Channel Disable Register */
948} ssi0struct;
949
950/*
951 * CLOCK MODULE (PHASE-LOCKED LOOP)
952 */
953typedef struct
954{
955 vudword pll_cr; /* 0xFC0C_0000 -> 0xFC0C_0003 - PLL Control Register */
956 vudword pll_dr; /* 0xFC0C_0004 -> 0xFC0C_0007 - PLL Divider Register */
957 vudword pll_sr; /* 0xFC0C_0008 -> 0xFC0C_000B - PLL Status Register */
958} clockstruct;
959
960/*
961 * RANDOM NUMBER GENERATOR
962 */
963typedef struct
964{
965 vudword ver; /* 0xFC0C_4000 -> 0xFC0C_4003 - Version ID Register */
966 vudword cmd; /* 0xFC0C_4004 -> 0xFC0C_4007 - Command Register */
967 vudword cr; /* 0xFC0C_4008 -> 0xFC0C_400B - Control Register */
968 vudword sr; /* 0xFC0C_400C -> 0xFC0C_400F - Status Register */
969 vudword esr; /* 0xFC0C_4010 -> 0xFC0C_4013 - Error Status Register */
970 vudword out; /* 0xFC0C_4014 -> 0xFC0C_4017 - Output FIFO */
971 vudword er; /* 0xFC0C_4018 -> 0xFC0C_401B - Entropy Register */
972} rngstruct;
973
974/*
975 * SYNCHRONOUS SERIAL INTERFACE 1
976 */
977typedef struct
978{
979 vudword tx0; /* 0xFC0C_8000 -> 0xFC0C_8003 - Transmit Data Register 0 */
980 vudword tx1; /* 0xFC0C_8004 -> 0xFC0C_8007 - Transmit Data Register 1 */
981 vudword rx0; /* 0xFC0C_8008 -> 0xFC0C_800B - Receive Data Register 0 */
982 vudword rx1; /* 0xFC0C_800C -> 0xFC0C_800F - Receive Data Register 1 */
983 vudword cr; /* 0xFC0C_8010 -> 0xFC0C_8013 - Control Register */
984 vudword isr; /* 0xFC0C_8014 -> 0xFC0C_8017 - Interrupt Status Register */
985 vudword ier; /* 0xFC0C_8018 -> 0xFC0C_801B - Interrupt Enable Register */
986 vudword tcr; /* 0xFC0C_801C -> 0xFC0C_801F - Transmit Configuration Register */
987 vudword rcr; /* 0xFC0C_8020 -> 0xFC0C_8023 - Receive Configuration Register */
988 vudword ccr; /* 0xFC0C_8024 -> 0xFC0C_8027 - Clock Control Register */
989 vubyte pack00[4]; /* 0xFC0C_8028 -> 0xFC0C_802B - RESERVED */
990 vudword fcsr; /* 0xFC0C_802C -> 0xFC0C_802F - FIFO Control/Status Register */
991 vubyte pack01[8]; /* 0xFC0C_8030 -> 0xFC0C_8037 - RESERVED */
992 vudword acr; /* 0xFC0C_8038 -> 0xFC0C_803B - AC97 Control Register */
993 vudword acadd; /* 0xFC0C_803C -> 0xFC0C_803F - AC97 Command Address Register */
994 vudword acdat; /* 0xFC0C_8040 -> 0xFC0C_8043 - AC97 Command Data Register */
995 vudword atag; /* 0xFC0C_8044 -> 0xFC0C_8047 - AC97 Tag Register */
996 vudword tmask; /* 0xFC0C_8048 -> 0xFC0C_804B - Transmit Time Slot Mask Register */
997 vudword rmask; /* 0xFC0C_804C -> 0xFC0C_804F - Receive Time Slot Mask Register */
998 vudword accsr; /* 0xFC0C_8050 -> 0xFC0C_8053 - AC97 Channel Status Register */
999 vudword accen; /* 0xFC0C_8054 -> 0xFC0C_8057 - AC97 Channel Enable Register */
1000 vudword accdis; /* 0xFC0C_8058 -> 0xFC0C_805B - AC97 Channel Disable Register */
1001} ssi1struct;
1002
1003/*
1004 * ENHANCED SECURE DIGITAL HOST CONTROLLER
1005 */
1006typedef struct
1007{
1008 vudword dsaddr; /* 0xFC0C_C000 -> 0xFC0C_C003 - DMA System Address */
1009 vudword blkattr; /* 0xFC0C_C004 -> 0xFC0C_C007 - Block Attributes */
1010 vudword cmdarg; /* 0xFC0C_C008 -> 0xFC0C_C00B - Command Argument */
1011 vudword xfertyp; /* 0xFC0C_C00C -> 0xFC0C_C00F - Command Transfer Type */
1012 vudword cmdrsp0; /* 0xFC0C_C010 -> 0xFC0C_C013 - Command Response 0 */
1013 vudword cmdrsp1; /* 0xFC0C_C014 -> 0xFC0C_C017 - Command Response 1 */
1014 vudword cmdrsp2; /* 0xFC0C_C018 -> 0xFC0C_C01B - Command Response 2 */
1015 vudword cmdrsp3; /* 0xFC0C_C01C -> 0xFC0C_C01F - Command Response 3 */
1016 vudword datport; /* 0xFC0C_C020 -> 0xFC0C_C023 - Data Buffer Access Port */
1017 vudword prsstat; /* 0xFC0C_C024 -> 0xFC0C_C027 - Present State */
1018 vudword proctl; /* 0xFC0C_C028 -> 0xFC0C_C02B - Protocol Control */
1019 vudword sysctl; /* 0xFC0C_C02C -> 0xFC0C_C02F - System Control */
1020 vudword irqstat; /* 0xFC0C_C030 -> 0xFC0C_C033 - Interrupt Status */
1021 vudword irqstaten; /* 0xFC0C_C034 -> 0xFC0C_C037 - Interrupt Status Enable */
1022 vudword irqsigen; /* 0xFC0C_C038 -> 0xFC0C_C03B - Interrupt Signal Enable */
1023 vudword autoc12err; /* 0xFC0C_C03C -> 0xFC0C_C03F - Auto CMD12 Status */
1024 vudword hostcapblt; /* 0xFC0C_C040 -> 0xFC0C_C043 - Host Controller Capabilities */
1025 vudword wml; /* 0xFC0C_C044 -> 0xFC0C_C047 - Watermark Level */
1026 vubyte pack00[8]; /* 0xFC0C_C048 -> 0xFC0C_C04F - RESERVERED */
1027 vudword fevt; /* 0xFC0C_C050 -> 0xFC0C_C053 - Force Event */
1028 vudword admaesr; /* 0xFC0C_C054 -> 0xFC0C_C057 - ADMA Error Status */
1029 vudword admasar; /* 0xFC0C_C058 -> 0xFC0C_C05B - ADMA System Address */
1030 vubyte pack01[160]; /* 0xFC0C_C05C -> 0xFC0C_C0FB - RESERVED */
1031 vudword hostver; /* 0xFC0C_C0FC -> 0xFC0C_C0FF - Host Controller Version */
1032} sdhcstruct;
1033
1034/*
1035 * MIB COUNTER BLOCK RMON TRANSMIT
1036 */
1037typedef struct
1038{
1039 vudword drop; /* 0x00 -> 0x03 - Count of Frames Not Counted Correctly (Not Implemented) */
1040 vudword packets; /* 0x04 -> 0x07 - RMON Tx Packet Count */
1041 vudword bc_pkt; /* 0x08 -> 0x0B - RMON Tx Broadcast Packets */
1042 vudword mc_pkt; /* 0x0C -> 0x0F - RMON Tx Multicast Packets */
1043 vudword crc_align; /* 0x10 -> 0x13 - RMON Tx Packets with CRC/Align Error */
1044 vudword undersize; /* 0x14 -> 0x17 - RMON Tx Packets < 64 Bytes, Good CRC */
1045 vudword oversize; /* 0x18 -> 0x1B - RMON Tx Packets > MAX_FL Bytes, Good CRC */
1046 vudword frag; /* 0x1C -> 0x1F - RMON Tx Packets < 64 Bytes, Bad CRC */
1047 vudword jab; /* 0x20 -> 0x23 - RMON Tx Packets > MAX_FL Bytes, Bad CRC */
1048 vudword col; /* 0x24 -> 0x27 - RMON Tx Collision Count */
1049 vudword p64; /* 0x28 -> 0x2B - RMON Tx 64 Byte Packets */
1050 vudword p65to127; /* 0x2C -> 0x2F - RMON Tx 65 to 127 Byte Packets */
1051 vudword p128to255; /* 0x30 -> 0x33 - RMON Tx 128 to 255 Byte Packets */
1052 vudword p256to511; /* 0x34 -> 0x37 - RMON Tx 256 to 511 Byte Packets */
1053 vudword p512to1023; /* 0x38 -> 0x3B - RMON Tx 512 to 1023 Byte Packets */
1054 vudword p1024to2047; /* 0x3C -> 0x3F - RMON Tx 1024 to 2047 Byte Packets */
1055 vudword p_gte2048; /* 0x40 -> 0x43 - RMON Tx Packets with > 2048 Bytes */
1056 vudword octets; /* 0x44 -> 0x47 - RMON Tx Octets */
1057} rmon_tstruct;
1058
1059/*
1060 * MIB COUNTER BLOCK IEEE TRANSMIT
1061 */
1062typedef struct
1063{
1064 vudword drop; /* 0x00 -> 0x03 - Count of Frames Not Counted Correctly (Not Implemented) */
1065 vudword frame_ok; /* 0x04 -> 0x07 - Frames Transmitted OK */
1066 vudword scol; /* 0x08 -> 0x0B - Frames Transmitted with Single Collision */
1067 vudword mcol; /* 0x0C -> 0x0F - Frames Transmitted with Multiple Collisions */
1068 vudword def; /* 0x10 -> 0x13 - Frames Transmitted after Deferral Delay */
1069 vudword lcol; /* 0x14 -> 0x17 - Frames Transmitted with Late Collision */
1070 vudword excol; /* 0x18 -> 0x1B - Frames Transmitted with Excessive Collisions */
1071 vudword macerr; /* 0x1C -> 0x1F - Frames Transmitted with Tx FIFO Underrun */
1072 vudword cserr; /* 0x20 -> 0x23 - Frames Transmitted with Carrier Sense Error */
1073 vudword sqe; /* 0x24 -> 0x27 - Frames Transmitted with SQE Error (Not Implemented) */
1074 vudword fdxfc; /* 0x28 -> 0x2B - Flow Control Pause Frames Transmitted */
1075 vudword octets_ok; /* 0x2C -> 0x2F - Octet Count for Frames Transmitted without Error */
1076} ieee_tstruct;
1077
1078/*
1079 * MIB COUNTER BLOCK RMON RECEIVE
1080 */
1081typedef struct
1082{
1083 vubyte pack00[4]; /* 0x00 -> 0x03 - RESERVED */
1084 vudword packets; /* 0x04 -> 0x07 - RMON Rx Packet Count */
1085 vudword bc_pkt; /* 0x08 -> 0x0B - RMON Rx Broadcast Packets */
1086 vudword mc_pkt; /* 0x0C -> 0x0F - RMON Rx Multicast Packets */
1087 vudword crc_align; /* 0x10 -> 0x13 - RMON Rx Packets with CRC/Align Error */
1088 vudword undersize; /* 0x14 -> 0x17 - RMON Rx Packets < 64 Bytes, Good CRC */
1089 vudword oversize; /* 0x18 -> 0x1B - RMON Rx > MAX_FL Bytes, Good CRC */
1090 vudword frag; /* 0x1C -> 0x1F - RMON Rx packets < 64 Bytes, Bad CRC */
1091 vudword jab; /* 0x20 -> 0x23 - RMON Rx Packets > MAX_FL Bytes, Bad CRC */
1092 vudword resvd_0; /* 0x24 -> 0x27 - RESERVED */
1093 vudword p64; /* 0x28 -> 0x2B - RMON Rx 64 Byte Packets */
1094 vudword p65to127; /* 0x2C -> 0x2F - RMON Rx 65 to 127 Byte Packets */
1095 vudword p128to255; /* 0x30 -> 0x33 - RMON Rx 128 to 255 Byte Packets */
1096 vudword p256to511; /* 0x34 -> 0x37 - RMON Rx 256 to 511 Byte Packets */
1097 vudword p512to1023; /* 0x38 -> 0x3B - RMON Rx 512 to 1023 Byte Packets */
1098 vudword p1024to2047; /* 0x3C -> 0x3F - RMON Rx 1024 to 2047 Byte Packets */
1099 vudword p_gte2048; /* 0x40 -> 0x43 - RMON Rx Packets with > 2048 Bytes */
1100 vudword octets; /* 0x44 -> 0x47 - RMON Rx Octets */
1101} rmon_rstruct;
1102
1103/*
1104 * MIB COUNTER BLOCK IEEE RECEIVE
1105 */
1106typedef struct
1107{
1108 vudword drop; /* 0x00 -> 0x03 - Count of Frames Not Counted Correctly */
1109 vudword frame_ok; /* 0x04 -> 0x07 - Frames Received OK */
1110 vudword crc; /* 0x08 -> 0x0B - Frames Received with CRC Error */
1111 vudword align; /* 0x0C -> 0x0F - Frames Received with Alignment Error */
1112 vudword macerr; /* 0x10 -> 0x13 - Receive FIFO Overflow Count */
1113 vudword fdxfc; /* 0x14 -> 0x17 - Flow Control Pause Frames Received */
1114 vudword octets_ok; /* 0x18 -> 0x1B - Octet Count for Frames Received without Error */
1115} ieee_rstruct;
1116
1117/*
1118 * 10/100 MBPS ETHERNET MAC-NET CORE 0-1 (fec[2] = 0xFC0D_4000 -> 0xFC0D_BFFF)
1119 */
1120typedef struct
1121{
1122 vudword l;
1123 vudword u;
1124} sumac;
1125typedef struct
1126{
1127 vubyte pack00[4]; /* 0x4000 -> 0x4003 - RESERVED */
1128 vudword eir; /* 0x4004 -> 0x4007 - Interrupt Event Register */
1129 vudword eimr; /* 0x4008 -> 0x400B - Interrupt Mask Register */
1130 vubyte pack01[4]; /* 0x400C -> 0x400F - RESERVED */
1131 vudword rdar; /* 0x4010 -> 0x4013 - Receive Descriptor Active Register */
1132 vudword tdar; /* 0x4014 -> 0x4017 - Transmit Descriptor Active Register */
1133 vubyte pack02[12]; /* 0x4018 -> 0x4023 - RESERVED */
1134 vudword ecr; /* 0x4024 -> 0x4027 - Ethernet Control Register */
1135 vubyte pack03[24]; /* 0x4028 -> 0x403F - RESERVED */
1136 vudword mdata; /* 0x4040 -> 0x4043 - MII Data Register (MII Management Frame Register) */
1137 vudword mscr; /* 0x4044 -> 0x4047 - MII Speed Control Register */
1138 vubyte pack04[28]; /* 0x4048 -> 0x4063 - RESERVED */
1139 vudword mibc; /* 0x4064 -> 0x4067 - MIB Control/Status Register */
1140 vubyte pack05[28]; /* 0x4068 -> 0x4083 - RESERVED */
1141 vudword rcr; /* 0x4084 -> 0x4087 - Receive Control Register */
1142 vubyte pack06[60]; /* 0x4088 -> 0x40C3 - RESERVED */
1143 vudword tcr; /* 0x40C4 -> 0x40C7 - Transmit Control Register */
1144 vubyte pack07[28]; /* 0x40C8 -> 0x40E3 - RESERVED */
1145 vudword palr; /* 0x40E4 -> 0x40E7 - Physical Address Low Register */
1146 vudword paur; /* 0x40E8 -> 0x40EB - Physical Address High Register */
1147 vudword opd; /* 0x40EC -> 0x40EF - Opcode/Pause Duration Register */
1148 vubyte pack08[40]; /* 0x40F0 -> 0x4117 - RESERVED */
1149 vudword iaur; /* 0x4118 -> 0x411B - Descriptor Individual Upper Address Register */
1150 vudword ialr; /* 0x411C -> 0x411F - Descriptor Individual Lower Address Register */
1151 vudword gaur; /* 0x4120 -> 0x4123 - Descriptor Group Upper Address Register */
1152 vudword galr; /* 0x4124 -> 0x4127 - Descriptor Group Lower Address Register */
1153 vubyte pack09[28]; /* 0x4128 -> 0x4143 - RESERVED */
1154 vudword tfwr; /* 0x4144 -> 0x4147 - Transmit FIFO Watermark and Store/Foward Control */
1155 vubyte pack10[4]; /* 0x4148 -> 0x414B - RESERVED */
1156 vudword frbr; /* 0x414C -> 0x414F - FIFO Receive Bound Register (Not Implemented) */
1157 vudword frsr; /* 0x4150 -> 0x4153 - FIFO Receive Start Register (Not Implemented) */
1158 vubyte pack11[44]; /* 0x4154 -> 0x417F - RESERVED */
1159 vudword erdsr; /* 0x4180 -> 0x4183 - Receive Descriptor Ring Start Register */
1160 vudword etdsr; /* 0x4184 -> 0x4187 - Transmit Descriptor Ring Start Register */
1161 vudword emrbr; /* 0x4188 -> 0x418B - Maximum Receive Buffer Size */
1162 vubyte pack12[4]; /* 0x418C -> 0x418F - RESERVED */
1163 vudword rsfl; /* 0x4190 -> 0x4193 - Receive FIFO Section Full Threshold */
1164 vudword rsem; /* 0x4194 -> 0x4197 - Receive FIFO Section Empty Threshold */
1165 vudword raem; /* 0x4198 -> 0x419B - Receive FIFO Almost Empty Threshold */
1166 vudword rafl; /* 0x419C -> 0x419F - Receive FIFO Almost Full Threshold */
1167 vudword tsem; /* 0x41A0 -> 0x41A3 - Transmit FIFO Section Empty Threshold */
1168 vudword taem; /* 0x41A4 -> 0x41A7 - Transmit FIFO Almost Empty Threshold */
1169 vudword tafl; /* 0x41A8 -> 0x41AB - Transmit FIFO Almost Full Threshold */
1170 vudword tipg; /* 0x41AC -> 0x41AF - Transmit Inter-Packet Gap */
1171 vudword ftrl; /* 0x41B0 -> 0x41B3 - Frame Truncation Length */
1172 vubyte pack13[12]; /* 0x41B4 -> 0x41BF - RESERVED */
1173 vudword tacc; /* 0x41C0 -> 0x41C3 - Transmit Accelerator Function Configuration */
1174 vudword racc; /* 0x41C4 -> 0x41C7 - Receive Accelerator Function Configuration */
1175 vubyte pack14[56]; /* 0x41C8 -> 0x41FF - RESERVED */
1176 rmon_tstruct fec_rmon_t; /* 0x4200 -> 0x4247 - MIB Counter Block RMON Transmit */
1177 ieee_tstruct fec_ieee_t; /* 0x4248 -> 0x4277 - MIB Counter Block IEEE Transmit */
1178 vubyte pack15[8]; /* 0x4278 -> 0x427F - RESERVED */
1179 rmon_rstruct fec_rmon_r; /* 0x4280 -> 0x42C7 - MIB Counter Block RMON Receive */
1180 ieee_rstruct fec_ieee_r; /* 0x42C8 -> 0x42E3 - MIB Counter Block IEEE Receive */
1181 vubyte pack16[284]; /* 0x42E4 -> 0x43FF - RESERVED */
1182 vudword atcr; /* 0x4400 -> 0x4403 - Timer Control Register */
1183 vudword atvr; /* 0x4404 -> 0x4407 - Timer Value Register */
1184 vudword atoff; /* 0x4408 -> 0x440B - Offset Value for One-Shot Event Generation */
1185 vudword atper; /* 0x440C -> 0x440F - Timer Period */
1186 vudword atcor; /* 0x4410 -> 0x4413 - Correction Counter Wrap-Around Value */
1187 vudword atinc; /* 0x4414 -> 0x4417 - Timestamp Clock Period and Correction Increment */
1188 vudword atstmp; /* 0x4418 -> 0x441B - Timestamp of Last Transmitted Frame */
1189 vubyte pack17[228]; /* 0x441C -> 0x44FF - RESERVED */
1190 volatile sumac smac[4]; /* 0x4500 -> 0x451F - Supplemental MAC Address 0-3 */
1191 vubyte pack18[15072]; /* 0x4520 -> 0x7FFF - RESERVED */
1192} fecstruct;
1193
1194typedef struct
1195{
1196 vudword low;
1197 vudword high;
1198} mactabentry;
1199
1200/*
1201 * ETHERNET SWITCH
1202 */
1203typedef struct
1204{
1205 vudword rev; /* 0xFC0D_C000 -> 0xFC0D_C003 - Revision */
1206 vudword scr; /* 0xFC0D_C004 -> 0xFC0D_C007 - Scratch Register */
1207 vudword per; /* 0xFC0D_C008 -> 0xFC0D_C00B - Port Enable Register */
1208 vubyte pack00[4]; /* 0xFC0D_C00C -> 0xFC0D_C00F - RESERVED */
1209 vudword vlanv; /* 0xFC0D_C010 -> 0xFC0D_C013 - VLAN Verify */
1210 vudword dbcr; /* 0xFC0D_C014 -> 0xFC0D_C017 - Default Broadcast Resolution */
1211 vudword dmcr; /* 0xFC0D_C018 -> 0xFC0D_C01B - Default Multicast Resolution */
1212 vudword bklr; /* 0xFC0D_C01C -> 0xFC0D_C01F - Blocking and Learning Enable */
1213 vudword bmpc; /* 0xFC0D_C020 -> 0xFC0D_C023 - Bridge Management Port Configuration */
1214 vudword mode; /* 0xFC0D_C024 -> 0xFC0D_C027 - Mode Configuration */
1215 vudword vimsel; /* 0xFC0D_C028 -> 0xFC0D_C02B - VLAN Input Manipulation Select */
1216 vudword vomsel; /* 0xFC0D_C02C -> 0xFC0D_C02F - VLAN Output Manipulation Select */
1217 vudword vimen; /* 0xFC0D_C030 -> 0xFC0D_C033 - VLAN Input Manipulation Enable */
1218 vudword vid; /* 0xFC0D_C034 -> 0xFC0D_C037 - VLAN Tag ID */
1219 vubyte pack01[8]; /* 0xFC0D_C038 -> 0xFC0D_C03F - RESERVED */
1220 vudword mcr; /* 0xFC0D_C040 -> 0xFC0D_C043 - Mirror Control Register */
1221 vudword egmap; /* 0xFC0D_C044 -> 0xFC0D_C047 - Egress Port Definitions */
1222 vudword ingmap; /* 0xFC0D_C048 -> 0xFC0D_C04B - Ingress Port Definitions */
1223 vudword ingsal; /* 0xFC0D_C04C -> 0xFC0D_C04F - Ingress Source MAC Address Low */
1224 vudword ingsah; /* 0xFC0D_C050 -> 0xFC0D_C053 - Ingress Source MAC Address High */
1225 vudword ingdal; /* 0xFC0D_C054 -> 0xFC0D_C057 - Ingress Destination MAC Address Low */
1226 vudword ingdah; /* 0xFC0D_C058 -> 0xFC0D_C05B - Ingress Destination MAC Address High */
1227 vudword egsal; /* 0xFC0D_C05C -> 0xFC0D_C05F - Egress Source MAC Address Low */
1228 vudword egsah; /* 0xFC0D_C060 -> 0xFC0D_C063 - Egress Source MAC Address High */
1229 vudword egdal; /* 0xFC0D_C064 -> 0xFC0D_C067 - Egress Destination MAC Address Low */
1230 vudword egdah; /* 0xFC0D_C068 -> 0xFC0D_C06B - Egress Destination MAC Address High */
1231 vudword mcval; /* 0xFC0D_C06C -> 0xFC0D_C06F - Mirror Count Value */
1232 vubyte pack02[16]; /* 0xFC0D_C070 -> 0xFC0D_C07F - RESERVED */
1233 vudword mmsr; /* 0xFC0D_C080 -> 0xFC0D_C083 - Memory Manager Status */
1234 vudword lmt; /* 0xFC0D_C084 -> 0xFC0D_C087 - Low Memory Threshold */
1235 vudword lfc; /* 0xFC0D_C088 -> 0xFC0D_C08B - Lowest Number of Free Cells */
1236 vudword pcsr; /* 0xFC0D_C08C -> 0xFC0D_C08F - Port Congestion Status */
1237 vudword iosr; /* 0xFC0D_C090 -> 0xFC0D_C093 - Switch Input and Output Interface Status */
1238 vudword qwt; /* 0xFC0D_C094 -> 0xFC0D_C097 - Queue Weights */
1239 vubyte pack03[4]; /* 0xFC0D_C098 -> 0xFC0D_C09B - RESERVED */
1240 vudword p0bct; /* 0xFC0D_C09C -> 0xFC0D_C09F - Port 0 Backpressure Congestion Threshold */
1241 vubyte pack04[28]; /* 0xFC0D_C0A0 -> 0xFC0D_C0BB - RESERVED */
1242 vudword ffen; /* 0xFC0D_C0BC -> 0xFC0D_C0BF - Port 0 Forced Forwarding Enable */
1243 vudword psnp1; /* 0xFC0D_C0C0 -> 0xFC0D_C0C3 - Port Snooping Register 1 */
1244 vudword psnp2; /* 0xFC0D_C0C4 -> 0xFC0D_C0C7 - Port Snooping Register 2 */
1245 vudword psnp3; /* 0xFC0D_C0C8 -> 0xFC0D_C0CB - Port Snooping Register 3 */
1246 vudword psnp4; /* 0xFC0D_C0CC -> 0xFC0D_C0CF - Port Snooping Register 4 */
1247 vudword psnp5; /* 0xFC0D_C0D0 -> 0xFC0D_C0D3 - Port Snooping Register 5 */
1248 vudword psnp6; /* 0xFC0D_C0D4 -> 0xFC0D_C0D7 - Port Snooping Register 6 */
1249 vudword psnp7; /* 0xFC0D_C0D8 -> 0xFC0D_C0DB - Port Snooping Register 7 */
1250 vudword psnp8; /* 0xFC0D_C0DC -> 0xFC0D_C0DF - Port Snooping Register 8 */
1251 vudword ipsnp1; /* 0xFC0D_C0E0 -> 0xFC0D_C0E3 - IP Snooping Register 1 */
1252 vudword ipsnp2; /* 0xFC0D_C0E4 -> 0xFC0D_C0E7 - IP Snooping Register 2 */
1253 vudword ipsnp3; /* 0xFC0D_C0E8 -> 0xFC0D_C0EB - IP Snooping Register 3 */
1254 vudword ipsnp4; /* 0xFC0D_C0EC -> 0xFC0D_C0EF - IP Snooping Register 4 */
1255 vudword ipsnp5; /* 0xFC0D_C0F0 -> 0xFC0D_C0F3 - IP Snooping Register 5 */
1256 vudword ipsnp6; /* 0xFC0D_C0F4 -> 0xFC0D_C0F7 - IP Snooping Register 6 */
1257 vudword ipsnp7; /* 0xFC0D_C0F8 -> 0xFC0D_C0FB - IP Snooping Register 7 */
1258 vudword ipsnp8; /* 0xFC0D_C0FC -> 0xFC0D_C0FF - IP Snooping Register 8 */
1259 vudword p0vres; /* 0xFC0D_C100 -> 0xFC0D_C103 - Port 0 VLAN Priority Resolution Map */
1260 vudword p1vres; /* 0xFC0D_C104 -> 0xFC0D_C107 - Port 1 VLAN Priority Resolution Map */
1261 vudword p2vres; /* 0xFC0D_C108 -> 0xFC0D_C10B - Port 2 VLAN Priority Resolution Map */
1262 vubyte pack05[52]; /* 0xFC0D_C10C -> 0xFC0D_C13F - RESERVED */
1263 vudword ipres; /* 0xFC0D_C140 -> 0xFC0D_C143 - IPv4/v6 Priority Resolution Table */
1264 vubyte pack06[60]; /* 0xFC0D_C144 -> 0xFC0D_C17F - RESERVED */
1265 vudword p0res; /* 0xFC0D_C180 -> 0xFC0D_C183 - Port 0 Priority Resolution Configuration */
1266 vudword p1res; /* 0xFC0D_C184 -> 0xFC0D_C187 - Port 1 Priority Resolution Configuration */
1267 vudword p2res; /* 0xFC0D_C188 -> 0xFC0D_C18B - Port 2 Priority Resolution Configuration */
1268 vubyte pack07[116]; /* 0xFC0D_C18C -> 0xFC0D_C1FF - RESERVED */
1269 vudword p0id; /* 0xFC0D_C200 -> 0xFC0D_C203 - Port 0 VLAN ID */
1270 vudword p1id; /* 0xFC0D_C204 -> 0xFC0D_C207 - Port 1 VLAN ID */
1271 vudword p2id; /* 0xFC0D_C208 -> 0xFC0D_C20B - Port 2 VLAN ID */
1272 vubyte pack08[116]; /* 0xFC0D_C20C -> 0xFC0D_C27F - RESERVED */
1273 vudword vres[32]; /* 0xFC0D_C280 -> 0xFC0D_C2FF - VLAN Domain Resolution Entry 0-31 */
1274 vudword discn; /* 0xFC0D_C300 -> 0xFC0D_C303 - Number of Discarded Frames */
1275 vudword discb; /* 0xFC0D_C304 -> 0xFC0D_C307 - Bytes of Discarded Frames */
1276 vudword ndiscn; /* 0xFC0D_C308 -> 0xFC0D_C30B - Number of Non-Discarded Frames */
1277 vudword ndiscb; /* 0xFC0D_C30C -> 0xFC0D_C30F - Bytes of Non-Discarded Frames */
1278 vudword p0oqc; /* 0xFC0D_C310 -> 0xFC0D_C313 - Port 0 Output Queue Congestion */
1279 vudword p0mvid; /* 0xFC0D_C314 -> 0xFC0D_C317 - Port 0 Mismatching VLAN ID */
1280 vudword p0mvtag; /* 0xFC0D_C318 -> 0xFC0D_C31B - Port 0 Missing VLAN Tag */
1281 vudword p0bl; /* 0xFC0D_C31C -> 0xFC0D_C31F - Port 0 Blocked */
1282 vudword p1oqc; /* 0xFC0D_C320 -> 0xFC0D_C323 - Port 1 Output Queue Congestion */
1283 vudword p1mvid; /* 0xFC0D_C324 -> 0xFC0D_C327 - Port 1 Mismatching VLAN ID */
1284 vudword p1mvtag; /* 0xFC0D_C328 -> 0xFC0D_C32B - Port 1 Missing VLAN Tag */
1285 vudword p1bl; /* 0xFC0D_C32C -> 0xFC0D_C32F - Port 1 Blocked */
1286 vudword p2oqc; /* 0xFC0D_C330 -> 0xFC0D_C333 - Port 2 Output Queue Congestion */
1287 vudword p2mvid; /* 0xFC0D_C334 -> 0xFC0D_C337 - Port 2 Mismatching VLAN ID */
1288 vudword p2mvtag; /* 0xFC0D_C338 -> 0xFC0D_C33B - Port 2 Missing VLAN Tag */
1289 vudword p2bl; /* 0xFC0D_C33C -> 0xFC0D_C33F - Port 2 Blocked */
1290 vubyte pack09[192]; /* 0xFC0D_C340 -> 0xFC0D_C3FF - RESERVED */
1291 vudword isr; /* 0xFC0D_C400 -> 0xFC0D_C403 - Interrupt Status Register */
1292 vudword imr; /* 0xFC0D_C404 -> 0xFC0D_C407 - Interrupt Mask Register */
1293 vudword rdsr; /* 0xFC0D_C408 -> 0xFC0D_C40B - Receive Descriptor Ring Pointer */
1294 vudword tdsr; /* 0xFC0D_C40C -> 0xFC0D_C40F - Transmit Descriptor Ring Pointer */
1295 vudword mrbr; /* 0xFC0D_C410 -> 0xFC0D_C413 - Maximum Receive Buffer Size */
1296 vudword rdar; /* 0xFC0D_C414 -> 0xFC0D_C417 - Receive Descriptor Active */
1297 vudword tdar; /* 0xFC0D_C418 -> 0xFC0D_C41B - Transmit Descriptor Active */
1298 vubyte pack10[228]; /* 0xFC0D_C41C -> 0xFC0D_C4FF - RESERVED */
1299 vudword lrec0; /* 0xFC0D_C500 -> 0xFC0D_C503 - Learning Records A0 & B1 */
1300 vudword lrec1; /* 0xFC0D_C504 -> 0xFC0D_C507 - Learning Record B1 */
1301 vudword lsr; /* 0xFC0D_C508 -> 0xFC0D_C50B - Learning Data Available Status */
1302 vubyte pack11[15092]; /* 0xFC0D_C50C -> 0xFC0D_FFFF - RESERVED */
1303 mactabentry mactable[2048]; /* 0xFC0E_0000 -> 0xFC0E_3FFF - MAC Address Lookup Table */
1304} eswstruct;
1305
1306/*
1307 * NAND FLASH CONTROLLER
1308 */
1309typedef struct
1310{
1311 vudword sramb0[576]; /* 0xFC0F_C000 -> 0xFC0F_C8FF - SRAM Buffer 0 */
1312 vubyte pack00[1792]; /* 0xFC0F_C900 -> 0xFC0F_CFFF - RESERVED */
1313 vudword sramb1[576]; /* 0xFC0F_D000 -> 0xFC0F_D8FF - SRAM Buffer 1 */
1314 vubyte pack01[1792]; /* 0xFC0F_D900 -> 0xFC0F_DFFF - RESERVED */
1315 vudword sramb2[576]; /* 0xFC0F_E000 -> 0xFC0F_E8FF - SRAM Buffer 2 */
1316 vubyte pack02[1792]; /* 0xFC0F_E900 -> 0xFC0F_EFFF - RESERVED */
1317 vudword sramb3[576]; /* 0xFC0F_F000 -> 0xFC0F_F8FF - SRAM Buffer 3 */
1318 vubyte pack03[1536]; /* 0xFC0F_F900 -> 0xFC0F_FEFF - RESERVED */
1319 vudword cmd1; /* 0xFC0F_FF00 -> 0xFC0F_FF03 - Flash Command 1 */
1320 vudword cmd2; /* 0xFC0F_FF04 -> 0xFC0F_FF07 - Flash Command 2 */
1321 vudword car; /* 0xFC0F_FF08 -> 0xFC0F_FF0B - Column Address */
1322 vudword rar; /* 0xFC0F_FF0C -> 0xFC0F_FF0F - Row Address */
1323 vudword rpt; /* 0xFC0F_FF10 -> 0xFC0F_FF13 - Flash Command Repeat */
1324 vudword rai; /* 0xFC0F_FF14 -> 0xFC0F_FF17 - Row Address Increment */
1325 vudword sr1; /* 0xFC0F_FF18 -> 0xFC0F_FF1B - Flash Status 1 */
1326 vudword sr2; /* 0xFC0F_FF1C -> 0xFC0F_FF1F - Flash Status 2 */
1327 vudword dma1; /* 0xFC0F_FF20 -> 0xFC0F_FF23 - DMA 1 Address Register */
1328 vudword dmacfg; /* 0xFC0F_FF24 -> 0xFC0F_FF27 - DMA Configuration Register */
1329 vudword swap; /* 0xFC0F_FF28 -> 0xFC0F_FF2B - Cache Swap Register */
1330 vudword secsz; /* 0xFC0F_FF2C -> 0xFC0F_FF2F - Sector Size Register */
1331 vudword cfg; /* 0xFC0F_FF30 -> 0xFC0F_FF33 - Flash Configuration Register */
1332 vudword dma2; /* 0xFC0F_FF34 -> 0xFC0F_FF37 - DMA 2 Address Register */
1333 vudword isr; /* 0xFC0F_FF38 -> 0xFC0F_FF3B - Interrupt Status Register */
1334} nfcstruct;
1335
1336/*
1337 * MCF54418 MAIN STRUCT 1
1338 */
1339typedef struct
1340{
1341 owstruct ow; /* 0xEC00_8000 -> 0xEC00_801B - 1-Wire Module */
1342
1343 vubyte pack01[32740]; /* 0xEC00_801C -> 0xEC00_FFFF */
1344
1345 i2cstruct i2c25[4]; /* 0xEC01_0000 -> 0xEC01_FFFF - I2C Module 2-5 */
1346
1347 vubyte pack02[98304]; /* 0xEC02_0000 -> 0xEC03_7FFF */
1348
1349 dspistruct dspi2; /* 0xEC03_8000 -> 0xEC03_80BB - DMA Serial Peripheral Interface 2 */
1350
1351 vubyte pack03[16196]; /* 0xEC03_80BC -> 0xEC03_BFFF */
1352
1353 dspistruct dspi3; /* 0xEC03_C000 -> 0xEC03_C0BB - DMA Serial Peripheral Interface 3 */
1354
1355 vubyte pack04[147268]; /* 0xEC03_C0BC -> 0xEC05_FFFF */
1356
1357 uartstruct uarts[6]; /* 0xEC06_0000 -> 0xEC07_7FFF - UART Module 4-9 */
1358
1359 vubyte pack05[65536]; /* 0xEC07_8000 -> 0xEC08_7FFF */
1360
1361 mcpwmstruct mcpwm; /* 0xEC08_8000 -> 0xEC08_8153 - Motor Control Pulse-Width Modulator */
1362
1363 vubyte pack06[32428]; /* 0xEC08_8154 -> 0xEC08_FFFF */
1364
1365 resetstruct reset; /* 0xEC09_0000 -> 0xEC09_0003 - Reset Controller */
1366
1367 ccmstruct ccm; /* 0xEC09_0004 -> 0xEC09_0027 - Chip Configuration Module */
1368
1369 vubyte pack07[16344]; /* 0xEC09_0028 -> 0xEC09_3FFF */
1370
1371 gpiostruct gpio; /* 0xEC09_4000 -> 0xEC09_4087 - Pin-Multiplexing and Control */
1372
1373} mcf54418_1;
1374
1375/*
1376 * MCF54418 MAIN STRUCT 2
1377 */
1378typedef struct
1379{
1380 xbsstruct xbs; /* 0xFC00_4000 -> 0xFC00_4713 - Crossbar Switch (XBS) */
1381
1382 vubyte pack09[14572]; /* 0xFC00_4714 -> 0xFC00_7FFF */
1383
1384 csstruct cs[6]; /* 0xFC00_8000 -> 0xFC00_8047 - Chip Select 0-5 */
1385
1386 vubyte pack10[98232]; /* 0xFC00_8048 -> 0xFC01_FFFF */
1387
1388 canstruct can[2]; /* 0xFC02_0000 -> 0xFC02_7FFF - Controller Area Network (FlexCAN) 0-1 */
1389
1390 vubyte pack11[65536]; /* 0xFC02_8000 -> 0xFC03_7FFF */
1391
1392 i2cstruct i2c1; /* 0xFC03_8000 -> 0xFC03_8013 - I2C Module 1 */
1393
1394 // vubyte pack12[16364]; /* 0xFC03_8014 -> 0xFC03_BFFF */
1395
1396 dspistruct dspi1; /* 0xFC03_C000 -> 0xFC03_C0BB - DMA Serial Peripheral Interface 1 */
1397
1398 vubyte pack13[16212]; /* 0xFC03_C0BC -> 0xFC04_000F */
1399
1400 scmstruct scm; /* 0xFC04_0010 -> 0xFC04_007F - System Control Module and Power Management */
1401
1402 vubyte pack14[16256]; /* 0xFC04_0080 -> 0xFC04_3FFF */
1403
1404 edmastruct edma; /* 0xFC04_4000 -> 0xFC04_57FF - Enhanced Direct Memory Access Controller */
1405
1406 vubyte pack15[10240]; /* 0xFC04_5800 -> 0xFC04_7FFF */
1407
1408 intcstruct intc[3]; /* 0xFC04_8000 -> 0xFC05_3FFF - Interrupt Controller 0-2 */
1409
1410 vubyte pack16[224]; /* 0xFC05_4000 -> 0xFC05_40DF */
1411
1412 intc_iackstruct intc_iack; /* 0xFC05_40E0 -> 0xFC05_40FF - Global Interrupt Acknowledge Cycles */
1413
1414 vubyte pack17[16128]; /* 0xFC05_4100 -> 0xFC05_7FFF */
1415
1416 i2cstruct i2c0; /* 0xFC05_8000 -> 0xFC05_8013 - I2C Module 0 */
1417
1418 // vubyte pack18[16364]; /* 0xFC05_8014 -> 0xFC05_BFFF */
1419
1420 dspistruct dspi0; /* 0xFC05_C000 -> 0xFC05_C0BB - DMA Serial Peripheral Interface 0 */
1421
1422 vubyte pack19[16196]; /* 0xFC05_C0BC -> 0xFC05_FFFF */
1423
1424 uartstruct uarts[4]; /* 0xFC06_0000 -> 0xFC06_FFFF - UART Module 0-3 */
1425
1426 timerstruct timer[4]; /* 0xFC07_0000 -> 0xFC07_FFFF - DMA Timer Module 0-3 */
1427
1428 pitstruct pit[4]; /* 0xFC08_0000 -> 0xFC08_FFFF - Programmable Interrupt Timer Module 0-3 */
1429
1430 eportstruct eport; /* 0xFC09_0000 -> 0xFC09_0007 - Edge Port Module */
1431
1432 vubyte pack20[16376]; /* 0xFC09_0008 -> 0xFC09_3FFF */
1433
1434 adcstruct adc; /* 0xFC09_4000 -> 0xFC09_405B - Analog-to-Digital Converter */
1435
1436 vubyte pack21[16292]; /* 0xFC09_405C -> 0xFC09_7FFF */
1437
1438 dacstruct dac[2]; /* 0xFC09_8000 -> 0xFC09_FFFF - Digital-to-Analog Converter */
1439
1440 vubyte pack22[32]; /* 0xFC0A_0000 -> 0xFC0A_001F */
1441
1442 sbfstruct sbf; /* 0xFC0A_0020 -> 0xFC0A_0023 - Serial Boot Facility */
1443
1444 vubyte pack23[32732]; /* 0xFC0A_0024 -> 0xFC0A_7FFF */
1445
1446 rtcstruct rtc; /* 0xFC0A_8000 -> 0xFC0A_883F - Real-Time Clock */
1447
1448 vubyte pack24[14272]; /* 0xFC0A_8840 -> 0xFC0A_BFFF */
1449
1450 simstruct sim; /* 0xFC0A_C000 -> 0xFC0A_C07B - Subscriber Identification Module */
1451
1452 vubyte pack25[16260]; /* 0xFC0A_C07C -> 0xFC0A_FFFF */
1453
1454 usb_otgstruct usb_otg; /* 0xFC0B_0000 -> 0xFC0B_01CF - USB On-the-Go */
1455
1456 vubyte pack26[15920]; /* 0xFC0B_01D0 -> 0xFC0B_3FFF */
1457
1458 usb_hoststruct usb_host; /* 0xFC0B_4000 -> 0xFC0B_41AB - USB Host Controller */
1459
1460 vubyte pack27[15956]; /* 0xFC0B_41AC -> 0xFC0B_7FFF */
1461
1462 ddrmcstruct ddrmc; /* 0xFC0B_8000 -> 0xFC0B_81AF - DDR1/2 SDRAM Memory Controller */
1463
1464 vubyte pack28[15952]; /* 0xFC0B_81B0 -> 0xFC0B_BFFF */
1465
1466 ssi0struct ssi0; /* 0xFC0B_C000 -> 0xFC0B_C05B - Synchronous Serial Interface 0 */
1467
1468 vubyte pack29[16292]; /* 0xFC0B_C05C -> 0xFC0B_FFFF */
1469
1470 clockstruct clock; /* 0xFC0C_0000 -> 0xFC0C_000B - Clock Module (Phase-Locked Loop) */
1471
1472 vubyte pack30[16372]; /* 0xFC0C_000C -> 0xFC0C_3FFF */
1473
1474 rngstruct rng; /* 0xFC0C_4000 -> 0xFC0C_401B - Random Number Generator */
1475
1476 vubyte pack31[16356]; /* 0xFC0C_401C -> 0xFC0C_7FFF */
1477
1478 ssi1struct ssi1; /* 0xFC0C_8000 -> 0xFC0C_805B - Synchronous Serial Interface 1 */
1479
1480 vubyte pack32[16292]; /* 0xFC0C_805C -> 0xFC0C_BFFF */
1481
1482 sdhcstruct sdhc; /* 0xFC0C_C000 -> 0xFC0C_C0FF - Enhanced Secure Digital Host Controller */
1483
1484 vubyte pack33[32512]; /* 0xFC0C_C100 -> 0xFC0D_3FFF */
1485
1486 fecstruct fec[2]; /* 0xFC0D_4000 -> 0xFC0D_BFFF - 10/100 Mbps Ethernet MAC-NET Core 0-1 */
1487
1488 eswstruct esw; /* 0xFC0D_C000 -> 0xFC0E_3FFF - Ethernet Switch */
1489
1490 vubyte pack36[98304]; /* 0xFC0E_4000 -> 0xFC0F_BFFF */
1491
1492 nfcstruct nfc; /* 0xFC0F_C000 -> 0xFC0F_FF3B - NAND Flash Controller */
1493
1494} mcf54418_2;
1495
1496extern vudword flash_mirror[0x80000];
1497extern volatile rgpiostruct sim_rgpio;
1498extern volatile mcf54418_1 sim1;
1499extern volatile mcf54418_2 sim2;
1500
1501typedef struct
1502{
1503 unsigned long table[256];
1504} vectors;
1505
1506extern vectors vector_base;
1507
1508typedef struct
1509{
1510 unsigned short flags;
1511 unsigned short length;
1512 unsigned long address;
1513} Legacy_EtherBD;
1514
1515typedef struct
1516{
1517 unsigned short flags;
1518 unsigned short length;
1519 unsigned long address;
1520 unsigned long flags2;
1521 unsigned short hLenAndProt;
1522 unsigned short payCSum;
1523 unsigned long bdu;
1524 unsigned long _1588_ts;
1525 unsigned long pad[2];
1526} Enhanced_EtherBD;
1527
1528#ifdef ENHANCED_ETHER_BD
1529typedef Enhanced_EtherBD EtherBD;
1530#else
1531typedef Legacy_EtherBD EtherBD;
1532#endif
1533
1534#define RXBD_Flag_Empty (0x8000)
1535#define RXBD_Flag_SW1b (0x4000)
1536#define RXBD_Flag_Wrap (0x2000)
1537#define RXBD_Flag_SW2b (0x1000)
1538#define RXBD_Flag_Last (0x0800)
1539#define RXBD_Flag_Miss (0x0100)
1540#define RXBD_Flag_BroadCast (0x0080)
1541#define RXBD_Flag_MultiCast (0x0040)
1542#define RXBD_Flag_LengthErr (0x0020)
1543#define RXBD_Flag_Align_Err (0x0010)
1544#define RXBD_Flag_ShortErr (0x0008)
1545#define RXBD_Flag_CRC_Err (0x0004)
1546#define RXBD_Flag_OverErr (0x0002)
1547#define RXBD_Flag_TruncErr (0x0001)
1548#define RXBD_Error_Mask \
1549 (RXBD_Flag_LengthErr | RXBD_Flag_Align_Err | RXBD_Flag_ShortErr | RXBD_Flag_CRC_Err | RXBD_Flag_OverErr | RXBD_Flag_TruncErr)
1550#define ERXBD_Flag2_MAC_Err (0x80000000)
1551#define ERXBD_Flag2_PHY_Err (0x04000000)
1552#define ERXBD_Flag2_Collision (0x02000000)
1553#define ERXBD_Flag2_Unicast (0x01000000)
1554#define ERXBD_Flag2_IRQ (0x00800000)
1555#define ERXBD_Flag2_IP_CSum (0x00000020)
1556#define ERXBD_Flag2_Prot_CSum (0x00000010)
1557#define ERXBD_Flag2_VLAN (0x00000004)
1558#define ERXBD_Flag2_IPv6 (0x00000002)
1559#define ERXBD_Flag2_Frag (0x00000001)
1560
1561#define TXBD_Flag_Ready (0x8000)
1562#define TXBD_Flag_SW1b (0x4000)
1563#define TXBD_Flag_Wrap (0x2000)
1564#define TXBD_Flag_SW2b (0x1000)
1565#define TXBD_Flag_Last (0x0800)
1566#define TXBD_Flag_TxCRC (0x0400)
1567#define TXBD_Flag_Defered (0x0200)
1568#define TXBD_Flag_HB_Error (0x0100)
1569#define TXBD_Flag_LC_Error (0x0080)
1570#define TXBD_Flag_RT_Error (0x0040)
1571#define TXBD_Flag_RC_B3 (0x0020)
1572#define TXBD_Flag_RC_B2 (0x0010)
1573#define TXBD_Flag_RC_B1 (0x0008)
1574#define TXBD_Flag_RC_B0 (0x0004)
1575#define TXBD_Flag_UN_Error (0x0002)
1576#define TXBD_Flag_CSL_Error (0x0001)
1577#define TXBD_Error_Mask (TXBD_Flag_UN_Error | TXBD_Flag_RT_Error | TXBD_Flag_LC_Error | TXBD_Flag_HB_Error)
1578#define TXBD_Flag_NormalSend (TXBD_Flag_TxCRC | TXBD_Flag_Ready | TXBD_Flag_Last)
1579#define ETXBD_Flag2_IRQ (0x40000000)
1580#define ETXBD_Flag2_TS_RQ (0x20000000)
1581#define ETXBD_Flag2_Insert_Prot (0x10000000)
1582#define ETXBD_Flag2_Insert_IP (0x08000000)
1583#define ETXBD_Flag2_TX_Err (0x00008000)
1584#define ETXBD_Flag2_UFlow_Err (0x00002000)
1585#define ETXBD_Flag2_Coll_Err (0x00001000)
1586#define ETXBD_Flag2_Frame_Err (0x00008000)
1587#define ETXBD_Flag2_Late_Coll (0x00004000)
1588#define ETXBD_Flag2_OFlow_Err (0x00002000)
1589#define ETXBD_Flag2_TS_Err (0x00001000)
1590
1591#define FEC_ISR_MASK_HBERR (0x80000000)
1592#define FEC_ISR_MASK_BABR (0x40000000)
1593#define FEC_ISR_MASK_BABT (0x20000000)
1594#define FEC_ISR_MASK_GRA (0x10000000)
1595#define FEC_ISR_MASK_TXF (0x08000000)
1596#define FEC_ISR_MASK_TXB (0x04000000)
1597#define FEC_ISR_MASK_RXF (0x02000000)
1598#define FEC_ISR_MASK_RXB (0x01000000)
1599#define FEC_ISR_MASK_MII (0x00800000)
1600#define FEC_ISR_MASK_EBERR (0x00400000)
1601#define FEC_ISR_MASK_LC (0x00200000)
1602#define FEC_ISR_MASK_RL (0x00100000)
1603#define FEC_ISR_MASK_UN (0x00080000)
1604
1605#define ESW_ISR_MASK_RXF (0x00000004)
1606#define ESW_ISR_MASK_RXB (0x00000002)
1607#define ESW_ISR_MASK_TXF (0x00000010)
1608#define ESW_ISR_MASK_TXB (0x00000008)
1609#define ESW_ISR_MASK_LRN (0x00000200)
1610
1611#endif /* _SIM54418_H_ */
init
void init()
System initialization. Ideally called at the beginning of all applications, since the easiest Recover...