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same70q21_sim.h
1#ifndef __SAME70Q21_SIM_H
2#define __SAME70Q21_SIM_H
37/*
38 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
39 */
40
41
42
43/*
44 * SOFTWARE PERIPHERAL API DEFINITION FOR SAME70Q21
45 */
46
47/* \addtogroup SAME70Q21_api Peripheral Software API
48 * @{
49 */
50#include "component/acc.h"
51#include "component/aes.h"
52#include "component/afec.h"
53#include "component/chipid.h"
54#include "component/dacc.h"
55#include "component/efc.h"
56#include "component/gmac.h"
57#include "component/gpbr.h"
58#include "component/hsmci.h"
59#include "component/icm.h"
60#include "component/isi.h"
61#include "component/matrix.h"
62#include "component/mcan.h"
63#include "component/pio.h"
64#include "component/pmc.h"
65#include "component/pwm.h"
66#include "component/qspi.h"
67#include "component/rstc.h"
68#include "component/rswdt.h"
69#include "component/rtc.h"
70#include "component/rtt.h"
71#include "component/sdramc.h"
72#include "component/smc.h"
73#include "component/spi.h"
74#include "component/ssc.h"
75#include "component/supc.h"
76#include "component/tc.h"
77#include "component/trng.h"
78#include "component/twihs.h"
79#include "component/uart.h"
80#include "component/usart.h"
81#include "component/usbhs.h"
82#include "component/utmi.h"
83#include "component/wdt.h"
84#include "component/xdmac.h"
85/* @} */
86
87/*
88 * REGISTER ACCESS DEFINITIONS FOR SAME70Q21
89 */
90
91/* \addtogroup SAME70Q21_reg Registers Access Definitions
92 * @{
93 */
94#include "instance/hsmci.h"
95#include "instance/ssc.h"
96#include "instance/spi0.h"
97#include "instance/tc0.h"
98#include "instance/tc1.h"
99#include "instance/tc2.h"
100#include "instance/twihs0.h"
101#include "instance/twihs1.h"
102#include "instance/pwm0.h"
103#include "instance/usart0.h"
104#include "instance/usart1.h"
105#include "instance/usart2.h"
106#include "instance/mcan0.h"
107#include "instance/mcan1.h"
108#include "instance/usbhs.h"
109#include "instance/afec0.h"
110#include "instance/dacc.h"
111#include "instance/acc.h"
112#include "instance/icm.h"
113#include "instance/isi.h"
114#include "instance/gmac.h"
115#include "instance/tc3.h"
116#include "instance/spi1.h"
117#include "instance/pwm1.h"
118#include "instance/twihs2.h"
119#include "instance/afec1.h"
120#include "instance/aes.h"
121#include "instance/trng.h"
122#include "instance/xdmac.h"
123#include "instance/qspi.h"
124#include "instance/smc.h"
125#include "instance/sdramc.h"
126#include "instance/matrix.h"
127#include "instance/utmi.h"
128#include "instance/pmc.h"
129#include "instance/uart0.h"
130#include "instance/chipid.h"
131#include "instance/uart1.h"
132#include "instance/efc.h"
133#include "instance/pioa.h"
134#include "instance/piob.h"
135#include "instance/pioc.h"
136#include "instance/piod.h"
137#include "instance/pioe.h"
138#include "instance/rstc.h"
139#include "instance/supc.h"
140#include "instance/rtt.h"
141#include "instance/wdt.h"
142#include "instance/rtc.h"
143#include "instance/gpbr.h"
144#include "instance/rswdt.h"
145#include "instance/uart2.h"
146#include "instance/uart3.h"
147#include "instance/uart4.h"
148/* @} */
149
150/*
151 * BASE ADDRESS DEFINITIONS FOR SAME70Q21
152 */
153
154/* \addtogroup SAME70Q21_base Peripheral Base Address Definitions
155 * @{
156 */
157#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
158#define HSMCI (0x40000000U)
159#define SSC (0x40004000U)
160#define SPI0 (0x40008000U)
161#define TC0 (0x4000C000U)
162#define TC1 (0x40010000U)
163#define TC2 (0x40014000U)
164#define TWIHS0 (0x40018000U)
165#define TWIHS1 (0x4001C000U)
166#define PWM0 (0x40020000U)
167#define USART0 (0x40024000U)
168#define USART1 (0x40028000U)
169#define USART2 (0x4002C000U)
170#define MCAN0 (0x40030000U)
171#define MCAN1 (0x40034000U)
172#define USBHS (0x40038000U)
173#define AFEC0 (0x4003C000U)
174#define DACC (0x40040000U)
175#define ACC (0x40044000U)
176#define ICM (0x40048000U)
177#define ISI (0x4004C000U)
178#define GMAC (0x40050000U)
179#define TC3 (0x40054000U)
180#define SPI1 (0x40058000U)
181#define PWM1 (0x4005C000U)
182#define TWIHS2 (0x40060000U)
183#define AFEC1 (0x40064000U)
184#define AES (0x4006C000U)
185#define TRNG (0x40070000U)
186#define XDMAC (0x40078000U)
187#define QSPI (0x4007C000U)
188#define SMC (0x40080000U)
189#define SDRAMC (0x40084000U)
190#define MATRIX (0x40088000U)
191#define UTMI (0x400E0400U)
192#define PMC (0x400E0600U)
193#define UART0 (0x400E0800U)
194#define CHIPID (0x400E0940U)
195#define UART1 (0x400E0A00U)
196#define EFC (0x400E0C00U)
197#define PIOA (0x400E0E00U)
198#define PIOB (0x400E1000U)
199#define PIOC (0x400E1200U)
200#define PIOD (0x400E1400U)
201#define PIOE (0x400E1600U)
202#define RSTC (0x400E1800U)
203#define SUPC (0x400E1810U)
204#define RTT (0x400E1830U)
205#define WDT (0x400E1850U)
206#define RTC (0x400E1860U)
207#define GPBR (0x400E1890U)
208#define RSWDT (0x400E1900U)
209#define UART2 (0x400E1A00U)
210#define UART3 (0x400E1C00U)
211#define UART4 (0x400E1E00U)
212#else
213#define HSMCI ((Hsmci *)0x40000000U)
214#define SSC ((Ssc *)0x40004000U)
215#define SPI0 ((Spi *)0x40008000U)
216#define TC0 ((Tc *)0x4000C000U)
217#define TC1 ((Tc *)0x40010000U)
218#define TC2 ((Tc *)0x40014000U)
219#define TWIHS0 ((Twihs *)0x40018000U)
220#define TWIHS1 ((Twihs *)0x4001C000U)
221#define PWM0 ((Pwm *)0x40020000U)
222#define USART0 ((Usart *)0x40024000U)
223#define USART1 ((Usart *)0x40028000U)
224#define USART2 ((Usart *)0x4002C000U)
225#define MCAN0 ((Mcan *)0x40030000U)
226#define MCAN1 ((Mcan *)0x40034000U)
227#define USBHS ((Usbhs *)0x40038000U)
228#define AFEC0 ((Afec *)0x4003C000U)
229#define DACC ((Dacc *)0x40040000U)
230#define ACC ((Acc *)0x40044000U)
231#define ICM ((Icm *)0x40048000U)
232#define ISI ((Isi *)0x4004C000U)
233#define GMAC ((Gmac *)0x40050000U)
234#define TC3 ((Tc *)0x40054000U)
235#define SPI1 ((Spi *)0x40058000U)
236#define PWM1 ((Pwm *)0x4005C000U)
237#define TWIHS2 ((Twihs *)0x40060000U)
238#define AFEC1 ((Afec *)0x40064000U)
239#define AES ((Aes *)0x4006C000U)
240#define TRNG ((Trng *)0x40070000U)
241#define XDMAC ((Xdmac *)0x40078000U)
242#define QSPI ((Qspi *)0x4007C000U)
243#define SMC ((Smc *)0x40080000U)
244#define SDRAMC ((Sdramc *)0x40084000U)
245#define MATRIX ((Matrix *)0x40088000U)
246#define UTMI ((Utmi *)0x400E0400U)
247#define PMC ((Pmc *)0x400E0600U)
248#define UART0 ((Uart *)0x400E0800U)
249#define CHIPID ((Chipid *)0x400E0940U)
250#define UART1 ((Uart *)0x400E0A00U)
251#define EFC ((Efc *)0x400E0C00U)
252#define PIO ((Pio[5] )0x400E0E00U)
253#define PIOA ((Pio *)0x400E0E00U)
254#define PIOB ((Pio *)0x400E1000U)
255#define PIOC ((Pio *)0x400E1200U)
256#define PIOD ((Pio *)0x400E1400U)
257#define PIOE ((Pio *)0x400E1600U)
258#define RSTC ((Rstc *)0x400E1800U)
259#define SUPC ((Supc *)0x400E1810U)
260#define RTT ((Rtt *)0x400E1830U)
261#define WDT ((Wdt *)0x400E1850U)
262#define RTC ((Rtc *)0x400E1860U)
263#define GPBR ((Gpbr *)0x400E1890U)
264#define RSWDT ((Rswdt *)0x400E1900U)
265#define UART2 ((Uart *)0x400E1A00U)
266#define UART3 ((Uart *)0x400E1C00U)
267#define UART4 ((Uart *)0x400E1E00U)
269#define ADDR_HSMCI (0x40000000U)
270#define ADDR_SSC (0x40004000U)
271#define ADDR_SPI0 (0x40008000U)
272#define ADDR_TC0 (0x4000C000U)
273#define ADDR_TC1 (0x40010000U)
274#define ADDR_TC2 (0x40014000U)
275#define ADDR_TWIHS0 (0x40018000U)
276#define ADDR_TWIHS1 (0x4001C000U)
277#define ADDR_PWM0 (0x40020000U)
278#define ADDR_USART0 (0x40024000U)
279#define ADDR_USART1 (0x40028000U)
280#define ADDR_USART2 (0x4002C000U)
281#define ADDR_MCAN0 (0x40030000U)
282#define ADDR_MCAN1 (0x40034000U)
283#define ADDR_USBHS (0x40038000U)
284#define ADDR_AFEC0 (0x4003C000U)
285#define ADDR_DACC (0x40040000U)
286#define ADDR_ACC (0x40044000U)
287#define ADDR_ICM (0x40048000U)
288#define ADDR_ISI (0x4004C000U)
289#define ADDR_GMAC (0x40050000U)
290#define ADDR_TC3 (0x40054000U)
291#define ADDR_SPI1 (0x40058000U)
292#define ADDR_PWM1 (0x4005C000U)
293#define ADDR_TWIHS2 (0x40060000U)
294#define ADDR_AFEC1 (0x40064000U)
295#define ADDR_AES (0x4006C000U)
296#define ADDR_TRNG (0x40070000U)
297#define ADDR_XDMAC (0x40078000U)
298#define ADDR_QSPI (0x4007C000U)
299#define ADDR_SMC (0x40080000U)
300#define ADDR_SDRAMC (0x40084000U)
301#define ADDR_MATRIX (0x40088000U)
302#define ADDR_UTMI (0x400E0400U)
303#define ADDR_PMC (0x400E0600U)
304#define ADDR_UART0 (0x400E0800U)
305#define ADDR_CHIPID (0x400E0940U)
306#define ADDR_UART1 (0x400E0A00U)
307#define ADDR_EFC (0x400E0C00U)
308#define ADDR_PIOA (0x400E0E00U)
309#define ADDR_PIOB (0x400E1000U)
310#define ADDR_PIOC (0x400E1200U)
311#define ADDR_PIOD (0x400E1400U)
312#define ADDR_PIOE (0x400E1600U)
313#define ADDR_RSTC (0x400E1800U)
314#define ADDR_SUPC (0x400E1810U)
315#define ADDR_RTT (0x400E1830U)
316#define ADDR_WDT (0x400E1850U)
317#define ADDR_RTC (0x400E1860U)
318#define ADDR_GPBR (0x400E1890U)
319#define ADDR_RSWDT (0x400E1900U)
320#define ADDR_UART2 (0x400E1A00U)
321#define ADDR_UART3 (0x400E1C00U)
322#define ADDR_UART4 (0x400E1E00U)
324#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
325/* @} */
326
327/*
328 * PIO DEFINITIONS FOR SAME70Q21
329 */
330
331/* \addtogroup SAME70Q21_pio Peripheral Pio Definitions
332 * @{
333 */
334
335#include "pio/same70q21.h"
336/* @} */
337
338
339
340#endif /* ----- #ifndef __SAME70Q21_SIM_H ----- */