NetBurner 3.5.8
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regs.h
1#include <stdint.h>
2typedef uint16_t beuint16_t;
3typedef uint32_t beuint32_t;
4
5#define KSZ98XX_MAX_PORTS 8
6
7struct global_control_t {
8 uint8_t CHIP_ID0; /* Address: 0x00-0x00 */
9 uint8_t CHIP_ID1; /* Address: 0x01-0x01 */
10 uint8_t CHIP_ID2; /* Address: 0x02-0x02 */
11 uint8_t CHIP_ID3; /* Address: 0x03-0x03 */
12 uint8_t RESERVED0[0x02]; /* Address: 0x04-0x05 */
13 uint8_t PME_CTRL; /* Address: 0x06-0x06 */
14 uint8_t RESERVED1[0x08]; /* Address: 0x07-0x0E */
15 uint8_t GLOBAL_OPTIONS; /* Address: 0x0F-0x0F */
16 beuint32_t GLOBAL_INT_STATUS; /* Address: 0x10-0x13 */
17 beuint32_t GLOBAL_INT_MASK; /* Address: 0x14-0x17 */
18 beuint32_t PORT_INT_STATUS; /* Address: 0x18-0x1B */
19 beuint32_t PORT_INT_MASK; /* Address: 0x1C-0x1F */
20 beuint32_t PHY_INT_STATUS; /* Address: 0x20-0x23 */
21 beuint32_t PHY_INT_MASK; /* Address: 0x24-0x27 */
22 uint8_t RESERVED2[0xD8]; /* Address: 0x28-0xFF */
23
24} __attribute__((packed));
25
26struct global_io_control_t {
27 uint8_t SERIAL_IO_CTRL; /* Address: 0x100-0x100 */
28 uint8_t RESERVED0[0x02]; /* Address: 0x101-0x102 */
29 uint8_t OUTPUT_CLOCK_CTRL; /* Address: 0x103-0x103 */
30 beuint32_t IBA_CTRL; /* Address: 0x104-0x107 */
31 beuint32_t APB_TIMEOUT; /* Address: 0x108-0x10B */
32 uint8_t IBA_SYNC; /* Address: 0x10C-0x10C */
33 uint8_t IO_DRIVE_STRENGTH; /* Address: 0x10D-0x10D */
34 uint8_t RESERVED1[0x02]; /* Address: 0x10E-0x10F */
35 beuint32_t IBA_STATUS; /* Address: 0x110-0x113 */
36 beuint32_t IBA_STATES; /* Address: 0x114-0x117 */
37 beuint32_t IBA_RESULT; /* Address: 0x118-0x11B */
38 uint8_t RESERVED2[0x04]; /* Address: 0x11C-0x11F */
39 beuint32_t LED_OVERRIDE; /* Address: 0x120-0x123 */
40 beuint32_t LED_OUTPUT; /* Address: 0x124-0x127 */
41 uint8_t RESERVED3[0xD8]; /* Address: 0x128-0x1FF */
42
43} __attribute__((packed));
44
45struct global_phy_control_t {
46 uint8_t RESERVED0[0x01]; /* Address: 0x200-0x200 */
47 uint8_t POWER_MANAGEMENT_CTRL; /* Address: 0x201-0x201 */
48 uint8_t RESERVED1[0x0E]; /* Address: 0x202-0x20F */
49 beuint32_t LED_STRAP; /* Address: 0x210-0x213 */
50 uint8_t RESERVED2[0xEC]; /* Address: 0x214-0x2FF */
51
52} __attribute__((packed));
53
54struct global_switch_control_t {
55 uint8_t SW_OPERATION; /* Address: 0x300-0x300 */
56 uint8_t RESERVED0[0x01]; /* Address: 0x301-0x301 */
57 uint8_t SW_MAC_ADDR_0; /* Address: 0x302-0x302 */
58 uint8_t SW_MAC_ADDR_1; /* Address: 0x303-0x303 */
59 uint8_t SW_MAC_ADDR_2; /* Address: 0x304-0x304 */
60 uint8_t SW_MAC_ADDR_3; /* Address: 0x305-0x305 */
61 uint8_t SW_MAC_ADDR_4; /* Address: 0x306-0x306 */
62 uint8_t SW_MAC_ADDR_5; /* Address: 0x307-0x307 */
63 beuint16_t SW_MTU; /* Address: 0x308-0x309 */
64 beuint16_t SW_ISP_TPID; /* Address: 0x30A-0x30B */
65 beuint16_t SW_HSR_TPID; /* Address: 0x30C-0x30D */
66 beuint16_t SW_AVB_STRATEGY; /* Address: 0x30E-0x30F */
67 beuint32_t SW_LUE_CTRL; /* Address: 0x310-0x313 */
68 uint8_t SW_LUE_INT_STATUS; /* Address: 0x314-0x314 */
69 uint8_t SW_LUE_INT_MASK; /* Address: 0x315-0x315 */
70 beuint16_t SW_LUE_INDEX_WRITE; /* Address: 0x316-0x317 */
71 beuint16_t SW_LUE_INDEX_LEARN; /* Address: 0x318-0x319 */
72 beuint16_t SW_LUE_INDEX_CPU; /* Address: 0x31A-0x31B */
73 uint8_t RESERVED1[0x04]; /* Address: 0x31C-0x31F */
74 beuint32_t SW_UNK_UCAST_CTRL; /* Address: 0x320-0x323 */
75 beuint32_t SW_UNK_MCAST_CTRL; /* Address: 0x324-0x327 */
76 beuint32_t SW_UNK_VID_CTRL; /* Address: 0x328-0x32B */
77 uint8_t RESERVED2[0x04]; /* Address: 0x32C-0x32F */
78 beuint32_t SW_MAC_CTRL; /* Address: 0x330-0x333 */
79 beuint32_t SW_MAC_CTRL2; /* Address: 0x334-0x337 */
80 beuint32_t SW_MAC_802_1P_MAP; /* Address: 0x338-0x33B */
81 uint8_t RESERVED3[0x02]; /* Address: 0x33C-0x33D */
82 uint8_t SW_MAC_TOS_CTRL; /* Address: 0x33E-0x33E */
83 uint8_t RESERVED4[0x01]; /* Address: 0x33F-0x33F */
84 uint8_t SW_MAC_TOS_PRIO_0; /* Address: 0x340-0x340 */
85 uint8_t SW_MAC_TOS_PRIO_1; /* Address: 0x341-0x341 */
86 uint8_t SW_MAC_TOS_PRIO_2; /* Address: 0x342-0x342 */
87 uint8_t SW_MAC_TOS_PRIO_3; /* Address: 0x343-0x343 */
88 uint8_t SW_MAC_TOS_PRIO_4; /* Address: 0x344-0x344 */
89 uint8_t SW_MAC_TOS_PRIO_5; /* Address: 0x345-0x345 */
90 uint8_t SW_MAC_TOS_PRIO_6; /* Address: 0x346-0x346 */
91 uint8_t SW_MAC_TOS_PRIO_7; /* Address: 0x347-0x347 */
92 uint8_t SW_MAC_TOS_PRIO_8; /* Address: 0x348-0x348 */
93 uint8_t SW_MAC_TOS_PRIO_9; /* Address: 0x349-0x349 */
94 uint8_t SW_MAC_TOS_PRIO_10; /* Address: 0x34A-0x34A */
95 uint8_t SW_MAC_TOS_PRIO_11; /* Address: 0x34B-0x34B */
96 uint8_t SW_MAC_TOS_PRIO_12; /* Address: 0x34C-0x34C */
97 uint8_t SW_MAC_TOS_PRIO_13; /* Address: 0x34D-0x34D */
98 uint8_t SW_MAC_TOS_PRIO_14; /* Address: 0x34E-0x34E */
99 uint8_t SW_MAC_TOS_PRIO_15; /* Address: 0x34F-0x34F */
100 uint8_t SW_MAC_TOS_PRIO_16; /* Address: 0x350-0x350 */
101 uint8_t SW_MAC_TOS_PRIO_17; /* Address: 0x351-0x351 */
102 uint8_t SW_MAC_TOS_PRIO_18; /* Address: 0x352-0x352 */
103 uint8_t SW_MAC_TOS_PRIO_19; /* Address: 0x353-0x353 */
104 uint8_t SW_MAC_TOS_PRIO_20; /* Address: 0x354-0x354 */
105 uint8_t SW_MAC_TOS_PRIO_21; /* Address: 0x355-0x355 */
106 uint8_t SW_MAC_TOS_PRIO_22; /* Address: 0x356-0x356 */
107 uint8_t SW_MAC_TOS_PRIO_23; /* Address: 0x357-0x357 */
108 uint8_t SW_MAC_TOS_PRIO_24; /* Address: 0x358-0x358 */
109 uint8_t SW_MAC_TOS_PRIO_25; /* Address: 0x359-0x359 */
110 uint8_t SW_MAC_TOS_PRIO_26; /* Address: 0x35A-0x35A */
111 uint8_t SW_MAC_TOS_PRIO_27; /* Address: 0x35B-0x35B */
112 uint8_t SW_MAC_TOS_PRIO_28; /* Address: 0x35C-0x35C */
113 uint8_t SW_MAC_TOS_PRIO_29; /* Address: 0x35D-0x35D */
114 uint8_t SW_MAC_TOS_PRIO_30; /* Address: 0x35E-0x35E */
115 uint8_t SW_MAC_TOS_PRIO_31; /* Address: 0x35F-0x35F */
116 uint8_t RESERVED5[0x10]; /* Address: 0x360-0x36F */
117 uint8_t SW_MRI_CTRL; /* Address: 0x370-0x370 */
118 uint8_t RESERVED6[0x07]; /* Address: 0x371-0x377 */
119 uint8_t SW_WRED_DSCP_COLOR; /* Address: 0x378-0x378 */
120 uint8_t RESERVED7[0x17]; /* Address: 0x379-0x38F */
121 beuint32_t SW_QM_CTRL; /* Address: 0x390-0x393 */
122 uint8_t RESERVED8[0x2E]; /* Address: 0x394-0x3C1 */
123 beuint16_t SW_EEE_TXQ_WAIT_TIME; /* Address: 0x3C2-0x3C3 */
124 uint8_t RESERVED9[0x3C]; /* Address: 0x3C4-0x3FF */
125
126} __attribute__((packed));
127
128struct global_lue_control_t {
129 beuint32_t VLAN_ENTRY; /* Address: 0x400-0x403 */
130 beuint32_t VLAN_UNTAG; /* Address: 0x404-0x407 */
131 beuint32_t VLAN_FORWARD; /* Address: 0x408-0x40B */
132 beuint16_t VLAN_INDEX; /* Address: 0x40C-0x40D */
133 uint8_t VLAN_CTRL; /* Address: 0x40E-0x40E */
134 uint8_t RESERVED0[0x01]; /* Address: 0x40F-0x40F */
135 beuint32_t ALU_INDEX; /* Address: 0x410-0x413 */
136 beuint32_t ALU_INDEX2; /* Address: 0x414-0x417 */
137 beuint32_t ALU_CTRL; /* Address: 0x418-0x41B */
138 beuint32_t ALU_STAT_CTRL; /* Address: 0x41C-0x41F */
139 beuint32_t ALU_VAL_A; /* Address: 0x420-0x423 */
140 beuint32_t ALU_VAL_B; /* Address: 0x424-0x427 */
141 beuint32_t ALU_VAL_C; /* Address: 0x428-0x42B */
142 beuint32_t ALU_VAL_D; /* Address: 0x42C-0x42F */
143 uint8_t RESERVED1[0xD0]; /* Address: 0x430-0x4FF */
144
145} __attribute__((packed));
146
147struct global_ptp_control_t {
148 beuint16_t PTP_CLK_CTRL; /* Address: 0x500-0x501 */
149 beuint16_t PTP_RTC_PHASE; /* Address: 0x502-0x503 */
150 beuint32_t PTP_RTC_NANO; /* Address: 0x504-0x507 */
151 beuint32_t PTP_RTC_SEC; /* Address: 0x508-0x50B */
152 beuint32_t PTP_RTC_SUBNANO; /* Address: 0x50C-0x50F */
153 beuint32_t PTP_RTC_TMP_ADJ; /* Address: 0x510-0x513 */
154 beuint32_t PTP_MSG_CONFIG; /* Address: 0x514-0x517 */
155 beuint16_t PTP_DOMAIN_VERSION; /* Address: 0x518-0x519 */
156 uint8_t RESERVED0[0x06]; /* Address: 0x51A-0x51F */
157 beuint32_t PTP_UNIT_INDEX; /* Address: 0x520-0x523 */
158 beuint32_t PTP_TRIG_STATUS; /* Address: 0x524-0x527 */
159 beuint32_t PTP_INT_STATUS; /* Address: 0x528-0x52B */
160 beuint32_t PTP_TS_CTRL; /* Address: 0x52C-0x52F */
161 beuint32_t PTP_TRIG_TARGET_NANO; /* Address: 0x530-0x533 */
162 beuint32_t PTP_TRIG_TARGET_SEC; /* Address: 0x534-0x537 */
163 beuint32_t PTP_TRIG_CTRL; /* Address: 0x538-0x53B */
164 beuint32_t PTP_TRIG_CYC_WIDTH; /* Address: 0x53C-0x53F */
165 beuint32_t PTP_TRIG_CYC_CNT; /* Address: 0x540-0x543 */
166 beuint32_t PTP_TRIG_ITER_TIME; /* Address: 0x544-0x547 */
167 beuint32_t PTP_TRIG_PULSE; /* Address: 0x548-0x54B */
168 uint8_t RESERVED1[0x04]; /* Address: 0x54C-0x54F */
169 beuint32_t PTP_TS_STAT_CTRL; /* Address: 0x550-0x553 */
170 beuint32_t PTP_TS_EVT_0_NANO; /* Address: 0x554-0x557 */
171 beuint32_t PTP_TS_EVT_0_SEC; /* Address: 0x558-0x55B */
172 beuint32_t PTP_TS_EVT_0_PHASE; /* Address: 0x55C-0x55F */
173 beuint32_t PTP_TS_EVT_1_NANO; /* Address: 0x560-0x563 */
174 beuint32_t PTP_TS_EVT_1_SEC; /* Address: 0x564-0x567 */
175 beuint32_t PTP_TS_EVT_1_PHASE; /* Address: 0x568-0x56B */
176 beuint32_t PTP_TS_EVT_2_NANO; /* Address: 0x56C-0x56F */
177 beuint32_t PTP_TS_EVT_2_SEC; /* Address: 0x570-0x573 */
178 beuint32_t PTP_TS_EVT_2_PHASE; /* Address: 0x574-0x577 */
179 beuint32_t PTP_TS_EVT_3_NANO; /* Address: 0x578-0x57B */
180 beuint32_t PTP_TS_EVT_3_SEC; /* Address: 0x57C-0x57F */
181 beuint32_t PTP_TS_EVT_3_PHASE; /* Address: 0x580-0x583 */
182 beuint32_t PTP_TS_EVT_4_NANO; /* Address: 0x584-0x587 */
183 beuint32_t PTP_TS_EVT_4_SEC; /* Address: 0x588-0x58B */
184 beuint32_t PTP_TS_EVT_4_PHASE; /* Address: 0x58C-0x58F */
185 beuint32_t PTP_TS_EVT_5_NANO; /* Address: 0x590-0x593 */
186 beuint32_t PTP_TS_EVT_5_SEC; /* Address: 0x594-0x597 */
187 beuint32_t PTP_TS_EVT_5_PHASE; /* Address: 0x598-0x59B */
188 beuint32_t PTP_TS_EVT_6_NANO; /* Address: 0x59C-0x59F */
189 beuint32_t PTP_TS_EVT_6_SEC; /* Address: 0x5A0-0x5A3 */
190 beuint32_t PTP_TS_EVT_6_PHASE; /* Address: 0x5A4-0x5A7 */
191 beuint32_t PTP_TS_EVT_7_NANO; /* Address: 0x5A8-0x5AB */
192 beuint32_t PTP_TS_EVT_7_SEC; /* Address: 0x5AC-0x5AF */
193 beuint32_t PTP_TS_EVT_7_PHASE; /* Address: 0x5B0-0x5B3 */
194 uint8_t RESERVED2[0x4C]; /* Address: 0x5B4-0x5FF */
195
196} __attribute__((packed));
197
198struct port_control_t {
199 beuint16_t PORT_DEFAULT_VID; /* Address: 0x00-0x01 */
200 beuint16_t PORT_CUSTOM_VID; /* Address: 0x02-0x03 */
201 beuint16_t PORT_AVB_SR_1_VID; /* Address: 0x04-0x05 */
202 beuint16_t PORT_AVB_SR_2_VID; /* Address: 0x06-0x07 */
203 beuint16_t PORT_AVB_SR_1_TYPE; /* Address: 0x08-0x09 */
204 beuint16_t PORT_AVB_SR_2_TYPE; /* Address: 0x0A-0x0B */
205 uint8_t RESERVED0[0x07]; /* Address: 0x0C-0x12 */
206 uint8_t PORT_WOL_STATUS; /* Address: 0x13-0x13 */
207 uint8_t RESERVED1[0x03]; /* Address: 0x14-0x16 */
208 uint8_t PORT_WOL_MASK; /* Address: 0x17-0x17 */
209 uint8_t RESERVED2[0x03]; /* Address: 0x18-0x1A */
210 uint8_t PORT_INT_STATUS; /* Address: 0x1B-0x1B */
211 uint8_t RESERVED3[0x03]; /* Address: 0x1C-0x1E */
212 uint8_t PORT_INT_MASK; /* Address: 0x1F-0x1F */
213 beuint32_t PORT_CTRL; /* Address: 0x20-0x23 */
214 uint8_t RESERVED4[0x0C]; /* Address: 0x24-0x2F */
215 beuint32_t PORT_STATUS; /* Address: 0x30-0x33 */
216 uint8_t RESERVED5[0xCC]; /* Address: 0x34-0xFF */
217
218} __attribute__((packed));
219
220struct port_phy_control_t {
221 beuint16_t PHY_BASIC_CTL; /* Address: 0x100-0x101 */
222 beuint16_t PHY_BASIC_ST; /* Address: 0x102-0x103 */
223 beuint16_t PHY_ID_1; /* Address: 0x104-0x105 */
224 beuint16_t PHY_ID_2; /* Address: 0x106-0x107 */
225 beuint16_t PHY_A_NEG_ADVERT; /* Address: 0x108-0x109 */
226 beuint16_t PHY_A_NEG_LPA; /* Address: 0x10A-0x10B */
227 beuint16_t PHY_A_NEG_EXP; /* Address: 0x10C-0x10D */
228 beuint16_t PHY_A_NEG_NEXT_PG; /* Address: 0x10E-0x10F */
229 beuint16_t PHY_LP_NEXT_PG_ABIL; /* Address: 0x110-0x111 */
230 beuint16_t PHY_GBCR; /* Address: 0x112-0x113 */
231 beuint16_t PHY_GBSR; /* Address: 0x114-0x115 */
232 uint8_t RESERVED0[0x04]; /* Address: 0x116-0x119 */
233 beuint16_t PHY_MMD_SETUP; /* Address: 0x11A-0x11B */
234 beuint16_t PHY_MMD_DATA; /* Address: 0x11C-0x11D */
235 beuint16_t PHY_EXT_STATUS; /* Address: 0x11E-0x11F */
236 uint8_t RESERVED1[0x02]; /* Address: 0x120-0x121 */
237 beuint16_t PHY_REMOTE_LOOPBACK; /* Address: 0x122-0x123 */
238 beuint16_t PHY_LINK_MD; /* Address: 0x124-0x125 */
239 beuint16_t PHY_PMA_STATUS; /* Address: 0x126-0x127 */
240 uint8_t RESERVED2[0x02]; /* Address: 0x128-0x129 */
241 beuint16_t PHY_RXER_CNT; /* Address: 0x12A-0x12B */
242 uint8_t RESERVED3[0x0A]; /* Address: 0x12C-0x135 */
243 beuint16_t PHY_INT; /* Address: 0x136-0x137 */
244 beuint16_t PHY_AUTO_MDIX; /* Address: 0x138-0x139 */
245 uint8_t RESERVED4[0x04]; /* Address: 0x13A-0x13D */
246 beuint16_t PHY_CTL_2; /* Address: 0x13E-0x13F */
247 uint8_t RESERVED5[0xC0]; /* Address: 0x140-0x1FF */
248
249} __attribute__((packed));
250
251struct port_mii_control_t {
252 beuint32_t PORT_XMII_CTRL; /* Address: 0x300-0x303 */
253 uint8_t RESERVED0[0xFC]; /* Address: 0x304-0x3FF */
254
255} __attribute__((packed));
256
257struct port_mac_control_t {
258 beuint32_t PORT_MAC_CTRL; /* Address: 0x400-0x403 */
259 uint8_t RESERVED0[0x0C]; /* Address: 0x404-0x40F */
260 uint8_t PORT_IN_RATE_0; /* Address: 0x410-0x410 */
261 uint8_t PORT_IN_RATE_1; /* Address: 0x411-0x411 */
262 uint8_t PORT_IN_RATE_2; /* Address: 0x412-0x412 */
263 uint8_t PORT_IN_RATE_3; /* Address: 0x413-0x413 */
264 uint8_t PORT_IN_RATE_4; /* Address: 0x414-0x414 */
265 uint8_t PORT_IN_RATE_5; /* Address: 0x415-0x415 */
266 uint8_t PORT_IN_RATE_6; /* Address: 0x416-0x416 */
267 uint8_t PORT_IN_RATE_7; /* Address: 0x417-0x417 */
268 uint8_t RESERVED1[0x08]; /* Address: 0x418-0x41F */
269 uint8_t PORT_OUT_RATE_0; /* Address: 0x420-0x420 */
270 uint8_t PORT_OUT_RATE_1; /* Address: 0x421-0x421 */
271 uint8_t PORT_OUT_RATE_2; /* Address: 0x422-0x422 */
272 uint8_t PORT_OUT_RATE_3; /* Address: 0x423-0x423 */
273 uint8_t RESERVED2[0xDC]; /* Address: 0x424-0x4FF */
274
275} __attribute__((packed));
276
277struct port_mib_control_t {
278 beuint32_t PORT_MIB_CTRL_STAT; /* Address: 0x500-0x503 */
279 beuint32_t PORT_MIB_DATA; /* Address: 0x504-0x507 */
280 uint8_t RESERVED0[0xF8]; /* Address: 0x508-0x5FF */
281
282} __attribute__((packed));
283
284struct port_acl_control_t {
285 beuint32_t PORT_ACL_ACCESS; /* Address: 0x600-0x603 */
286 beuint32_t PORT_ACL_ACCESS2; /* Address: 0x604-0x607 */
287 beuint32_t PORT_ACL_ACCESS3; /* Address: 0x608-0x60B */
288 beuint32_t PORT_ACL_ACCESS4; /* Address: 0x60C-0x60F */
289 beuint32_t PORT_ACL_EN_CTRL; /* Address: 0x610-0x613 */
290 uint8_t RESERVED0[0xEC]; /* Address: 0x614-0x6FF */
291
292} __attribute__((packed));
293
294struct port_sw_ingress_control_t {
295 uint8_t PORT_MIRROR_CTRL; /* Address: 0x800-0x800 */
296 uint8_t PORT_PRIO_CTRL; /* Address: 0x801-0x801 */
297 uint8_t PORT_IN_MAC_CTRL; /* Address: 0x802-0x802 */
298 uint8_t PORT_AUTH_CTRL; /* Address: 0x803-0x803 */
299 beuint32_t PORT_POINTER; /* Address: 0x804-0x807 */
300 beuint32_t PORT_PRIO_QUEUE_MAP; /* Address: 0x808-0x80B */
301 beuint32_t PORT_POLICE_CTRL; /* Address: 0x80C-0x80F */
302 uint8_t RESERVED0[0xF0]; /* Address: 0x810-0x8FF */
303
304} __attribute__((packed));
305
306struct port_sw_egress_control_t {
307 beuint32_t PORT_TX_QUEUE_IDX; /* Address: 0x900-0x903 */
308 beuint32_t PORT_TX_QUEUE_PVID; /* Address: 0x904-0x907 */
309 uint8_t RESERVED0[0x0C]; /* Address: 0x908-0x913 */
310 beuint16_t PORT_TX_QUEUE_CTRL; /* Address: 0x914-0x915 */
311 uint8_t RESERVED1[0xEA]; /* Address: 0x916-0x9FF */
312
313} __attribute__((packed));
314
315struct port_sw_queue_management_control_t {
316 uint8_t RESERVED0[0x04]; /* Address: 0xA00-0xA03 */
317 beuint32_t PORT_VLAN_MEMBERS; /* Address: 0xA04-0xA07 */
318 uint8_t RESERVED1[0xF8]; /* Address: 0xA08-0xAFF */
319
320} __attribute__((packed));
321
322struct port_sw_addr_lue_control_t {
323 uint8_t PORT_LUE_CTRL; /* Address: 0xB00-0xB00 */
324 uint8_t PORT_MSTP_POINTER; /* Address: 0xB01-0xB01 */
325 uint8_t RESERVED0[0x02]; /* Address: 0xB02-0xB03 */
326 uint8_t PORT_MSTP_STATE; /* Address: 0xB04-0xB04 */
327 uint8_t RESERVED1[0xFB]; /* Address: 0xB05-0xBFF */
328
329} __attribute__((packed));
330
331struct global_regs_t {
332 global_control_t ctl; /* Address: 0x0000-0x00FF */
333 global_io_control_t io; /* Address: 0x0100-0x01FF */
334 global_phy_control_t phy; /* Address: 0x0200-0x02FF */
335 global_switch_control_t sw; /* Address: 0x0300-0x03FF */
336 global_lue_control_t lue; /* Address: 0x0400-0x04FF */
337 global_ptp_control_t ptp; /* Address: 0x0500-0x05FF */
338} __attribute__((packed));
339
340struct port_regs_t {
341 port_control_t ctl; /* Address: 0xN000-0xN0FF */
342 port_phy_control_t phy; /* Address: 0xN100-0xN1FF */
343 uint8_t RESERVED0[0x100]; /* Address: 0x200-0x2FF */
344 port_mii_control_t mii; /* Address: 0xN300-0xN3FF */
345 port_mac_control_t mac; /* Address: 0xN400-0xN4FF */
346 port_mib_control_t mib; /* Address: 0xN500-0xN5FF */
347 port_acl_control_t acl; /* Address: 0xN600-0xN6FF */
348 uint8_t RESERVED1[0x100]; /* Address: 0x700-0x7FF */
349 port_sw_ingress_control_t in; /* Address: 0xN800-0xN8FF */
350 port_sw_egress_control_t out; /* Address: 0xN900-0xN9FF */
351 port_sw_queue_management_control_t qmanage; /* Address: 0xNA00-0xNAFF */
352 port_sw_addr_lue_control_t lue; /* Address: 0xNB00-0xNBFF */
353 uint8_t RESERVED2[0x400]; /* Address: 0xC00-0xFFF */
354} __attribute__((packed));
355
356struct ksz_98xx_regs_t {
357 global_regs_t g; /* Address: 0x0000-0x05FF */
358 uint8_t RESERVED0[0xA00]; /* Address: 0x600-0xFFF */
359 port_regs_t p[KSZ98XX_MAX_PORTS]; /* Address: 0xN000-0xNBFF */
360} __attribute__((packed));
361
362#ifdef __cplusplus
363namespace CHIP_ID1 {
364 enum {
365 FAMILY_ID = 0x95,
366 FAMILY_ID_94 = 0x94,
367 FAMILY_ID_95 = 0x95,
368 FAMILY_ID_85 = 0x85,
369 FAMILY_ID_98 = 0x98,
370 FAMILY_ID_88 = 0x88,
371 };
372
373}
374namespace CHIP_ID2 {
375 enum {
376 CHIP_ID_63 = 0x63,
377 CHIP_ID_66 = 0x66,
378 CHIP_ID_67 = 0x67,
379 CHIP_ID_77 = 0x77,
380 CHIP_ID_93 = 0x93,
381 CHIP_ID_96 = 0x96,
382 CHIP_ID_97 = 0x97,
383 };
384
385}
386namespace CHIP_ID3 {
387 enum {
388 SW_REV_Pos = 4,
389 SW_REV_Msk = ( 0xF << SW_REV_Pos),
390 };
391
392}
393namespace PME_CTRL {
394 enum {
395 PME_ENABLE_Pos = 0,
396 PME_ENABLE_Msk = (0x1 << PME_ENABLE_Pos),
397 PME_ENABLE_ENABLED = (1 << PME_ENABLE_Pos),
398 PME_ENABLE_DISABLED = (0 << PME_ENABLE_Pos),
399 PME_POLARITY_Pos = 1,
400 PME_POLARITY_Msk = (0x1 << PME_POLARITY_Pos),
401 PME_POLARITY_HIGH = (1 << PME_POLARITY_Pos),
402 PME_POLARITY_LOW = (0 << PME_POLARITY_Pos),
403 };
404
405 inline uint32_t PME_ENABLE(uint32_t _x)
406 { return ((_x) << PME_ENABLE_Pos); }
407 inline uint32_t PME_POLARITY(uint32_t _x)
408 { return ((_x) << PME_POLARITY_Pos); }
409
410}
411namespace GLOBAL_INT_STATUS {
412 enum {
413 LUE_INT_Pos = 31,
414 LUE_INT_Msk = (0x1 << LUE_INT_Pos),
415 TRIG_TS_INT_Pos = 30,
416 TRIG_TS_INT_Msk = (0x1 << TRIG_TS_INT_Pos),
417 ABP_TIMEOUT_INT_Pos = 29,
418 ABP_TIMEOUT_INT_Msk = (0x1 << ABP_TIMEOUT_INT_Pos),
419 };
420
421}
422namespace GLOBAL_INT_MASK {
423 enum {
424 LUE_INT_Pos = 31,
425 LUE_INT_Msk = (0x1 << LUE_INT_Pos),
426 TRIG_TS_INT_Pos = 30,
427 TRIG_TS_INT_Msk = (0x1 << TRIG_TS_INT_Pos),
428 ABP_TIMEOUT_INT_Pos = 29,
429 ABP_TIMEOUT_INT_Msk = (0x1 << ABP_TIMEOUT_INT_Pos),
430 };
431
432}
433namespace PORT_INT_STATUS {
434 enum {
435 };
436
437 inline uint32_t PORT(uint32_t _x)
438 { return (0x1 << (_x)); }
439
440}
441namespace PORT_INT_MASK {
442 enum {
443 };
444
445 inline uint32_t PORT(uint32_t _x)
446 { return (0x1 << (_x)); }
447
448}
449namespace PHY_INT_STATUS {
450 enum {
451 };
452
453 inline uint32_t PHY(uint32_t _x)
454 { return (0x1 << (_x)); }
455
456}
457namespace PHY_INT_MASK {
458 enum {
459 };
460
461 inline uint32_t PHY(uint32_t _x)
462 { return (0x1 << (_x)); }
463
464}
465
466namespace SERIAL_IO_CTRL {
467 enum {
468 SPI_CLOCK_OUT_RISING_EDGE_Pos = 0,
469 SPI_CLOCK_OUT_RISING_EDGE_Msk = (0x1 << SPI_CLOCK_OUT_RISING_EDGE_Pos),
470 SPI_CLOCK_OUT_RISING_EDGE_TRUE = (0x1 << SPI_CLOCK_OUT_RISING_EDGE_Pos),
471 SPI_CLOCK_OUT_RISING_EDGE_FALSE = (0x1 << SPI_CLOCK_OUT_RISING_EDGE_Pos),
472 SPI_AUTO_EDGE_DETECTION_Pos = 1,
473 SPI_AUTO_EDGE_DETECTION_Msk = (0x1 << SPI_AUTO_EDGE_DETECTION_Pos),
474 SPI_AUTO_EDGE_DETECTION_ENABLED = (0x1 << SPI_AUTO_EDGE_DETECTION_Pos),
475 SPI_AUTO_EDGE_DETECTION_DISABLED = (0x0 << SPI_AUTO_EDGE_DETECTION_Pos),
476 MIIM_PREAMBLE_SUPPRESSION_Pos = 2,
477 MIIM_PREAMBLE_SUPPRESSION_Msk = (0x1 << MIIM_PREAMBLE_SUPPRESSION_Pos),
478 MIIM_PREAMBLE_SUPPRESSION_ENABLED = (0x1 << MIIM_PREAMBLE_SUPPRESSION_Pos),
479 MIIM_PREAMBLE_SUPPRESSION_DISABLED = (0x0 << MIIM_PREAMBLE_SUPPRESSION_Pos),
480 };
481
482 inline uint32_t SPI_CLOCK_OUT_RISING_EDGE(uint32_t _x)
483 { return (((_x) << SPI_CLOCK_OUT_RISING_EDGE_Pos) & SPI_CLOCK_OUT_RISING_EDGE_Msk); }
484 inline uint32_t SPI_AUTO_EDGE_DETECTION(uint32_t _x)
485 { return ((_x) << SPI_AUTO_EDGE_DETECTION_Pos); }
486 inline uint32_t MIIM_PREAMBLE_SUPPRESSION(uint32_t _x)
487 { return ((_x) << MIIM_PREAMBLE_SUPPRESSION_Pos); }
488
489}
490namespace OUTPUT_CLOCK_CTRL {
491 enum {
492 REFCLKO_IS_125MHZ_Pos = 0,
493 REFCLKO_IS_125MHZ_Msk = (0x1 << REFCLKO_IS_125MHZ_Pos),
494 REFCLKO_IS_125MHZ_TRUE = (0x1 << REFCLKO_IS_125MHZ_Pos),
495 REFCLKO_IS_125MHZ_FALSE = (0x0 << REFCLKO_IS_125MHZ_Pos),
496 REFCLKO_Pos = 1,
497 REFCLKO_Msk = (0x1 << REFCLKO_Pos),
498 REFCLKO_ENABLED = (0x1 << REFCLKO_Pos),
499 REFCLKO_DISABLED = (0x0 << REFCLKO_Pos),
500 };
501
502 inline uint32_t REFCLKO_IS_125MHZ(uint32_t _x)
503 { return ((_x) << REFCLKO_IS_125MHZ_Pos); }
504 inline uint32_t REFCLKO(uint32_t _x)
505 { return ((_x) << REFCLKO_Pos); }
506
507}
508namespace IBA_CTRL {
509 enum {
510 IBA_FRAME_TPID_Pos = 0,
511 IBA_FRAME_TPID_Msk = (0xFFFF << IBA_FRAME_TPID_Pos),
512 IBA_PORT_Pos = 16,
513 IBA_PORT_Msk = (0x7 << IBA_PORT_Pos),
514 IBA_RESP_PRIO_Pos = 22,
515 IBA_RESP_PRIO_Msk = (0x3 << IBA_RESP_PRIO_Pos),
516 IBA_RESET_Pos = 29,
517 IBA_RESET_Msk = (0x1 << IBA_RESET_Pos),
518 IBA_DA_MATCH_Pos = 30,
519 IBA_DA_MATCH_Msk = (0x1 << IBA_DA_MATCH_Pos),
520 IBA_DA_MATCH_ENABLED = (0x1 << IBA_DA_MATCH_Pos),
521 IBA_DA_MATCH_DISABLED = (0x0 << IBA_DA_MATCH_Pos),
522 IBA_ENABLE_Pos = 31,
523 IBA_ENABLE_Msk = (0x1 << IBA_ENABLE_Pos),
524 IBA_ENABLE_ENABLED = (0x1 << IBA_ENABLE_Pos),
525 IBA_ENABLE_DISABLED = (0x0 << IBA_ENABLE_Pos),
526 };
527
528 inline uint32_t IBA_FRAME_TPID(uint32_t _x)
529 { return ((_x) << IBA_FRAME_TPID_Pos); }
530 inline uint32_t IBA_PORT(uint32_t _x)
531 { return ((_x) << IBA_PORT_Pos); }
532 inline uint32_t IBA_RESP_PRIO(uint32_t _x)
533 { return ((_x) << IBA_RESP_PRIO_Pos); }
534 inline uint32_t IBA_RESET(uint32_t _x)
535 { return ((_x) << IBA_RESET_Pos); }
536 inline uint32_t IBA_DA_MATCH(uint32_t _x)
537 { return (((_x) << IBA_DA_MATCH_Pos) & IBA_DA_MATCH_Msk); }
538 inline uint32_t IBA_ENABLE(uint32_t _x)
539 { return (((_x) << IBA_ENABLE_Pos) & IBA_ENABLE_Msk); }
540
541}
542namespace APB_TIMEOUT {
543 enum {
544 APB_TIMEOUT_ACK_Pos = 31,
545 APB_TIMEOUT_ACK_Msk = (0x1 << APB_TIMEOUT_ACK_Pos),
546 };
547
548}
549namespace IO_DRIVE_STRENGTH {
550 enum {
551 LO_SPEED_DRIVE_STRENGTH_Pos = 0,
552 LO_SPEED_DRIVE_STRENGTH_Msk = (0x7 << LO_SPEED_DRIVE_STRENGTH_Pos),
553 HI_SPEED_DRIVE_STRENGTH_Pos = 4,
554 HI_SPEED_DRIVE_STRENGTH_Msk = (0x7 << HI_SPEED_DRIVE_STRENGTH_Pos),
555 };
556
557 inline uint32_t LO_SPEED_DRIVE_STRENGTH(uint32_t _x)
558 { return (((_x) << LO_SPEED_DRIVE_STRENGTH_Pos) & LO_SPEED_DRIVE_STRENGTH_Msk); }
559 inline uint32_t HI_SPEED_DRIVE_STRENGTH(uint32_t _x)
560 { return (((_x) << HI_SPEED_DRIVE_STRENGTH_Pos) & HI_SPEED_DRIVE_STRENGTH_Msk); }
561
562}
563namespace IBA_STATUS {
564 enum {
565 IBA_CMD_LOC_Pos = 0,
566 IBA_CMD_LOC_Msk = (0x7F << IBA_CMD_LOC_Pos),
567 IBA_OVERSIZE_ERROR_Pos = 10,
568 IBA_OVERSIZE_ERROR_Msk = (0x1 << IBA_OVERSIZE_ERROR_Pos),
569 IBA_CMD_ERROR_Pos = 11,
570 IBA_CMD_ERROR_Msk = (0x1 << IBA_CMD_ERROR_Pos),
571 IBA_CODE_ERROR_Pos = 12,
572 IBA_CODE_ERROR_Msk = (0x1 << IBA_CMD_ERROR_Pos),
573 IBA_FMT_MISMATCH_Pos = 13,
574 IBA_FMT_MISMATCH_Msk = (0x1 << IBA_FMT_MISMATCH_Pos),
575 IBA_DA_MISMATCH_Pos = 14,
576 IBA_DA_MISMATCH_Msk = (0x1 << IBA_DA_MISMATCH_Pos),
577 IBA_EXEC_DONE_Pos = 29,
578 IBA_EXEC_DONE_Msk = (0x1 << IBA_EXEC_DONE_Pos),
579 IBA_RESP_Pos = 30,
580 IBA_RESP_Msk = (0x1 << IBA_RESP_Pos),
581 IBA_REQ_Pos = 31,
582 IBA_REQ_Msk = (0x1 << IBA_REQ_Pos),
583 };
584
585 inline uint32_t IBA_CMD_LOC(uint32_t _x)
586 { return (((_x) << IBA_CMD_LOC_Pos) & IBA_CMD_LOC_Msk); }
587
588}
589namespace IBA_STATES {
590 enum {
591 IBA_FMT_ID_Pos = 0,
592 IBA_FMT_ID_Msk = (0xFFFF << IBA_FMT_ID_Pos),
593 IBA_PACKET_SIZE_Pos = 16,
594 IBA_PACKET_SIZE_Msk = (0x7F << IBA_PACKET_SIZE_Pos),
595 IBA_RESP_STATE_Pos = 26,
596 IBA_RESP_STATE_Msk = (0x3 << IBA_RESP_STATE_Pos),
597 IBA_CMD_STATE_Pos = 28,
598 IBA_CMD_STATE_Msk = (0x3 << IBA_CMD_STATE_Pos),
599 IBA_BUF_STATE_Pos = 30,
600 IBA_BUF_STATE_Msk = (0x3 << IBA_BUF_STATE_Pos),
601 };
602
603}
604namespace IBA_RESULT {
605 enum {
606 IBA_RETRY_CNT_Pos = 0,
607 IBA_RETRY_CNT_Msk = (0x3F << IBA_RETRY_CNT_Pos),
608 IBA_SIZE_Pos = 24,
609 IBA_SIZE_Msk = (0xFF << IBA_SIZE_Pos),
610 };
611
612}
613namespace LED_OVERRIDE {
614 enum {
615 };
616
617 inline uint32_t LED_GPO(uint32_t _x)
618 { return (1 << (_x)); }
619
620}
621namespace LED_OUTPUT {
622 enum {
623 };
624
625 inline uint32_t HIGH(uint32_t _x)
626 { return (1 << (_x)); }
627
628}
629
630namespace POWER_MANAGEMENT_CTRL {
631 enum {
632 MODE_Pos = 3,
633 MODE_Msk = (0x3 << MODE_Pos),
634 MODE_NORMAL = (0x0 << MODE_Pos),
635 MODE_ENERGY_DETECT_POWER_DOWN = (0x1 << MODE_Pos),
636 MODE_SOFT_POWER_DOWN = (0x2 << MODE_Pos),
637 PLL_POWER_DOWN_Pos = 5,
638 PLL_POWER_DOWN_Msk = (0x1 << MODE_Pos),
639 PLL_POWER_DOWN_NORMAL = (0x0 << MODE_Pos),
640 PLL_POWER_DOWN_PLL_DISABLED = (0x1 << MODE_Pos),
641 };
642
643}
644
645namespace SW_OPERATION {
646 enum {
647 SW_START_Pos = 0,
648 SW_START_Msk = (0x1 << SW_START_Pos),
649 SW_START_ENABLED = (0x1 << SW_START_Pos),
650 SW_START_DISABLED = (0x1 << SW_START_Pos),
651 SW_RESET_Pos = 1,
652 SW_RESET_Msk = (0x1 << SW_RESET_Pos),
653 SW_RESET_RESET = (0x1 << SW_RESET_Pos),
654 SW_DOUBLE_TAG_Pos = 2,
655 SW_DOUBLE_TAG_Msk = (0x1 << SW_DOUBLE_TAG_Pos),
656 SW_DOUBLE_TAG_ENABLED = (0x1 << SW_DOUBLE_TAG_Pos),
657 SW_DOUBLE_TAG_DISABLED = (0x0 << SW_DOUBLE_TAG_Pos),
658 };
659
660}
661namespace SW_MTU {
662 enum {
663 MTU_Pos = 0,
664 MTU_Msk = (0x3FFF << MTU_Pos),
665 };
666
667 inline uint32_t MTU(uint32_t _x)
668 { return (((_x) << MTU_Pos) & MTU_Msk); }
669
670}
671namespace SW_ISP_TPID {
672 enum {
673 ISP_TPID_Pos = 0,
674 ISP_TPID_Msk = (0xFFFF << ISP_TPID_Pos),
675 };
676
677 inline uint32_t ISP_TPID(uint32_t _x)
678 { return (((_x) << ISP_TPID_Pos) & ISP_TPID_Msk); }
679
680}
681namespace SW_HSR_TPID {
682 enum {
683 HSR_TPID_Pos = 0,
684 HSR_TPID_Msk = (0xFFFF << HSR_TPID_Pos),
685 };
686
687 inline uint32_t ISP_TPID(uint32_t _x)
688 { return (((_x) << HSR_TPID_Pos) & HSR_TPID_Msk); }
689
690}
691namespace SW_AVB_STRATEGY {
692 enum {
693 POLICING_CREDIT_ACCT_Pos = 0,
694 POLICING_CREDIT_ACCT_Msk = (0x1 << POLICING_CREDIT_ACCT_Pos),
695 SHAPING_CREDIT_ACCT_Pos = 1,
696 SHAPING_CREDIT_ACCT_Msk = (0x1 << SHAPING_CREDIT_ACCT_Pos),
697 };
698
699}
700namespace SW_LUE_CTRL {
701 enum {
702 AGE_PERIOD_Pos = 0,
703 AGE_PERIOD_Msk = (0xFF << AGE_PERIOD_Pos),
704 PRIO_Pos = 8,
705 PRIO_Msk = (0x3 << PRIO_Pos),
706 PRIO_DST_ADDR = (0x0 << PRIO_Pos),
707 PRIO_SRC_ADDR = (0x1 << PRIO_Pos),
708 PRIO_HIGHEST_DA_SA = (0x2 << PRIO_Pos),
709 PRIO_LOWEST_DA_SA = (0x3 << PRIO_Pos),
710 FLUSH_OPTION_Pos = 10,
711 FLUSH_OPTION_Msk = (0x3 << FLUSH_OPTION_Pos),
712 FLUSH_OPTION_NONE = (0x0 << FLUSH_OPTION_Pos),
713 FLUSH_OPTION_DYN_MAC = (0x1 << FLUSH_OPTION_Pos),
714 FLUSH_OPTION_STA_MAC = (0x2 << FLUSH_OPTION_Pos),
715 FLUSH_OPTION_BOTH = (0x3 << FLUSH_OPTION_Pos),
716 EGRESS_VLAN_FILTER_STA_Pos = 12,
717 EGRESS_VLAN_FILTER_STA_Msk = (0x3 << EGRESS_VLAN_FILTER_STA_Pos),
718 EGRESS_VLAN_FILTER_STA_ENABLED = (0x1 << EGRESS_VLAN_FILTER_STA_Pos),
719 EGRESS_VLAN_FILTER_STA_DISABLED = (0x0 << EGRESS_VLAN_FILTER_STA_Pos),
720 EGRESS_VLAN_FILTER_DYN_Pos = 13,
721 EGRESS_VLAN_FILTER_DYN_Msk = (0x1 << EGRESS_VLAN_FILTER_DYN_Pos),
722 EGRESS_VLAN_FILTER_DYN_ENABLED = (0x1 << EGRESS_VLAN_FILTER_DYN_Pos),
723 EGRESS_VLAN_FILTER_DYN_DISABLED = (0x0 << EGRESS_VLAN_FILTER_DYN_Pos),
724 TRAP_DOUBLE_TAG_Pos = 14,
725 TRAP_DOUBLE_TAG_Msk = (0x1 << TRAP_DOUBLE_TAG_Pos),
726 TRAP_DOUBLE_TAG_ENABLED = (0x1 << TRAP_DOUBLE_TAG_Pos),
727 TRAP_DOUBLE_TAG_DISABLED = (0x0 << TRAP_DOUBLE_TAG_Pos),
728 LINK_DOWN_FLUSH_Pos = 16,
729 LINK_DOWN_FLUSH_Msk = (0x1 << LINK_DOWN_FLUSH_Pos),
730 LINK_DOWN_FLUSH_ENABLED = (0x1 << LINK_DOWN_FLUSH_Pos),
731 LINK_DOWN_FLUSH_DISABLED = (0x0 << LINK_DOWN_FLUSH_Pos),
732 FAST_AGING_Pos = 17,
733 FAST_AGING_Msk = (0x1 << FAST_AGING_Pos),
734 FAST_AGING_ENABLED = (0x1 << FAST_AGING_Pos),
735 FAST_AGING_DISABLED = (0x0 << FAST_AGING_Pos),
736 AGING_Pos = 18,
737 AGING_Msk = (0x1 << AGING_Pos),
738 AGING_ENABLED = (0x1 << AGING_Pos),
739 AGING_DISABLED = (0x0 << AGING_Pos),
740 FWD_MCAST_SRC_ADDR_Pos = 19,
741 FWD_MCAST_SRC_ADDR_Msk = (0x1 << FWD_MCAST_SRC_ADDR_Pos),
742 FWD_MCAST_SRC_ADDR_ENABLED = (0x1 << FWD_MCAST_SRC_ADDR_Pos),
743 FWD_MCAST_SRC_ADDR_DISABLED = (0x0 << FWD_MCAST_SRC_ADDR_Pos),
744 FLUSH_MSTP_TABLE_Pos = 20,
745 FLUSH_MSTP_TABLE_Msk = (0x1 << FLUSH_MSTP_TABLE_Pos),
746 FLUSH_MSTP_TABLE_ENABLED = (0x1 << FLUSH_MSTP_TABLE_Pos),
747 FLUSH_MSTP_TABLE_DISABLED = (0x0 << FLUSH_MSTP_TABLE_Pos),
748 FLUSH_STP_TABLE_Pos = 21,
749 FLUSH_STP_TABLE_Msk = (0x1 << FLUSH_STP_TABLE_Pos),
750 FLUSH_STP_TABLE_ENABLED = (0x1 << FLUSH_STP_TABLE_Pos),
751 FLUSH_STP_TABLE_DISABLED = (0x0 << FLUSH_STP_TABLE_Pos),
752 SRC_ADDR_FILTER_Pos = 22,
753 SRC_ADDR_FILTER_Msk = (0x1 << SRC_ADDR_FILTER_Pos),
754 SRC_ADDR_FILTER_ENABLED = (0x1 << SRC_ADDR_FILTER_Pos),
755 SRC_ADDR_FILTER_DISABLED = (0x0 << SRC_ADDR_FILTER_Pos),
756 UNICAST_LEARN_DISABLE_Pos = 23,
757 UNICAST_LEARN_DISABLE_Msk = (0x1 << UNICAST_LEARN_DISABLE_Pos),
758 UNICAST_LEARN_DISABLE_ENABLED = (0x1 << UNICAST_LEARN_DISABLE_Pos),
759 UNICAST_LEARN_DISABLE_DISABLED = (0x0 << UNICAST_LEARN_DISABLE_Pos),
760 HASH_OPTION_Pos = 24,
761 HASH_OPTION_Msk = (0x3 << HASH_OPTION_Pos),
762 HASH_OPTION_CRC = (0x1 << HASH_OPTION_Pos),
763 HASH_OPTION_XOR = (0x2 << HASH_OPTION_Pos),
764 HASH_OPTION_DIRECT = (0x3 << HASH_OPTION_Pos),
765 RESV_MCAST_Pos = 26,
766 RESV_MCAST_Msk = (0x1 << RESV_MCAST_Pos),
767 RESV_MCAST_ENABLED = (0x1 << RESV_MCAST_Pos),
768 RESV_MCAST_DISABLED = (0x0 << RESV_MCAST_Pos),
769 AGE_CNT_Pos = 27,
770 AGE_CNT_Msk = (0x7 << AGE_CNT_Pos),
771 DROP_INVALID_VID_Pos = 30,
772 DROP_INVALID_VID_Msk = (0x1 << DROP_INVALID_VID_Pos),
773 DROP_INVALID_VID_ENABLED = (0x1 << DROP_INVALID_VID_Pos),
774 DROP_INVALID_VID_DISABLED = (0x0 << DROP_INVALID_VID_Pos),
775 VLAN_ENABLE_Pos = 31,
776 VLAN_ENABLE_Msk = (0x1 << VLAN_ENABLE_Pos),
777 VLAN_ENABLE_ENABLED = (0x1 << VLAN_ENABLE_Pos),
778 VLAN_ENABLE_DISABLED = (0x0 << VLAN_ENABLE_Pos),
779 };
780
781 inline uint32_t AGE_PERIOD(uint32_t _x)
782 { return (((_x) << AGE_PERIOD_Pos) & AGE_PERIOD_Msk); }
783 inline uint32_t AGE_CNT(uint32_t _x)
784 { return (((_x) << AGE_CNT_Pos) & AGE_CNT_Msk); }
785
786}
787namespace SW_LUE_INT_STATUS {
788 enum {
789 WRITE_FAIL_Pos = 0,
790 WRITE_FAIL_Msk = (0x1 << WRITE_FAIL_Pos),
791 WRITE_FAIL_ENABLED = (0x1 << WRITE_FAIL_Pos),
792 WRITE_FAIL_DISABLED = (0x0 << WRITE_FAIL_Pos),
793 ALMOST_FULL_Pos = 1,
794 ALMOST_FULL_Msk = (0x1 << ALMOST_FULL_Pos),
795 ALMOST_FULL_ENABLED = (0x1 << ALMOST_FULL_Pos),
796 ALMOST_FULL_DISABLED = (0x0 << ALMOST_FULL_Pos),
797 LEARN_FAIL_Pos = 2,
798 LEARN_FAIL_Msk = (0x1 << LEARN_FAIL_Pos),
799 LEARN_FAIL_ENABLED = (0x1 << LEARN_FAIL_Pos),
800 LEARN_FAIL_DISABLED = (0x0 << LEARN_FAIL_Pos),
801 };
802
803}
804namespace SW_LUE_INT_MASK {
805 enum {
806 WRITE_FAIL_Pos = 0,
807 WRITE_FAIL_Msk = (0x1 << WRITE_FAIL_Pos),
808 WRITE_FAIL_ENABLED = (0x0 << WRITE_FAIL_Pos),
809 WRITE_FAIL_DISABLED = (0x1 << WRITE_FAIL_Pos),
810 ALMOST_FULL_Pos = 1,
811 ALMOST_FULL_Msk = (0x1 << ALMOST_FULL_Pos),
812 ALMOST_FULL_ENABLED = (0x0 << ALMOST_FULL_Pos),
813 ALMOST_FULL_DISABLED = (0x1 << ALMOST_FULL_Pos),
814 LEARN_FAIL_Pos = 2,
815 LEARN_FAIL_Msk = (0x1 << LEARN_FAIL_Pos),
816 LEARN_FAIL_ENABLED = (0x0 << LEARN_FAIL_Pos),
817 LEARN_FAIL_DISABLED = (0x1 << LEARN_FAIL_Pos),
818 };
819
820}
821namespace SW_LUE_INDEX_WRITE {
822 enum {
823 FAIL_WRITE_ALMOST_FULL_Pos = 0,
824 FAIL_WRITE_ALMOST_FULL_Msk = (0xFFF << FAIL_WRITE_ALMOST_FULL_Pos),
825 };
826
827}
828namespace SW_LUE_INDEX_LEARN {
829 enum {
830 FAIL_LEARN_Pos = 0,
831 FAIL_LEARN_Msk = (0x3FF << FAIL_LEARN_Pos),
832 };
833
834}
835namespace SW_LUE_INDEX_CPU {
836 enum {
837 CPU_ACCESS_Pos = 0,
838 CPU_ACCESS_Msk = (0x3FF << CPU_ACCESS_Pos),
839 };
840
841}
842namespace SW_UNK_UCAST_CTRL {
843 enum {
844 FWD_PORTS_Pos = 0,
845 FWD_PORTS_Msk = (0xFF << FWD_PORTS_Pos),
846 FWD_Pos = 31,
847 FWD_Msk = (0x1 << FWD_Pos),
848 FWD_ENABLED = (0x1 << FWD_Pos),
849 FWD_DISABLED = (0x0 << FWD_Pos),
850 };
851
852 inline uint32_t FWD_PORT(uint32_t _x)
853 { return (((_x) << FWD_PORTS_Pos) & FWD_PORTS_Msk); }
854
855}
856namespace SW_UNK_MCAST_CTRL {
857 enum {
858 FWD_PORTS_Pos = 0,
859 FWD_PORTS_Msk = (0xFF << FWD_PORTS_Pos),
860 FWD_Pos = 31,
861 FWD_Msk = (0x1 << FWD_Pos),
862 FWD_ENABLED = (0x1 << FWD_Pos),
863 FWD_DISABLED = (0x0 << FWD_Pos),
864 };
865
866 inline uint32_t FWD_PORT(uint32_t _x)
867 { return (((_x) << FWD_PORTS_Pos) & FWD_PORTS_Msk); }
868
869}
870namespace SW_UNK_VID_CTRL {
871 enum {
872 FWD_PORTS_Pos = 0,
873 FWD_PORTS_Msk = (0xFF << FWD_PORTS_Pos),
874 FWD_Pos = 31,
875 FWD_Msk = (0x1 << FWD_Pos),
876 FWD_ENABLED = (0x1 << FWD_Pos),
877 FWD_DISABLED = (0x0 << FWD_Pos),
878 };
879
880 inline uint32_t FWD_PORT(uint32_t _x)
881 { return (((_x) << FWD_PORTS_Pos) & FWD_PORTS_Msk); }
882
883}
884namespace SW_MAC_CTRL {
885 enum {
886 AGGR_BACKOFF_Pos = 24,
887 AGGR_BACKOFF_Msk = (0x1 << AGGR_BACKOFF_Pos),
888 AGGR_BACKOFF_ENABLED = (0x1 << AGGR_BACKOFF_Pos),
889 AGGR_BACKOFF_DISABLED = (0x0 << AGGR_BACKOFF_Pos),
890 PAUSE_UNH_MODE_Pos = 25,
891 PAUSE_UNH_MODE_Msk = (0x1 << PAUSE_UNH_MODE_Pos),
892 PAUSE_UNH_MODE_DROP_EITHER = (0x1 << PAUSE_UNH_MODE_Pos),
893 PAUSE_UNH_MODE_DROP_BOTH = (0x0 << PAUSE_UNH_MODE_Pos),
894 CHECK_LENGTH_Pos = 27,
895 CHECK_LENGTH_Msk = (0x1 << CHECK_LENGTH_Pos),
896 CHECK_LENGTH_ENABLED = (0x1 << CHECK_LENGTH_Pos),
897 CHECK_LENGTH_DISABLED = (0x0 << CHECK_LENGTH_Pos),
898 NEW_BACKOFF_Pos = 31,
899 NEW_BACKOFF_Msk = (0x1 << NEW_BACKOFF_Pos),
900 NEW_BACKOFF_ENABLED = (0x1 << NEW_BACKOFF_Pos),
901 NEW_BACKOFF_DISABLED = (0x0 << NEW_BACKOFF_Pos),
902 PASS_SHORT_FRAME_Pos = 16,
903 PASS_SHORT_FRAME_Msk = (0x1 << PASS_SHORT_FRAME_Pos),
904 PASS_SHORT_FRAME_ENABLED = (0x1 << PASS_SHORT_FRAME_Pos),
905 PASS_SHORT_FRAME_DISABLED = (0x0 << PASS_SHORT_FRAME_Pos),
906 LEGAL_PACKET_SIZE_CHECK_Pos = 17,
907 LEGAL_PACKET_SIZE_CHECK_Msk = (0x1 << LEGAL_PACKET_SIZE_CHECK_Pos),
908 LEGAL_PACKET_SIZE_CHECK_ENABLED = (0x0 << LEGAL_PACKET_SIZE_CHECK_Pos),
909 LEGAL_PACKET_SIZE_CHECK_DISABLED = (0x1 << LEGAL_PACKET_SIZE_CHECK_Pos),
910 JUMBO_PACKET_Pos = 18,
911 JUMBO_PACKET_Msk = (0x1 << JUMBO_PACKET_Pos),
912 JUMBO_PACKET_ENABLED = (0x1 << JUMBO_PACKET_Pos),
913 JUMBO_PACKET_DISABLED = (0x0 << JUMBO_PACKET_Pos),
914 NO_EXC_COLLISION_DROP_Pos = 19,
915 NO_EXC_COLLISION_DROP_Msk = (0x1 << NO_EXC_COLLISION_DROP_Pos),
916 NO_EXC_COLLISION_DROP_ENABLED = (0x1 << NO_EXC_COLLISION_DROP_Pos),
917 NO_EXC_COLLISION_DROP_DISABLED = (0x0 << NO_EXC_COLLISION_DROP_Pos),
918 FAIR_FLOW_CTRL_Pos = 20,
919 FAIR_FLOW_CTRL_Msk = (0x1 << FAIR_FLOW_CTRL_Pos),
920 FAIR_FLOW_CTRL_ENABLED = (0x1 << FAIR_FLOW_CTRL_Pos),
921 FAIR_FLOW_CTRL_DISABLED = (0x0 << FAIR_FLOW_CTRL_Pos),
922 BACK_PRESSURE_Pos = 21,
923 BACK_PRESSURE_Msk = (0x1 << BACK_PRESSURE_Pos),
924 BACK_PRESSURE_CARRIER_SENSE = (0x1 << BACK_PRESSURE_Pos),
925 BACK_PRESSURE_COLLISION = (0x0 << BACK_PRESSURE_Pos),
926 MCAST_STORM_PROT_Pos = 22,
927 MCAST_STORM_PROT_Msk = (0x1 << MCAST_STORM_PROT_Pos),
928 MCAST_STORM_PROT_ENABLED = (0x0 << MCAST_STORM_PROT_Pos),
929 MCAST_STORM_PROT_DISABLED = (0x1 << MCAST_STORM_PROT_Pos),
930 NULL_VID_REPLACE_Pos = 11,
931 NULL_VID_REPLACE_Msk = (0x1 << NULL_VID_REPLACE_Pos),
932 NULL_VID_REPLACE_ENABLED = (0x1 << NULL_VID_REPLACE_Pos),
933 NULL_VID_REPLACE_DISABLED = (0x0 << NULL_VID_REPLACE_Pos),
934 BCAST_STORM_RATE_Pos = 0,
935 BCAST_STORM_RATE_Msk = (0x7FF << BCAST_STORM_RATE_Pos),
936 BCAST_STORM_RATE_DISABLED = (0x0 << BCAST_STORM_RATE_Pos),
937 };
938
939 inline uint32_t BCAST_STORM_RATE(uint32_t _x)
940 { return (((_x) << BCAST_STORM_RATE_Pos & BCAST_STORM_RATE_Msk)); }
941
942}
943namespace SW_MAC_CTRL2 {
944 enum {
945 PASS_PAUSE_Pos = 24,
946 PASS_PAUSE_Msk = (0x1 << PASS_PAUSE_Pos),
947 PASS_PAUSE_ENABLED = (0x1 << PASS_PAUSE_Pos),
948 PASS_PAUSE_DISABLED = (0x0 << PASS_PAUSE_Pos),
949 INGRESS_RATE_LIMIT_PERIOD_Pos = 20,
950 INGRESS_RATE_LIMIT_PERIOD_Msk = (0x3 << INGRESS_RATE_LIMIT_PERIOD_Pos),
951 INGRESS_RATE_LIMIT_PERIOD_16MS = (0x0 << INGRESS_RATE_LIMIT_PERIOD_Pos),
952 INGRESS_RATE_LIMIT_PERIOD_64MS = (0x1 << INGRESS_RATE_LIMIT_PERIOD_Pos),
953 INGRESS_RATE_LIMIT_PERIOD_256MS = (0x2 << INGRESS_RATE_LIMIT_PERIOD_Pos),
954 EGRESS_RATE_LIMIT_BY_Pos = 19,
955 EGRESS_RATE_LIMIT_BY_Msk = (0x1 << EGRESS_RATE_LIMIT_BY_Pos),
956 EGRESS_RATE_LIMIT_BY_QUEUE = (0x1 << EGRESS_RATE_LIMIT_BY_Pos),
957 EGRESS_RATE_LIMIT_BY_PORT = (0x0 << EGRESS_RATE_LIMIT_BY_Pos),
958 MIB_COUNTER_FLUSH_Pos = 15,
959 MIB_COUNTER_FLUSH_Msk = (0x1 << MIB_COUNTER_FLUSH_Pos),
960 MIB_COUNTER_FLUSH_ENABLED = (0x1 << MIB_COUNTER_FLUSH_Pos),
961 MIB_COUNTER_FLUSH_DISABLED = (0x0 << MIB_COUNTER_FLUSH_Pos),
962 MIB_COUNTER_FREEZE_Pos = 14,
963 MIB_COUNTER_FREEZE_Msk = (0x1 << MIB_COUNTER_FREEZE_Pos),
964 MIB_COUNTER_FREEZE_ENABLED = (0x1 << MIB_COUNTER_FREEZE_Pos),
965 MIB_COUNTER_FREEZE_DISABLED = (0x0 << MIB_COUNTER_FREEZE_Pos),
966 };
967
968}
969namespace SW_MAC_802_1P_MAP {
970 enum {
971 };
972
973 inline uint32_t PCP_VAL_Pos(uint32_t _x)
974 { return (28-((!(_x&1))*4)-(((_x>>1)&0x3)*8)); }
975 inline uint32_t PCP_VAL_Msk(uint32_t _x)
976 { return (0xF << PCP_VAL_Pos(_x)); }
977 inline uint32_t PCP_VAL(uint32_t _x, uint32_t _val)
978 { return (((_val) << PCP_VAL_Pos(_x) & PCP_VAL_Msk(_x))); }
979
980}
981namespace SW_MAC_TOS_CTRL {
982 enum {
983 TOS_DCSP_REMAP_Pos = 0,
984 TOS_DCSP_REMAP_Msk = (0x1 << TOS_DCSP_REMAP_Pos),
985 TOS_DCSP_REMAP_ENABLED = (0x1 << TOS_DCSP_REMAP_Pos),
986 TOS_DCSP_REMAP_DISABLED = (0x0 << TOS_DCSP_REMAP_Pos),
987 TOS_DCSP_REMARK_Pos = 1,
988 TOS_DCSP_REMARK_Msk = (0x1 << TOS_DCSP_REMARK_Pos),
989 TOS_DCSP_REMARK_ENABLED = (0x1 << TOS_DCSP_REMARK_Pos),
990 TOS_DCSP_REMARK_DISABLED = (0x0 << TOS_DCSP_REMARK_Pos),
991 };
992
993}
994namespace SW_MAC_TOS_PRIO_31 {
995 enum {
996 };
997
998 inline uint32_t REG(uint32_t _x)
999 { return ((_x>>1)&0x1F); }
1000 inline uint32_t DCSP_VAL_Pos(uint32_t _x)
1001 { return (((_x&1))*4); }
1002 inline uint32_t DCSP_VAL_Msk(uint32_t _x)
1003 { return (0xF << DCSP_VAL_Pos(_x)); }
1004 inline uint32_t DCSP_VAL(uint32_t _x, uint32_t _val)
1005 { return (((_val) << DCSP_VAL_Pos(_x) & DCSP_VAL_Msk(_x))); }
1006
1007}
1008namespace SW_MRI_CTRL {
1009 enum {
1010 MIRROR_FILTER_Pos = 0,
1011 MIRROR_FILTER_Msk = (0x1 << MIRROR_FILTER_Pos),
1012 MIRROR_FILTER_AND = (0x1 << MIRROR_FILTER_Pos),
1013 MIRROR_FILTER_OR = (0x0 << MIRROR_FILTER_Pos),
1014 IPV6_MLD_SNOOP_Pos = 2,
1015 IPV6_MLD_SNOOP_Msk = (0x1 << IPV6_MLD_SNOOP_Pos),
1016 IPV6_MLD_SNOOP_ENABLED = (0x1 << IPV6_MLD_SNOOP_Pos),
1017 IPV6_MLD_SNOOP_DISABLED = (0x0 << IPV6_MLD_SNOOP_Pos),
1018 IPV6_MLD_OPTION_Pos = 3,
1019 IPV6_MLD_OPTION_Msk = (0x1 << IPV6_MLD_OPTION_Pos),
1020 IPV6_MLD_OPTION_ENABLED = (0x1 << IPV6_MLD_OPTION_Pos),
1021 IPV6_MLD_OPTION_DISABLED = (0x0 << IPV6_MLD_OPTION_Pos),
1022 IGMP_SNOOP_Pos = 6,
1023 IGMP_SNOOP_Msk = (0x1 << IGMP_SNOOP_Pos),
1024 IGMP_SNOOP_ENABLED = (0x1 << IGMP_SNOOP_Pos),
1025 IGMP_SNOOP_DISABLED = (0x0 << IGMP_SNOOP_Pos),
1026 };
1027
1028}
1029namespace SW_WRED_DSCP_COLOR {
1030 enum {
1031 GREEN_Pos = 0,
1032 GREEN_Msk = (0x3 << GREEN_Pos),
1033 YELLOW_Pos = 2,
1034 YELLOW_Msk = (0x3 << YELLOW_Pos),
1035 RED_Pos = 4,
1036 RED_Msk = (0x3 << RED_Pos),
1037 NO_COLOR_Pos = 6,
1038 NO_COLOR_Msk = (0x3 << NO_COLOR_Pos),
1039 };
1040
1041 inline uint32_t GREEN(uint32_t _x)
1042 { return (((_x) << GREEN_Pos) & GREEN_Msk); }
1043 inline uint32_t YELLOW(uint32_t _x)
1044 { return (((_x) << YELLOW_Pos) & YELLOW_Msk); }
1045 inline uint32_t RED(uint32_t _x)
1046 { return (((_x) << RED_Pos) & RED_Msk); }
1047 inline uint32_t NO_COLOR(uint32_t _x)
1048 { return (((_x) << NO_COLOR_Pos) & NO_COLOR_Msk); }
1049
1050}
1051namespace SW_QM_CTRL {
1052 enum {
1053 UNICAST_VLAN_BOUNDARY_Pos = 1,
1054 UNICAST_VLAN_BOUNDARY_Msk = (0x1 << UNICAST_VLAN_BOUNDARY_Pos),
1055 UNICAST_VLAN_BOUNDARY_ENABLED = (0x1 << UNICAST_VLAN_BOUNDARY_Pos),
1056 UNICAST_VLAN_BOUNDARY_DISABLED = (0x0 << UNICAST_VLAN_BOUNDARY_Pos),
1057 PRIO_SCHEME_SELECT_Pos = 6,
1058 PRIO_SCHEME_SELECT_Msk = (0x1 << PRIO_SCHEME_SELECT_Pos),
1059 PRIO_SCHEME_SELECT_MAP_3_HI = (0x0 << PRIO_SCHEME_SELECT_Pos),
1060 PRIO_SCHEME_SELECT_MAP_2_HI = (0x2 << PRIO_SCHEME_SELECT_Pos),
1061 PRIO_SCHEME_SELECT_MAP_0_LO = (0x3 << PRIO_SCHEME_SELECT_Pos),
1062 };
1063
1064}
1065
1066namespace VLAN_ENTRY {
1067 enum {
1068 FID_Pos = 0,
1069 FID_Msk = (0x7F << FID_Pos),
1070 MSTP_INDEX_Pos = 12,
1071 MSTP_INDEX_Msk = (0x7 << MSTP_INDEX_Pos),
1072 PRIORITY_Pos = 24,
1073 PRIORITY_Msk = (0x3 << PRIORITY_Pos),
1074 FORWARD_OPTION_Pos = 27,
1075 FORWARD_OPTION_Msk = (0x1 << FORWARD_OPTION_Pos),
1076 FORWARD_OPTION_OTHER = (0x0 << FORWARD_OPTION_Pos),
1077 FORWARD_OPTION_VLAN_MAP = (0x1 << FORWARD_OPTION_Pos),
1078 VALID_Pos = 31,
1079 VALID_Msk = (0x1 << VALID_Pos),
1080 VALID_FALSE = (0x0 << VALID_Pos),
1081 VALID_TRUE = (0x1 << VALID_Pos),
1082 };
1083
1084 inline uint32_t FID(uint32_t _x)
1085 { return (((_x) << FID_Pos) & FID_Msk); }
1086 inline uint32_t MSTP_INDEX(uint32_t _x)
1087 { return (((_x) << MSTP_INDEX_Pos) & MSTP_INDEX_Msk); }
1088 inline uint32_t PRIORITY(uint32_t _x)
1089 { return (((_x) << PRIORITY_Pos) & PRIORITY_Msk); }
1090
1091}
1092namespace VLAN_UNTAG {
1093 enum {
1094 };
1095
1096 inline uint32_t PORT(uint32_t _x)
1097 { return (( 0x1 << (((_x)-1) & 0x1F))); }
1098
1099}
1100namespace VLAN_FORWARD {
1101 enum {
1102 };
1103
1104 inline uint32_t PORT(uint32_t _x)
1105 { return (( 0x1 << (((_x)-1) & 0x1F))); }
1106
1107}
1108namespace VLAN_INDEX {
1109 enum {
1110 INDEX_Pos = 0,
1111 INDEX_Msk = (0xFFF << INDEX_Pos),
1112 };
1113
1114 inline uint32_t INDEX(uint32_t _x)
1115 { return (((_x) << INDEX_Pos) & INDEX_Msk); }
1116
1117}
1118namespace VLAN_CTRL {
1119 enum {
1120 ACTION_Pos = 0,
1121 ACTION_Msk = (0x3 << ACTION_Pos),
1122 ACTION_NOP = (0x0 << ACTION_Pos),
1123 ACTION_WRITE = (0x1 << ACTION_Pos),
1124 ACTION_READ = (0x2 << ACTION_Pos),
1125 ACTION_CLEAR = (0x3 << ACTION_Pos),
1126 START_ACTION_Pos = 7,
1127 START_ACTION_Msk = (0x1 << START_ACTION_Pos),
1128 START_ACTION_START = (0x1 << START_ACTION_Pos),
1129 START_ACTION_COMPLETE = (0x1 << START_ACTION_Pos),
1130 };
1131
1132}
1133namespace ALU_INDEX {
1134 enum {
1135 MAC_ADDR_HI_Pos = 0,
1136 MAC_ADDR_HI_Msk = (0xFFFF << MAC_ADDR_HI_Pos),
1137 FID_INDEX_Pos = 16,
1138 FID_INDEX_Msk = (0x7F << FID_INDEX_Pos),
1139 };
1140
1141 inline uint32_t MAC_ADDR_HI(uint32_t _x)
1142 { return (((_x) << MAC_ADDR_HI_Pos) & MAC_ADDR_HI_Msk); }
1143 inline uint32_t FID_INDEX(uint32_t _x)
1144 { return (((_x) << FID_INDEX_Pos) & FID_INDEX_Msk); }
1145
1146}
1147namespace ALU_INDEX2 {
1148 enum {
1149 MAC_ADDR_LO_Pos = 0,
1150 MAC_ADDR_LO_Msk = (0xFFFFFFFF << MAC_ADDR_LO_Pos),
1151 ALU_DIRECT_INDEX_Pos = 0,
1152 ALU_DIRECT_INDEX_Msk = (0xFFF << ALU_DIRECT_INDEX_Pos),
1153 };
1154
1155 inline uint32_t MAC_ADDR_LO(uint32_t _x)
1156 { return (((_x) << MAC_ADDR_LO_Pos) & MAC_ADDR_LO_Msk); }
1157 inline uint32_t ALU_DIRECT_INDEX(uint32_t _x)
1158 { return (((_x) << ALU_DIRECT_INDEX_Pos) & ALU_DIRECT_INDEX_Msk); }
1159
1160}
1161namespace ALU_CTRL {
1162 enum {
1163 ACTION_Pos = 0,
1164 ACTION_Msk = (0x3 << ACTION_Pos),
1165 ACTION_NOP = (0x0 << ACTION_Pos),
1166 ACTION_WRITE = (0x1 << ACTION_Pos),
1167 ACTION_READ = (0x2 << ACTION_Pos),
1168 ACTION_SEARCH = (0x3 << ACTION_Pos),
1169 DIRECT_Pos = 2,
1170 DIRECT_Msk = (0x1 << DIRECT_Pos),
1171 DIRECT_DIRECT = (0x1 << DIRECT_Pos),
1172 DIRECT_HASHED = (0x0 << DIRECT_Pos),
1173 VALID_OR_STOP_Pos = 5,
1174 VALID_OR_STOP_Msk = (0x1 << VALID_OR_STOP_Pos),
1175 VALID_OR_STOP_TRUE = (0x1 << VALID_OR_STOP_Pos),
1176 VALID_OR_STOP_FALSE = (0x0 << VALID_OR_STOP_Pos),
1177 VALID_Pos = 6,
1178 VALID_Msk = (0x1 << VALID_Pos),
1179 VALID_TRUE = (0x1 << VALID_Pos),
1180 VALID_FALSE = (0x0 << VALID_Pos),
1181 START_Pos = 7,
1182 START_Msk = (0x1 << START_Pos),
1183 START_START = (0x1 << START_Pos),
1184 START_COMPLETE = (0x0 << START_Pos),
1185 VALID_CNT_Pos = 0,
1186 VALID_CNT_Msk = (0x3FFF << VALID_CNT_Pos),
1187 };
1188
1189}
1190namespace ALU_STAT_CTRL {
1191 enum {
1192 ACTION_Pos = 0,
1193 ACTION_Msk = (0x1 << ACTION_Pos),
1194 ACTION_WRITE = (0x0 << ACTION_Pos),
1195 ACTION_READ = (0x1 << ACTION_Pos),
1196 TABLE_Pos = 1,
1197 TABLE_Msk = (0x1 << TABLE_Pos),
1198 TABLE_STATIC_ADDR = (0x0 << TABLE_Pos),
1199 TABLE_STATIC_RESV_MCAST = (0x1 << TABLE_Pos),
1200 START_Pos = 7,
1201 START_Msk = (0x1 << START_Pos),
1202 START_NOP = (0x0 << START_Pos),
1203 START_START = (0x1 << START_Pos),
1204 START_COMPLETE = (0x0 << START_Pos),
1205 TABLE_INDEX_Pos = 16,
1206 TABLE_INDEX_Msk = (0x3F << TABLE_INDEX_Pos),
1207 };
1208
1209 inline uint32_t TABLE_INDEX(uint32_t _x)
1210 { return (((_x) << TABLE_INDEX_Pos) & TABLE_INDEX_Msk); }
1211
1212}
1213namespace ALU_VAL_A {
1214 enum {
1215 MSTP_Pos = 0,
1216 MSTP_Msk = (0x7 << MSTP_Pos),
1217 PRIO_AGE_Pos = 26,
1218 PRIO_AGE_Msk = (0x3 << PRIO_AGE_Pos),
1219 DST_FILTER_Pos = 29,
1220 DST_FILTER_Msk = (0x1 << DST_FILTER_Pos),
1221 DST_FILTER_ENABLED = (0x1 << DST_FILTER_Pos),
1222 DST_FILTER_DISABLED = (0x0 << DST_FILTER_Pos),
1223 SRC_FILTER_Pos = 30,
1224 SRC_FILTER_Msk = (0x1 << SRC_FILTER_Pos),
1225 SRC_FILTER_ENABLED = (0x1 << SRC_FILTER_Pos),
1226 SRC_FILTER_DISABLED = (0x0 << SRC_FILTER_Pos),
1227 ALU_STATIC_Pos = 31,
1228 ALU_STATIC_Msk = (0x1 << ALU_STATIC_Pos),
1229 ALU_STATIC_STATIC = (0x1 << ALU_STATIC_Pos),
1230 ALU_STATIC_DYN = (0x0 << ALU_STATIC_Pos),
1231 STATIC_VALID_Pos = 31,
1232 STATIC_VALID_Msk = (0x1 << STATIC_VALID_Pos),
1233 STATIC_VALID_TRUE = (0x1 << STATIC_VALID_Pos),
1234 STATIC_VALID_FALSE = (0x0 << STATIC_VALID_Pos),
1235 };
1236
1237 inline uint32_t MSTP(uint32_t _x)
1238 { return (((_x) << MSTP_Pos) & MSTP_Msk); }
1239 inline uint32_t PRIO_AGE(uint32_t _x)
1240 { return (((_x) << PRIO_AGE_Pos) & PRIO_AGE_Msk); }
1241
1242}
1243namespace ALU_VAL_B {
1244 enum {
1245 PORTS_Pos = 0,
1246 PORTS_Msk = (0x1FFFFFFF << PORTS_Pos),
1247 USE_FID_Pos = 30,
1248 USE_FID_Msk = (0x1 << USE_FID_Pos),
1249 USE_FID_ENABLED = (0x1 << USE_FID_Pos),
1250 USE_FID_DISABLED = (0x0 << USE_FID_Pos),
1251 OVERRIDE_Pos = 31,
1252 OVERRIDE_Msk = (0x1 << OVERRIDE_Pos),
1253 OVERRIDE_ENABLED = (0x1 << OVERRIDE_Pos),
1254 OVERRIDE_DISABLED = (0x0 << OVERRIDE_Pos),
1255 };
1256
1257 inline uint32_t PORT(uint32_t _x)
1258 { return (((_x) << PORTS_Pos) & PORTS_Msk); }
1259
1260}
1261namespace ALU_VAL_C {
1262 enum {
1263 MAC_ADDR_HI_Pos = 0,
1264 MAC_ADDR_HI_Msk = (0xFFFF << MAC_ADDR_HI_Pos),
1265 FID_Pos = 16,
1266 FID_Msk = (0x7F << FID_Pos),
1267 };
1268
1269 inline uint32_t MAC_ADDR_HI(uint32_t _x)
1270 { return (((_x) << MAC_ADDR_HI_Pos) & MAC_ADDR_HI_Msk); }
1271 inline uint32_t FID(uint32_t _x)
1272 { return (((_x) << FID_Pos) & FID_Msk); }
1273
1274}
1275namespace ALU_VAL_D {
1276 enum {
1277 MAC_ADDR_LO_Pos = 0,
1278 MAC_ADDR_LO_Msk = (0xFFFFFFFF << MAC_ADDR_LO_Pos),
1279 };
1280
1281 inline uint32_t MAC_ADDR_LO(uint32_t _x)
1282 { return (((_x) << MAC_ADDR_LO_Pos) & MAC_ADDR_LO_Msk); }
1283
1284}
1285
1286namespace PTP_CLK_CTRL {
1287 enum {
1288 CLK_RESET_Pos = 0,
1289 CLK_RESET_Msk = (0x1 << CLK_RESET_Pos),
1290 CLK_RESET_RESET = (0x1 << CLK_RESET_Pos),
1291 CLK_Pos = 1,
1292 CLK_Msk = (0x1 << CLK_Pos),
1293 CLK_ENABLED = (0x1 << CLK_Pos),
1294 CLK_DISABLED = (0x0 << CLK_Pos),
1295 CLK_ADJ_Pos = 2,
1296 CLK_ADJ_Msk = (0x1 << CLK_ADJ_Pos),
1297 CLK_ADJ_ENABLED = (0x1 << CLK_ADJ_Pos),
1298 CLK_ADJ_DISABLED = (0x0 << CLK_ADJ_Pos),
1299 LOAD_Pos = 3,
1300 LOAD_Msk = (0x1 << LOAD_Pos),
1301 LOAD_ENABLED = (0x1 << LOAD_Pos),
1302 READ_Pos = 4,
1303 READ_Msk = (0x1 << READ_Pos),
1304 READ_ENABLED = (0x1 << READ_Pos),
1305 STEP_DIR_Pos = 5,
1306 STEP_DIR_Msk = (0x1 << STEP_DIR_Pos),
1307 STEP_DIR_ADD = (0x1 << STEP_DIR_Pos),
1308 STEP_DIR_SUB = (0x0 << STEP_DIR_Pos),
1309 STEP_ADJ_Pos = 6,
1310 STEP_ADJ_Msk = (0x1 << STEP_ADJ_Pos),
1311 STEP_ADJ_ENABLED = (0x1 << STEP_ADJ_Pos),
1312 STEP_ADJ_DISABLED = (0x0 << STEP_ADJ_Pos),
1313 SW_FREQ_ADJ_Pos = 15,
1314 SW_FREQ_ADJ_Msk = (0x1 << SW_FREQ_ADJ_Pos),
1315 SW_FREQ_ADJ_ENABLED = (0x1 << SW_FREQ_ADJ_Pos),
1316 SW_FREQ_ADJ_DISABLED = (0x0 << SW_FREQ_ADJ_Pos),
1317 };
1318
1319}
1320namespace PTP_RTC_PHASE {
1321 enum {
1322 PHASE_Pos = 0,
1323 PHASE_Msk = (0x3 << PHASE_Pos),
1324 };
1325
1326 inline uint32_t PHASE(uint32_t _x)
1327 { return (((_x) << PHASE_Pos) & PHASE_Msk); }
1328
1329}
1330namespace PTP_RTC_NANO {
1331 enum {
1332 NANOSEC_Pos = 0,
1333 NANOSEC_Msk = (0xFFFFFFFF << NANOSEC_Pos),
1334 };
1335
1336 inline uint32_t NANOSEC(uint32_t _x)
1337 { return (((_x) << NANOSEC_Pos) & NANOSEC_Msk); }
1338
1339}
1340namespace PTP_RTC_SEC {
1341 enum {
1342 SEC_Pos = 0,
1343 SEC_Msk = (0xFFFFFFFF << SEC_Pos),
1344 };
1345
1346 inline uint32_t SEC(uint32_t _x)
1347 { return (((_x) << SEC_Pos) & SEC_Msk); }
1348
1349}
1350namespace PTP_RTC_SUBNANO {
1351 enum {
1352 SUB_NANO_Pos = 0,
1353 SUB_NANO_Msk = (0x3FFFFFFF << SUB_NANO_Pos),
1354 TMP_ADJ_Pos = 30,
1355 TMP_ADJ_Msk = (0x1 << TMP_ADJ_Pos),
1356 TMP_ADJ_ENABLED = (0x1 << TMP_ADJ_Pos),
1357 TMP_ADJ_DISABLED = (0x0 << TMP_ADJ_Pos),
1358 TMP_ADJ_DIR_Pos = 31,
1359 TMP_ADJ_DIR_Msk = (0x1 << TMP_ADJ_DIR_Pos),
1360 TMP_ADJ_DIR_ENABLED = (0x1 << TMP_ADJ_DIR_Pos),
1361 TMP_ADJ_DIR_DISABLED = (0x0 << TMP_ADJ_DIR_Pos),
1362 };
1363
1364 inline uint32_t SUB_NANO(uint32_t _x)
1365 { return (((_x) << SUB_NANO_Pos) & SUB_NANO_Msk); }
1366
1367}
1368namespace PTP_MSG_CONFIG {
1369 enum {
1370 IPV4_CSUM_UPDATE_Pos = 2,
1371 IPV4_CSUM_UPDATE_Msk = (0x1 << IPV4_CSUM_UPDATE_Pos),
1372 IPV4_CSUM_UPDATE_ENABLED = (0x1 << IPV4_CSUM_UPDATE_Pos),
1373 IPV4_CSUM_UPDATE_DISABLED = (0x0 << IPV4_CSUM_UPDATE_Pos),
1374 DOMAIN_CHECK_Pos = 4,
1375 DOMAIN_CHECK_Msk = (0x1 << DOMAIN_CHECK_Pos),
1376 DOMAIN_CHECK_ENABLED = (0x1 << DOMAIN_CHECK_Pos),
1377 DOMAIN_CHECK_DISABLED = (0x0 << DOMAIN_CHECK_Pos),
1378 DROP_SYNC_DELAY_REQ_Pos = 5,
1379 DROP_SYNC_DELAY_REQ_Msk = (0x1 << DROP_SYNC_DELAY_REQ_Pos),
1380 DROP_SYNC_DELAY_REQ_ENABLED = (0x1 << DROP_SYNC_DELAY_REQ_Pos),
1381 DROP_SYNC_DELAY_REQ_DISABLED = (0x0 << DROP_SYNC_DELAY_REQ_Pos),
1382 PDELAY_CHECK_Pos = 7,
1383 PDELAY_CHECK_Msk = (0x1 << PDELAY_CHECK_Pos),
1384 PDELAY_CHECK_ENABLED = (0x1 << PDELAY_CHECK_Pos),
1385 PDELAY_CHECK_DISABLED = (0x0 << PDELAY_CHECK_Pos),
1386 DELAY_CHECK_Pos = 8,
1387 DELAY_CHECK_Msk = (0x1 << DELAY_CHECK_Pos),
1388 DELAY_CHECK_ENABLED = (0x1 << DELAY_CHECK_Pos),
1389 DELAY_CHECK_DISABLED = (0x0 << DELAY_CHECK_Pos),
1390 SYNC_CHECK_Pos = 9,
1391 SYNC_CHECK_Msk = (0x1 << SYNC_CHECK_Pos),
1392 SYNC_CHECK_ENABLED = (0x1 << SYNC_CHECK_Pos),
1393 SYNC_CHECK_DISABLED = (0x0 << SYNC_CHECK_Pos),
1394 ALL_PTP_HI_PRIO_Pos = 10,
1395 ALL_PTP_HI_PRIO_Msk = (0x1 << ALL_PTP_HI_PRIO_Pos),
1396 ALL_PTP_HI_PRIO_ENABLED = (0x1 << ALL_PTP_HI_PRIO_Pos),
1397 ALL_PTP_HI_PRIO_DISABLED = (0x0 << ALL_PTP_HI_PRIO_Pos),
1398 ALT_MASTER_Pos = 11,
1399 ALT_MASTER_Msk = (0x1 << ALT_MASTER_Pos),
1400 ALT_MASTER_ENABLED = (0x1 << ALT_MASTER_Pos),
1401 ALT_MASTER_DISABLED = (0x0 << ALT_MASTER_Pos),
1402 UNICAST_Pos = 12,
1403 UNICAST_Msk = (0x1 << UNICAST_Pos),
1404 UNICAST_ENABLED = (0x1 << UNICAST_Pos),
1405 UNICAST_DISABLED = (0x0 << UNICAST_Pos),
1406 MODE_Pos = 17,
1407 MODE_Msk = (0x1 << MODE_Pos),
1408 MODE_MASTER = (0x1 << MODE_Pos),
1409 MODE_SLAVE = (0x0 << MODE_Pos),
1410 TC_Pos = 18,
1411 TC_Msk = (0x1 << TC_Pos),
1412 TC_P2P = (0x1 << TC_Pos),
1413 TC_E2E = (0x0 << TC_Pos),
1414 IPV6_UDP_Pos = 19,
1415 IPV6_UDP_Msk = (0x1 << IPV6_UDP_Pos),
1416 IPV6_UDP_ENABLED = (0x1 << IPV6_UDP_Pos),
1417 IPV6_UDP_DISABLED = (0x0 << IPV6_UDP_Pos),
1418 IPV4_UDP_Pos = 20,
1419 IPV4_UDP_Msk = (0x1 << IPV4_UDP_Pos),
1420 IPV4_UDP_ENABLED = (0x1 << IPV4_UDP_Pos),
1421 IPV4_UDP_DISABLED = (0x0 << IPV4_UDP_Pos),
1422 ETH_MSG_Pos = 21,
1423 ETH_MSG_Msk = (0x1 << ETH_MSG_Pos),
1424 ETH_MSG_ENABLED = (0x1 << ETH_MSG_Pos),
1425 ETH_MSG_DISABLED = (0x0 << ETH_MSG_Pos),
1426 PTP_Pos = 22,
1427 PTP_Msk = (0x1 << PTP_Pos),
1428 PTP_ENABLED = (0x1 << PTP_Pos),
1429 PTP_DISABLED = (0x0 << PTP_Pos),
1430 };
1431
1432}
1433namespace PTP_DOMAIN_VERSION {
1434 enum {
1435 DOMAIN_Pos = 0,
1436 DOMAIN_Msk = (0xFF << DOMAIN_Pos),
1437 VERSION_Pos = 8,
1438 VERSION_Msk = (0xF << VERSION_Pos),
1439 };
1440
1441 inline uint32_t DOMAIN(uint32_t _x)
1442 { return (((_x) << DOMAIN_Pos) & DOMAIN_Msk); }
1443 inline uint32_t VERSION(uint32_t _x)
1444 { return (((_x) << VERSION_Pos) & VERSION_Msk); }
1445
1446}
1447namespace PTP_UNIT_INDEX {
1448 enum {
1449 TRIG_UNIT_Pos = 0,
1450 TRIG_UNIT_Msk = (0x3 << TRIG_UNIT_Pos),
1451 TIMESTAMP_UNIT_Pos = 8,
1452 TIMESTAMP_UNIT_Msk = (0x1 << TIMESTAMP_UNIT_Pos),
1453 GPIO_INDEX_Pos = 16,
1454 GPIO_INDEX_Msk = (0xFF << GPIO_INDEX_Pos),
1455 };
1456
1457 inline uint32_t TRIG_UNIT(uint32_t _x)
1458 { return (((_x) << TRIG_UNIT_Pos) & TRIG_UNIT_Msk); }
1459 inline uint32_t TIMESTAMP_UNIT(uint32_t _x)
1460 { return (((_x) << TIMESTAMP_UNIT_Pos) & TIMESTAMP_UNIT_Msk); }
1461 inline uint32_t GPIO_INDEX(uint32_t _x)
1462 { return (((_x) << GPIO_INDEX_Pos) & GPIO_INDEX_Msk); }
1463
1464}
1465namespace PTP_TRIG_STATUS {
1466 enum {
1467 DONE_Pos = 0,
1468 DONE_Msk = (0x7 << DONE_Pos),
1469 ERROR_Pos = 16,
1470 ERROR_Msk = (0x7 << ERROR_Pos),
1471 };
1472
1473 inline uint32_t DONE(uint32_t _x)
1474 { return (((_x) << DONE_Pos) & DONE_Msk); }
1475 inline uint32_t ERROR(uint32_t _x)
1476 { return (((_x) << ERROR_Pos) & ERROR_Msk); }
1477
1478}
1479namespace PTP_INT_STATUS {
1480 enum {
1481 TIMESTAMP_IRQ_Pos = 0,
1482 TIMESTAMP_IRQ_Msk = (0x7 << TIMESTAMP_IRQ_Pos),
1483 TRIG_IRQ_Pos = 16,
1484 TRIG_IRQ_Msk = (0x7 << TRIG_IRQ_Pos),
1485 };
1486
1487 inline uint32_t TIMESTAMP_IRQ(uint32_t _x)
1488 { return (((_x) << TIMESTAMP_IRQ_Pos) & TIMESTAMP_IRQ_Msk); }
1489 inline uint32_t TRIG_IRQ(uint32_t _x)
1490 { return (((_x) << TRIG_IRQ_Pos) & TRIG_IRQ_Msk); }
1491
1492}
1493namespace PTP_TS_CTRL {
1494 enum {
1495 TS_SW_RESET_Pos = 0,
1496 TS_SW_RESET_Msk = (0x1 << TS_SW_RESET_Pos),
1497 TS_SW_RESET = (0x1 << TS_SW_RESET_Pos),
1498 TS_Pos = 1,
1499 TS_Msk = (0x1 << TS_Pos),
1500 TS_ENABLED = (0x1 << TS_Pos),
1501 TS_DISABLED = (0x0 << TS_Pos),
1502 TRIG_RESET_Pos = 2,
1503 TRIG_RESET_Msk = (0x1 << TRIG_RESET_Pos),
1504 TRIG_RESET = (0x1 << TRIG_RESET_Pos),
1505 TRIG_Pos = 3,
1506 TRIG_Msk = (0x1 << TRIG_Pos),
1507 TRIG_ENABLED = (0x1 << TRIG_Pos),
1508 TRIG_DISABLED = (0x0 << TRIG_Pos),
1509 TRIG_ACTIVE_Pos = 4,
1510 TRIG_ACTIVE_Msk = (0x1 << TRIG_ACTIVE_Pos),
1511 TRIG_ACTIVE_ENABLED = (0x1 << TRIG_ACTIVE_Pos),
1512 TRIG_ACTIVE_DISABLED = (0x0 << TRIG_ACTIVE_Pos),
1513 TS_INT_Pos = 5,
1514 TS_INT_Msk = (0x1 << TS_INT_Pos),
1515 TS_INT_ENABLED = (0x1 << TS_INT_Pos),
1516 TS_INT_DISABLED = (0x0 << TS_INT_Pos),
1517 GPIO_DIR_Pos = 6,
1518 GPIO_DIR_Msk = (0x1 << GPIO_DIR_Pos),
1519 GPIO_DIR_TS_INPUT = (0x1 << GPIO_DIR_Pos),
1520 GPIO_DIR_TRIG_OUT = (0x0 << GPIO_DIR_Pos),
1521 GPIO_IN_Pos = 7,
1522 GPIO_IN_Msk = (0x1 << GPIO_IN_Pos),
1523 GPIO_OUT_SEL_Pos = 8,
1524 GPIO_OUT_SEL_Msk = (0x1 << GPIO_OUT_SEL_Pos),
1525 GPIO_OUT_SEL_COMB = (0x1 << GPIO_OUT_SEL_Pos),
1526 GPIO_OUT_SEL_FF = (0x0 << GPIO_OUT_SEL_Pos),
1527 };
1528
1529}
1530namespace PTP_TRIG_TARGET_NANO {
1531 enum {
1532 NANOSEC_Pos = 0,
1533 NANOSEC_Msk = (0x3FFFFFFF << NANOSEC_Pos),
1534 };
1535
1536 inline uint32_t NANOSEC(uint32_t _x)
1537 { return (((_x) << NANOSEC_Pos) & NANOSEC_Msk); }
1538
1539}
1540namespace PTP_TRIG_TARGET_SEC {
1541 enum {
1542 SEC_Pos = 0,
1543 SEC_Msk = (0xFFFFFFFF << SEC_Pos),
1544 };
1545
1546 inline uint32_t SEC(uint32_t _x)
1547 { return (((_x) << SEC_Pos) & SEC_Msk); }
1548
1549}
1550namespace PTP_TRIG_CTRL {
1551 enum {
1552 TRIG_ITERATION_Pos = 0,
1553 TRIG_ITERATION_Msk = (0xFFFF << TRIG_ITERATION_Pos),
1554 TRIG_GPO_Pos = 16,
1555 TRIG_GPO_Msk = (0x1 << TRIG_GPO_Pos),
1556 TRIG_GPO_GPIO2 = (0x1 << TRIG_GPO_Pos),
1557 TRIG_GPO_GPIO1 = (0x0 << TRIG_GPO_Pos),
1558 TRIG_EVT_OUT_Pos = 20,
1559 TRIG_EVT_OUT_Msk = (0x7 << TRIG_EVT_OUT_Pos),
1560 TRIG_EVT_OUT_EDGE_NEG = (0x0 << TRIG_EVT_OUT_Pos),
1561 TRIG_EVT_OUT_EDGE_POS = (0x1 << TRIG_EVT_OUT_Pos),
1562 TRIG_EVT_OUT_PULSE_NEG = (0x2 << TRIG_EVT_OUT_Pos),
1563 TRIG_EVT_OUT_PLUSE_POS = (0x3 << TRIG_EVT_OUT_Pos),
1564 TRIG_EVT_OUT_PER_NEG = (0x4 << TRIG_EVT_OUT_Pos),
1565 TRIG_EVT_OUT_PER_POS = (0x5 << TRIG_EVT_OUT_Pos),
1566 TRIG_EVT_OUT_PATTERN = (0x6 << TRIG_EVT_OUT_Pos),
1567 TRIG_EDGE_Pos = 23,
1568 TRIG_EDGE_Msk = (0x1 << TRIG_EDGE_Pos),
1569 TRIG_EDGE_POS = (0x0 << TRIG_EDGE_Pos),
1570 TRIG_EDGE_NEG = (0x1 << TRIG_EDGE_Pos),
1571 TRIG_NOTIFY_Pos = 24,
1572 TRIG_NOTIFY_Msk = (0x1 << TRIG_NOTIFY_Pos),
1573 TRIG_NOTIFY_ENABLED = (0x1 << TRIG_NOTIFY_Pos),
1574 TRIG_NOTIFY_DISABLED = (0x0 << TRIG_NOTIFY_Pos),
1575 TRIG_NOW_Pos = 25,
1576 TRIG_NOW_Msk = (0x1 << TRIG_NOW_Pos),
1577 TRIG_NOW = (0x1 << TRIG_NOW_Pos),
1578 CASCADE_UPSTREAM_SEL_Pos = 26,
1579 CASCADE_UPSTREAM_SEL_Msk = (0x3 << CASCADE_UPSTREAM_SEL_Pos),
1580 CASCADE_TAIL_Pos = 30,
1581 CASCADE_TAIL_Msk = (0x1 << CASCADE_TAIL_Pos),
1582 CASCADE_TAIL_ENABLED = (0x1 << CASCADE_TAIL_Pos),
1583 CASCADE_TAIL_DISABLED = (0x0 << CASCADE_TAIL_Pos),
1584 CASCADE_Pos = 31,
1585 CASCADE_Msk = (0x1 << CASCADE_Pos),
1586 CASCADE_ENABLED = (0x1 << CASCADE_Pos),
1587 CASCADE_DISABLED = (0x0 << CASCADE_Pos),
1588 };
1589
1590 inline uint32_t TRIG_ITERATION(uint32_t _x)
1591 { return (((_x) << TRIG_ITERATION_Pos) & TRIG_ITERATION_Msk); }
1592 inline uint32_t CASCADE_UPSTREAM_SEL(uint32_t _x)
1593 { return (((_x) << CASCADE_UPSTREAM_SEL_Pos) & CASCADE_UPSTREAM_SEL_Msk); }
1594
1595}
1596namespace PTP_TRIG_CYC_WIDTH {
1597 enum {
1598 WIDTH_Pos = 0,
1599 WIDTH_Msk = (0xFFFFFFFF << WIDTH_Pos),
1600 };
1601
1602 inline uint32_t WIDTH(uint32_t _x)
1603 { return (((_x) << WIDTH_Pos) & WIDTH_Msk); }
1604
1605}
1606namespace PTP_TRIG_CYC_CNT {
1607 enum {
1608 BIT_PATTERN_Pos = 0,
1609 BIT_PATTERN_Msk = (0xFFFF << BIT_PATTERN_Pos),
1610 CYCLE_CNT_Pos = 16,
1611 CYCLE_CNT_Msk = (0xFFFF << CYCLE_CNT_Pos),
1612 };
1613
1614 inline uint32_t BIT_PATTERN(uint32_t _x)
1615 { return (((_x) << BIT_PATTERN_Pos) & BIT_PATTERN_Msk); }
1616 inline uint32_t CYCLE_CNT(uint32_t _x)
1617 { return (((_x) << CYCLE_CNT_Pos) & CYCLE_CNT_Msk); }
1618
1619}
1620namespace PTP_TRIG_ITER_TIME {
1621 enum {
1622 NANOSEC_Pos = 0,
1623 NANOSEC_Msk = (0xFFFFFFFF << NANOSEC_Pos),
1624 };
1625
1626 inline uint32_t NANOSEC(uint32_t _x)
1627 { return (((_x) << NANOSEC_Pos) & NANOSEC_Msk); }
1628
1629}
1630namespace PTP_TRIG_PULSE {
1631 enum {
1632 OUT_WIDTH_Pos = 0,
1633 OUT_WIDTH_Msk = (0xFFFF << OUT_WIDTH_Pos),
1634 PPS_WIDTH_HI_Pos = 16,
1635 PPS_WIDTH_HI_Msk = (0xFF << PPS_WIDTH_HI_Pos),
1636 };
1637
1638 inline uint32_t OUT_WIDTH(uint32_t _x)
1639 { return (((_x) << OUT_WIDTH_Pos) & OUT_WIDTH_Msk); }
1640 inline uint32_t PPS_WIDTH_HI(uint32_t _x)
1641 { return (((_x) << PPS_WIDTH_HI_Pos) & PPS_WIDTH_HI_Msk); }
1642
1643}
1644namespace PTP_TS_STAT_CTRL {
1645 enum {
1646 TS_CASCADE_Pos = 0,
1647 TS_CASCADE_Msk = (0x1 << TS_CASCADE_Pos),
1648 TS_CASCADE_ENABLED = (0x1 << TS_CASCADE_Pos),
1649 TS_CASCADE_DISABLED = (0x0 << TS_CASCADE_Pos),
1650 TS_CASCADE_UPS_Pos = 1,
1651 TS_CASCADE_UPS_Msk = (0x1 << TS_CASCADE_UPS_Pos),
1652 TS_CASCADE_UPS_TS_1 = (0x1 << TS_CASCADE_UPS_Pos),
1653 TS_CASCADE_UPS_TS_0 = (0x0 << TS_CASCADE_UPS_Pos),
1654 TS_CASCADE_TAIL_Pos = 5,
1655 TS_CASCADE_TAIL_Msk = (0x1 << TS_CASCADE_TAIL_Pos),
1656 TS_CASCADE_TAIL_ENABLED = (0x1 << TS_CASCADE_TAIL_Pos),
1657 TS_CASCADE_TAIL_DISABLED = (0x0 << TS_CASCADE_TAIL_Pos),
1658 TS_DETECT_NEG_Pos = 6,
1659 TS_DETECT_NEG_Msk = (0x1 << TS_DETECT_NEG_Pos),
1660 TS_DETECT_NEG_ENABLED = (0x1 << TS_DETECT_NEG_Pos),
1661 TS_DETECT_NEG_DISABLED = (0x0 << TS_DETECT_NEG_Pos),
1662 TS_DETECT_POS_Pos = 7,
1663 TS_DETECT_POS_Msk = (0x1 << TS_DETECT_POS_Pos),
1664 TS_DETECT_POS_ENABLED = (0x1 << TS_DETECT_POS_Pos),
1665 TS_DETECT_POS_DISABLED = (0x0 << TS_DETECT_POS_Pos),
1666 TS_EVT_OVERFLOW_Pos = 16,
1667 TS_EVT_OVERFLOW_Msk = (0x1 << TS_EVT_OVERFLOW_Pos),
1668 TS_EVT_OVERFLOW_ENABLED = (0x1 << TS_EVT_OVERFLOW_Pos),
1669 TS_EVT_OVERFLOW_DISABLED = (0x0 << TS_EVT_OVERFLOW_Pos),
1670 TS_EVT_CNT_Pos = 17,
1671 TS_EVT_CNT_Msk = (0xF << TS_EVT_CNT_Pos),
1672 };
1673
1674}
1675namespace PTP_TS_EVT_0_NANO {
1676 enum {
1677 NANOSEC_Pos = 0,
1678 NANOSEC_Msk = (0x3FFFFFFF << NANOSEC_Pos),
1679 EVT_EDGE_Pos = 30,
1680 EVT_EDGE_Msk = (0x1 << EVT_EDGE_Pos),
1681 EVT_EDGE_POS = (0x1 << EVT_EDGE_Pos),
1682 EVT_EDGE_NEG = (0x1 << EVT_EDGE_Pos),
1683 };
1684
1685}
1686namespace PTP_TS_EVT_0_SEC {
1687 enum {
1688 SEC_Pos = 0,
1689 SEC_Msk = (0xFFFFFFFF << SEC_Pos),
1690 };
1691
1692}
1693namespace PTP_TS_EVT_0_PHASE {
1694 enum {
1695 PHASE_Pos = 0,
1696 PHASE_Msk = (0x7 << PHASE_Pos),
1697 };
1698
1699}
1700namespace PTP_TS_EVT_1_NANO {
1701 enum {
1702 NANOSEC_Pos = 0,
1703 NANOSEC_Msk = (0x3FFFFFFF << NANOSEC_Pos),
1704 EVT_EDGE_Pos = 30,
1705 EVT_EDGE_Msk = (0x1 << EVT_EDGE_Pos),
1706 EVT_EDGE_POS = (0x1 << EVT_EDGE_Pos),
1707 EVT_EDGE_NEG = (0x1 << EVT_EDGE_Pos),
1708 };
1709
1710}
1711namespace PTP_TS_EVT_1_SEC {
1712 enum {
1713 SEC_Pos = 0,
1714 SEC_Msk = (0xFFFFFFFF << SEC_Pos),
1715 };
1716
1717}
1718namespace PTP_TS_EVT_1_PHASE {
1719 enum {
1720 PHASE_Pos = 0,
1721 PHASE_Msk = (0x7 << PHASE_Pos),
1722 };
1723
1724}
1725namespace PTP_TS_EVT_2_NANO {
1726 enum {
1727 NANOSEC_Pos = 0,
1728 NANOSEC_Msk = (0x3FFFFFFF << NANOSEC_Pos),
1729 EVT_EDGE_Pos = 30,
1730 EVT_EDGE_Msk = (0x1 << EVT_EDGE_Pos),
1731 EVT_EDGE_POS = (0x1 << EVT_EDGE_Pos),
1732 EVT_EDGE_NEG = (0x1 << EVT_EDGE_Pos),
1733 };
1734
1735}
1736namespace PTP_TS_EVT_2_SEC {
1737 enum {
1738 SEC_Pos = 0,
1739 SEC_Msk = (0xFFFFFFFF << SEC_Pos),
1740 };
1741
1742}
1743namespace PTP_TS_EVT_2_PHASE {
1744 enum {
1745 PHASE_Pos = 0,
1746 PHASE_Msk = (0x7 << PHASE_Pos),
1747 };
1748
1749}
1750namespace PTP_TS_EVT_3_NANO {
1751 enum {
1752 NANOSEC_Pos = 0,
1753 NANOSEC_Msk = (0x3FFFFFFF << NANOSEC_Pos),
1754 EVT_EDGE_Pos = 30,
1755 EVT_EDGE_Msk = (0x1 << EVT_EDGE_Pos),
1756 EVT_EDGE_POS = (0x1 << EVT_EDGE_Pos),
1757 EVT_EDGE_NEG = (0x1 << EVT_EDGE_Pos),
1758 };
1759
1760}
1761namespace PTP_TS_EVT_3_SEC {
1762 enum {
1763 SEC_Pos = 0,
1764 SEC_Msk = (0xFFFFFFFF << SEC_Pos),
1765 };
1766
1767}
1768namespace PTP_TS_EVT_3_PHASE {
1769 enum {
1770 PHASE_Pos = 0,
1771 PHASE_Msk = (0x7 << PHASE_Pos),
1772 };
1773
1774}
1775namespace PTP_TS_EVT_4_NANO {
1776 enum {
1777 NANOSEC_Pos = 0,
1778 NANOSEC_Msk = (0x3FFFFFFF << NANOSEC_Pos),
1779 EVT_EDGE_Pos = 30,
1780 EVT_EDGE_Msk = (0x1 << EVT_EDGE_Pos),
1781 EVT_EDGE_POS = (0x1 << EVT_EDGE_Pos),
1782 EVT_EDGE_NEG = (0x1 << EVT_EDGE_Pos),
1783 };
1784
1785}
1786namespace PTP_TS_EVT_4_SEC {
1787 enum {
1788 SEC_Pos = 0,
1789 SEC_Msk = (0xFFFFFFFF << SEC_Pos),
1790 };
1791
1792}
1793namespace PTP_TS_EVT_4_PHASE {
1794 enum {
1795 PHASE_Pos = 0,
1796 PHASE_Msk = (0x7 << PHASE_Pos),
1797 };
1798
1799}
1800namespace PTP_TS_EVT_5_NANO {
1801 enum {
1802 NANOSEC_Pos = 0,
1803 NANOSEC_Msk = (0x3FFFFFFF << NANOSEC_Pos),
1804 EVT_EDGE_Pos = 30,
1805 EVT_EDGE_Msk = (0x1 << EVT_EDGE_Pos),
1806 EVT_EDGE_POS = (0x1 << EVT_EDGE_Pos),
1807 EVT_EDGE_NEG = (0x1 << EVT_EDGE_Pos),
1808 };
1809
1810}
1811namespace PTP_TS_EVT_5_SEC {
1812 enum {
1813 SEC_Pos = 0,
1814 SEC_Msk = (0xFFFFFFFF << SEC_Pos),
1815 };
1816
1817}
1818namespace PTP_TS_EVT_5_PHASE {
1819 enum {
1820 PHASE_Pos = 0,
1821 PHASE_Msk = (0x7 << PHASE_Pos),
1822 };
1823
1824}
1825namespace PTP_TS_EVT_6_NANO {
1826 enum {
1827 NANOSEC_Pos = 0,
1828 NANOSEC_Msk = (0x3FFFFFFF << NANOSEC_Pos),
1829 EVT_EDGE_Pos = 30,
1830 EVT_EDGE_Msk = (0x1 << EVT_EDGE_Pos),
1831 EVT_EDGE_POS = (0x1 << EVT_EDGE_Pos),
1832 EVT_EDGE_NEG = (0x1 << EVT_EDGE_Pos),
1833 };
1834
1835}
1836namespace PTP_TS_EVT_6_SEC {
1837 enum {
1838 SEC_Pos = 0,
1839 SEC_Msk = (0xFFFFFFFF << SEC_Pos),
1840 };
1841
1842}
1843namespace PTP_TS_EVT_6_PHASE {
1844 enum {
1845 PHASE_Pos = 0,
1846 PHASE_Msk = (0x7 << PHASE_Pos),
1847 };
1848
1849}
1850namespace PTP_TS_EVT_7_NANO {
1851 enum {
1852 NANOSEC_Pos = 0,
1853 NANOSEC_Msk = (0x3FFFFFFF << NANOSEC_Pos),
1854 EVT_EDGE_Pos = 30,
1855 EVT_EDGE_Msk = (0x1 << EVT_EDGE_Pos),
1856 EVT_EDGE_POS = (0x1 << EVT_EDGE_Pos),
1857 EVT_EDGE_NEG = (0x1 << EVT_EDGE_Pos),
1858 };
1859
1860}
1861namespace PTP_TS_EVT_7_SEC {
1862 enum {
1863 SEC_Pos = 0,
1864 SEC_Msk = (0xFFFFFFFF << SEC_Pos),
1865 };
1866
1867}
1868namespace PTP_TS_EVT_7_PHASE {
1869 enum {
1870 PHASE_Pos = 0,
1871 PHASE_Msk = (0x7 << PHASE_Pos),
1872 };
1873
1874}
1875
1876namespace PORT_DEFAULT_VID {
1877 enum {
1878 VID_Pos = 0,
1879 VID_Msk = (0xFFF << VID_Pos),
1880 DEI_Pos = 12,
1881 DEI_Msk = (0x1 << DEI_Pos),
1882 PCP_Pos = 13,
1883 PCP_Msk = (0x7 << PCP_Pos),
1884 };
1885
1886 inline uint32_t VID(uint32_t _x)
1887 { return (((_x) << VID_Pos) & VID_Msk); }
1888 inline uint32_t DEI(uint32_t _x)
1889 { return (((_x) << DEI_Pos) & DEI_Msk); }
1890 inline uint32_t PCP(uint32_t _x)
1891 { return (((_x) << PCP_Pos) & PCP_Msk); }
1892
1893}
1894namespace PORT_CUSTOM_VID {
1895 enum {
1896 VID_Pos = 0,
1897 VID_Msk = (0xFFF << VID_Pos),
1898 DEI_Pos = 12,
1899 DEI_Msk = (0x1 << DEI_Pos),
1900 PCP_Pos = 13,
1901 PCP_Msk = (0x7 << PCP_Pos),
1902 };
1903
1904 inline uint32_t VID(uint32_t _x)
1905 { return (((_x) << VID_Pos) & VID_Msk); }
1906 inline uint32_t DEI(uint32_t _x)
1907 { return (((_x) << DEI_Pos) & DEI_Msk); }
1908 inline uint32_t PCP(uint32_t _x)
1909 { return (((_x) << PCP_Pos) & PCP_Msk); }
1910
1911}
1912namespace PORT_AVB_SR_1_VID {
1913 enum {
1914 VID_Pos = 0,
1915 VID_Msk = (0xFFF << VID_Pos),
1916 CFI_Pos = 12,
1917 CFI_Msk = (0x1 << CFI_Pos),
1918 PRIO_Pos = 13,
1919 PRIO_Msk = (0x7 << PRIO_Pos),
1920 };
1921
1922 inline uint32_t VID(uint32_t _x)
1923 { return (((_x) << VID_Pos) & VID_Msk); }
1924 inline uint32_t CFI(uint32_t _x)
1925 { return (((_x) << CFI_Pos) & CFI_Msk); }
1926 inline uint32_t PRIO(uint32_t _x)
1927 { return (((_x) << PRIO_Pos) & PRIO_Msk); }
1928
1929}
1930namespace PORT_AVB_SR_2_VID {
1931 enum {
1932 VID_Pos = 0,
1933 VID_Msk = (0xFFF << VID_Pos),
1934 CFI_Pos = 12,
1935 CFI_Msk = (0x1 << CFI_Pos),
1936 PRIO_Pos = 13,
1937 PRIO_Msk = (0x7 << PRIO_Pos),
1938 };
1939
1940 inline uint32_t VID(uint32_t _x)
1941 { return (((_x) << VID_Pos) & VID_Msk); }
1942 inline uint32_t CFI(uint32_t _x)
1943 { return (((_x) << CFI_Pos) & CFI_Msk); }
1944 inline uint32_t PRIO(uint32_t _x)
1945 { return (((_x) << PRIO_Pos) & PRIO_Msk); }
1946
1947}
1948namespace PORT_WOL_STATUS {
1949 enum {
1950 ENERGY_DETECTED_Pos = 0,
1951 ENERGY_DETECTED_Msk = (0x1 << ENERGY_DETECTED_Pos),
1952 ENERGY_DETECTED = (0x1 << ENERGY_DETECTED_Pos),
1953 LINK_DETECTED_Pos = 1,
1954 LINK_DETECTED_Msk = (0x1 << LINK_DETECTED_Pos),
1955 LINK_DETECTED = (0x1 << LINK_DETECTED_Pos),
1956 MAGIC_PKT_DETECTED_Pos = 2,
1957 MAGIC_PKT_DETECTED_Msk = (0x1 << MAGIC_PKT_DETECTED_Pos),
1958 MAGIC_PKT_DETECTED = (0x1 << MAGIC_PKT_DETECTED_Pos),
1959 };
1960
1961}
1962namespace PORT_WOL_MASK {
1963 enum {
1964 ENERGY_Pos = 0,
1965 ENERGY_Msk = (0x1 << ENERGY_Pos),
1966 ENERGY_ENABLED = (0x1 << ENERGY_Pos),
1967 ENERGY_DISABLED = (0x0 << ENERGY_Pos),
1968 LINK_Pos = 1,
1969 LINK_Msk = (0x1 << LINK_Pos),
1970 LINK_ENABLED = (0x1 << LINK_Pos),
1971 LINK_DISABLED = (0x0 << LINK_Pos),
1972 MAGIC_PKT_Pos = 2,
1973 MAGIC_PKT_Msk = (0x1 << MAGIC_PKT_Pos),
1974 MAGIC_PKT_ENABLED = (0x1 << MAGIC_PKT_Pos),
1975 MAGIC_PKT_DISABLED = (0x0 << MAGIC_PKT_Pos),
1976 };
1977
1978}
1979namespace PORT_INT_STATUS {
1980 enum {
1981 ACL_INT_Pos = 0,
1982 ACL_INT_Msk = (0x1 << ACL_INT_Pos),
1983 ACL_INT = (0x1 << ACL_INT_Pos),
1984 PHY_INT_Pos = 1,
1985 PHY_INT_Msk = (0x1 << PHY_INT_Pos),
1986 PHY_INT = (0x1 << PHY_INT_Pos),
1987 PTP_INT_Pos = 2,
1988 PTP_INT_Msk = (0x1 << PTP_INT_Pos),
1989 PTP_INT = (0x1 << PTP_INT_Pos),
1990 SGMII_INT_Pos = 2,
1991 SGMII_INT_Msk = (0x1 << SGMII_INT_Pos),
1992 SGMII_INT = (0x1 << SGMII_INT_Pos),
1993 };
1994
1995}
1996namespace PORT_INT_MASK {
1997 enum {
1998 ACL_INT_Pos = 0,
1999 ACL_INT_Msk = (0x1 << ACL_INT_Pos),
2000 ACL_INT_ENABLED = (0x1 << ACL_INT_Pos),
2001 ACL_INT_DISABLED = (0x0 << ACL_INT_Pos),
2002 PHY_INT_Pos = 1,
2003 PHY_INT_Msk = (0x1 << PHY_INT_Pos),
2004 PHY_INT_ENABLED = (0x1 << PHY_INT_Pos),
2005 PHY_INT_DISABLED = (0x0 << PHY_INT_Pos),
2006 PTP_INT_Pos = 2,
2007 PTP_INT_Msk = (0x1 << PTP_INT_Pos),
2008 PTP_INT_ENABLED = (0x1 << PTP_INT_Pos),
2009 PTP_INT_DISABLED = (0x0 << PTP_INT_Pos),
2010 SGMII_INT_Pos = 2,
2011 SGMII_INT_Msk = (0x1 << SGMII_INT_Pos),
2012 SGMII_INT_ENABLED = (0x1 << SGMII_INT_Pos),
2013 SGMII_INT_DISABLED = (0x0 << SGMII_INT_Pos),
2014 };
2015
2016}
2017namespace PORT_CTRL {
2018 enum {
2019 SRP_ENABLE_Pos = 16,
2020 SRP_ENABLE_Msk = (0x3 << SRP_ENABLE_Pos),
2021 SRP_ENABLE_NONE = (0x0 << SRP_ENABLE_Pos),
2022 SRP_ENABLE_SRP_1 = (0x1 << SRP_ENABLE_Pos),
2023 SRP_ENABLE_SRP_2 = (0x2 << SRP_ENABLE_Pos),
2024 QUEUE_SPLIT_Pos = 24,
2025 QUEUE_SPLIT_Msk = (0x3 << QUEUE_SPLIT_Pos),
2026 QUEUE_SPLIT_SINGLE = (0x0 << QUEUE_SPLIT_Pos),
2027 QUEUE_SPLIT_DUAL = (0x1 << QUEUE_SPLIT_Pos),
2028 QUEUE_SPLIT_QUAD = (0x2 << QUEUE_SPLIT_Pos),
2029 TAIL_TAG_Pos = 26,
2030 TAIL_TAG_Msk = (0x1 << TAIL_TAG_Pos),
2031 TAIL_TAG_DISABLED = (0x0 << TAIL_TAG_Pos),
2032 TAIL_TAG_ENABLED = (0x1 << TAIL_TAG_Pos),
2033 REMOTE_LOOPBACK_Pos = 30,
2034 REMOTE_LOOPBACK_Msk = (0x1 << REMOTE_LOOPBACK_Pos),
2035 REMOTE_LOOPBACK_DISABLED = (0x0 << REMOTE_LOOPBACK_Pos),
2036 REMOTE_LOOPBACK_ENABLED = (0x1 << REMOTE_LOOPBACK_Pos),
2037 LOCAL_LOOPBACK_Pos = 31,
2038 LOCAL_LOOPBACK_Msk = (0x1 << LOCAL_LOOPBACK_Pos),
2039 LOCAL_LOOPBACK_DISABLED = (0x0 << LOCAL_LOOPBACK_Pos),
2040 LOCAL_LOOPBACK_ENABLED = (0x1 << LOCAL_LOOPBACK_Pos),
2041 };
2042
2043}
2044namespace PORT_STATUS {
2045 enum {
2046 RX_FLOW_CTRL_Pos = 24,
2047 RX_FLOW_CTRL_Msk = (0x1 << RX_FLOW_CTRL_Pos),
2048 RX_FLOW_CTRL_DISABLED = (0x0 << RX_FLOW_CTRL_Pos),
2049 RX_FLOW_CTRL_ENABLED = (0x1 << RX_FLOW_CTRL_Pos),
2050 TX_FLOW_CTRL_Pos = 25,
2051 TX_FLOW_CTRL_Msk = (0x3 << TX_FLOW_CTRL_Pos),
2052 TX_FLOW_CTRL_DISABLED = (0x0 << TX_FLOW_CTRL_Pos),
2053 TX_FLOW_CTRL_ENABLED = (0x1 << TX_FLOW_CTRL_Pos),
2054 DUPLEX_Pos = 26,
2055 DUPLEX_Msk = (0x3 << DUPLEX_Pos),
2056 DUPLEX_HALF = (0x0 << DUPLEX_Pos),
2057 DUPLEX_FULL = (0x1 << DUPLEX_Pos),
2058 SPEED_Pos = 27,
2059 SPEED_Msk = (0x3 << SPEED_Pos),
2060 SPEED_10M = (0x0 << SPEED_Pos),
2061 SPEED_100M = (0x1 << SPEED_Pos),
2062 SPEED_1000M = (0x2 << SPEED_Pos),
2063 };
2064
2065}
2066
2067namespace PHY_BASIC_CTL {
2068 enum {
2069 PHY_SPEED_100M_Pos = 6,
2070 PHY_SPEED_100M_Msk = (0x1 << PHY_SPEED_100M_Pos),
2071 PHY_SPEED_100M_10M = (0x0 << PHY_SPEED_100M_Pos),
2072 PHY_SPEED_100M_100M = (0x1 << PHY_SPEED_100M_Pos),
2073 PHY_SPEED_100M_1000M = (0x0 << PHY_SPEED_100M_Pos),
2074 COL_TEST_Pos = 7,
2075 COL_TEST_Msk = (0x1 << COL_TEST_Pos),
2076 COL_TEST_DISABLED = (0x0 << COL_TEST_Pos),
2077 COL_TEST_ENABLED = (0x1 << COL_TEST_Pos),
2078 DUPLEX_Pos = 8,
2079 DUPLEX_Msk = (0x1 << DUPLEX_Pos),
2080 DUPLEX_HALF = (0x0 << DUPLEX_Pos),
2081 DUPLEX_FULl = (0x1 << DUPLEX_Pos),
2082 RESTART_AUTONEG_Pos = 9,
2083 RESTART_AUTONEG_Msk = (0x1 << RESTART_AUTONEG_Pos),
2084 RESTART_AUTONEG = (0x1 << RESTART_AUTONEG_Pos),
2085 ISOLATE_Pos = 10,
2086 ISOLATE_Msk = (0x1 << ISOLATE_Pos),
2087 ISOLATE_DISABLED = (0x0 << ISOLATE_Pos),
2088 ISOLATE_ENABLED = (0x1 << ISOLATE_Pos),
2089 POWER_DOWN_Pos = 11,
2090 POWER_DOWN_Msk = (0x1 << POWER_DOWN_Pos),
2091 POWER_DOWN_DISABLED = (0x0 << POWER_DOWN_Pos),
2092 POWER_DOWN_ENABLED = (0x1 << POWER_DOWN_Pos),
2093 AUTONEG_Pos = 12,
2094 AUTONEG_Msk = (0x1 << AUTONEG_Pos),
2095 AUTONEG_DISABLED = (0x0 << AUTONEG_Pos),
2096 AUTONEG_ENABLED = (0x1 << AUTONEG_Pos),
2097 PHY_SPEED_1000M_Pos = 13,
2098 PHY_SPEED_1000M_Msk = (0x1 << PHY_SPEED_1000M_Pos),
2099 PHY_SPEED_1000M_10M = (0x0 << PHY_SPEED_1000M_Pos),
2100 PHY_SPEED_1000M_100M = (0x0 << PHY_SPEED_1000M_Pos),
2101 PHY_SPEED_1000M_1000M = (0x1 << PHY_SPEED_1000M_Pos),
2102 LOCAL_LOOPBACK_Pos = 14,
2103 LOCAL_LOOPBACK_Msk = (0x1 << LOCAL_LOOPBACK_Pos),
2104 LOCAL_LOOPBACK_DISABLED = (0x0 << LOCAL_LOOPBACK_Pos),
2105 LOCAL_LOOPBACK_ENABLED = (0x1 << LOCAL_LOOPBACK_Pos),
2106 PHY_RESET_Pos = 15,
2107 PHY_RESET_Msk = (0x1 << PHY_RESET_Pos),
2108 PHY_RESET = (0x1 << PHY_RESET_Pos),
2109 };
2110
2111}
2112namespace PHY_BASIC_ST {
2113 enum {
2114 CAPABILITY_Pos = 0,
2115 CAPABILITY_Msk = (0x1 << CAPABILITY_Pos),
2116 CAPABILITY_BASIC = (0x0 << CAPABILITY_Pos),
2117 CAPABILITY_EXTENDED = (0x1 << CAPABILITY_Pos),
2118 JABBER_Pos = 1,
2119 JABBER_Msk = (0x1 << JABBER_Pos),
2120 JABBER_NONE = (0x0 << JABBER_Pos),
2121 JABBER_DETECTED = (0x1 << JABBER_Pos),
2122 LINK_STATUS_Pos = 2,
2123 LINK_STATUS_Msk = (0x1 << LINK_STATUS_Pos),
2124 LINK_STATUS_DOWN = (0x0 << LINK_STATUS_Pos),
2125 LINK_STATUS_UP = (0x1 << LINK_STATUS_Pos),
2126 AUTONEG_CAPABLE_Pos = 3,
2127 AUTONEG_CAPABLE_Msk = (0x1 << AUTONEG_CAPABLE_Pos),
2128 AUTONEG_CAPABLE_NOT_CAPABLE = (0x0 << AUTONEG_CAPABLE_Pos),
2129 AUTONEG_CAPABLE_CAPABLE = (0x1 << AUTONEG_CAPABLE_Pos),
2130 REMOTE_FAULT_Pos = 4,
2131 REMOTE_FAULT_Msk = (0x1 << REMOTE_FAULT_Pos),
2132 REMOTE_FAULT_NONE = (0x0 << REMOTE_FAULT_Pos),
2133 REMOTE_FAULT_DETECTED = (0x1 << REMOTE_FAULT_Pos),
2134 AUTONEG_STATUS_Pos = 5,
2135 AUTONEG_STATUS_Msk = (0x1 << AUTONEG_STATUS_Pos),
2136 AUTONEG_STATUS_NOT_COMPLETE = (0x0 << AUTONEG_STATUS_Pos),
2137 AUTONEG_STATUS_COMPLETE = (0x1 << AUTONEG_STATUS_Pos),
2138 MF_PREAMBLE_SUPRESS_Pos = 6,
2139 MF_PREAMBLE_SUPRESS_Msk = (0x1 << MF_PREAMBLE_SUPRESS_Pos),
2140 MF_PREAMBLE_SUPRESS_NOT_SUPPORTED = (0x0 << MF_PREAMBLE_SUPRESS_Pos),
2141 MF_PREAMBLE_SUPRESS_SUPPORTED = (0x1 << MF_PREAMBLE_SUPRESS_Pos),
2142 EXT_STATUS_Pos = 8,
2143 EXT_STATUS_Msk = (0x1 << EXT_STATUS_Pos),
2144 EXT_STATUS_NOT_PRESENT = (0x0 << EXT_STATUS_Pos),
2145 EXT_STATUS_PRESENT = (0x1 << EXT_STATUS_Pos),
2146 _100BT_HD_Pos = 11,
2147 _100BT_HD_Msk = (0x1 << _100BT_HD_Pos),
2148 _100BT_HD_NOT_SUPPORTED = (0x0 << _100BT_HD_Pos),
2149 _100BT_HD_SUPPORTED = (0x1 << _100BT_HD_Pos),
2150 _10BT_FD_Pos = 12,
2151 _10BT_FD_Msk = (0x1 << _10BT_FD_Pos),
2152 _10BT_FD_NOT_SUPPORTED = (0x0 << _10BT_FD_Pos),
2153 _10BT_FD_SUPPORTED = (0x1 << _10BT_FD_Pos),
2154 _100BTX_HD_Pos = 13,
2155 _100BTX_HD_Msk = (0x1 << _100BTX_HD_Pos),
2156 _100BTX_HD_NOT_SUPPORTED = (0x0 << _100BTX_HD_Pos),
2157 _100BTX_HD_SUPPORTED = (0x1 << _100BTX_HD_Pos),
2158 _100BTX_FD_Pos = 14,
2159 _100BTX_FD_Msk = (0x1 << _100BTX_FD_Pos),
2160 _100BTX_FD_NOT_SUPPORTED = (0x0 << _100BTX_FD_Pos),
2161 _100BTX_FD_SUPPORTED = (0x1 << _100BTX_FD_Pos),
2162 _100BT4_Pos = 15,
2163 _100BT4_Msk = (0x1 << _100BT4_Pos),
2164 _100BT4_NOT_SUPPORTED = (0x0 << _100BT4_Pos),
2165 _100BT4_SUPPORTED = (0x1 << _100BT4_Pos),
2166 };
2167
2168}
2169namespace PHY_A_NEG_ADVERT {
2170 enum {
2171 SELECTOR_Pos = 0,
2172 SELECTOR_Msk = (0x1F << SELECTOR_Pos),
2173 _10BT_HD_Pos = 5,
2174 _10BT_HD_Msk = (0x1 << _10BT_HD_Pos),
2175 _10BT_HD_NOT_ALLOWED = (0x0 << _10BT_HD_Pos),
2176 _10BT_HD_ALLOWED = (0x1 << _10BT_HD_Pos),
2177 _10BT_FD_Pos = 6,
2178 _10BT_FD_Msk = (0x1 << _10BT_FD_Pos),
2179 _10BT_FD_NOT_ALLOWED = (0x0 << _10BT_FD_Pos),
2180 _10BT_FD_ALLOWED = (0x1 << _10BT_FD_Pos),
2181 _100BTX_HD_Pos = 7,
2182 _100BTX_HD_Msk = (0x1 << _100BTX_HD_Pos),
2183 _100BTX_HD_NOT_ALLOWED = (0x0 << _100BTX_HD_Pos),
2184 _100BTX_HD_ALLOWED = (0x1 << _100BTX_HD_Pos),
2185 _100BTX_FD_Pos = 8,
2186 _100BTX_FD_Msk = (0x1 << _100BTX_FD_Pos),
2187 _100BTX_FD_NOT_ALLOWED = (0x0 << _100BTX_FD_Pos),
2188 _100BTX_FD_ALLOWED = (0x1 << _100BTX_FD_Pos),
2189 _100BT4_Pos = 9,
2190 _100BT4_Msk = (0x1 << _100BT4_Pos),
2191 _100BT4_NOT_ALLOWED = (0x0 << _100BT4_Pos),
2192 _100BT4_ALLOWED = (0x1 << _100BT4_Pos),
2193 SYM_PAUSE_Pos = 10,
2194 SYM_PAUSE_Msk = (0x1 << SYM_PAUSE_Pos),
2195 SYM_PAUSE_NOT_ALLOWED = (0x0 << SYM_PAUSE_Pos),
2196 SYM_PAUSE_ALLOWED = (0x1 << SYM_PAUSE_Pos),
2197 ASYM_PAUSE_Pos = 11,
2198 ASYM_PAUSE_Msk = (0x1 << ASYM_PAUSE_Pos),
2199 ASYM_PAUSE_NOT_ALLOWED = (0x0 << ASYM_PAUSE_Pos),
2200 ASYM_PAUSE_ALLOWED = (0x1 << ASYM_PAUSE_Pos),
2201 REMOTE_FAULT_Pos = 13,
2202 REMOTE_FAULT_Msk = (0x1 << REMOTE_FAULT_Pos),
2203 REMOTE_FAULT_NOT_CAPABLE = (0x0 << REMOTE_FAULT_Pos),
2204 REMOTE_FAULT_CAPABLE = (0x1 << REMOTE_FAULT_Pos),
2205 NEXT_PAGE_Pos = 15,
2206 NEXT_PAGE_Msk = (0x1 << NEXT_PAGE_Pos),
2207 NEXT_PAGE_NOT_CAPABLE = (0x0 << NEXT_PAGE_Pos),
2208 NEXT_PAGE_CAPABLE = (0x1 << NEXT_PAGE_Pos),
2209 };
2210
2211 inline uint32_t SELECTOR(uint32_t _x)
2212 { return (((_x) << SELECTOR_Pos) & SELECTOR_Msk); }
2213
2214}
2215namespace PHY_A_NEG_LPA {
2216 enum {
2217 SELECTOR_Pos = 0,
2218 SELECTOR_Msk = (0x1F << SELECTOR_Pos),
2219 _10BT_HD_Pos = 5,
2220 _10BT_HD_Msk = (0x1 << _10BT_HD_Pos),
2221 _10BT_HD_NOT_ALLOWED = (0x0 << _10BT_HD_Pos),
2222 _10BT_HD_ALLOWED = (0x1 << _10BT_HD_Pos),
2223 _10BT_FD_Pos = 6,
2224 _10BT_FD_Msk = (0x1 << _10BT_FD_Pos),
2225 _10BT_FD_NOT_ALLOWED = (0x0 << _10BT_FD_Pos),
2226 _10BT_FD_ALLOWED = (0x1 << _10BT_FD_Pos),
2227 _100BTX_HD_Pos = 7,
2228 _100BTX_HD_Msk = (0x1 << _100BTX_HD_Pos),
2229 _100BTX_HD_NOT_ALLOWED = (0x0 << _100BTX_HD_Pos),
2230 _100BTX_HD_ALLOWED = (0x1 << _100BTX_HD_Pos),
2231 _100BTX_FD_Pos = 8,
2232 _100BTX_FD_Msk = (0x1 << _100BTX_FD_Pos),
2233 _100BTX_FD_NOT_ALLOWED = (0x0 << _100BTX_FD_Pos),
2234 _100BTX_FD_ALLOWED = (0x1 << _100BTX_FD_Pos),
2235 _100BT4_Pos = 9,
2236 _100BT4_Msk = (0x1 << _100BT4_Pos),
2237 _100BT4_NOT_ALLOWED = (0x0 << _100BT4_Pos),
2238 _100BT4_ALLOWED = (0x1 << _100BT4_Pos),
2239 SYM_PAUSE_Pos = 10,
2240 SYM_PAUSE_Msk = (0x1 << SYM_PAUSE_Pos),
2241 SYM_PAUSE_NOT_ALLOWED = (0x0 << SYM_PAUSE_Pos),
2242 SYM_PAUSE_ALLOWED = (0x1 << SYM_PAUSE_Pos),
2243 ASYM_PAUSE_Pos = 11,
2244 ASYM_PAUSE_Msk = (0x1 << ASYM_PAUSE_Pos),
2245 ASYM_PAUSE_NOT_ALLOWED = (0x0 << ASYM_PAUSE_Pos),
2246 ASYM_PAUSE_ALLOWED = (0x1 << ASYM_PAUSE_Pos),
2247 REMOTE_FAULT_Pos = 13,
2248 REMOTE_FAULT_Msk = (0x1 << REMOTE_FAULT_Pos),
2249 REMOTE_FAULT_NONE = (0x0 << REMOTE_FAULT_Pos),
2250 REMOTE_FAULT_DETECTED = (0x1 << REMOTE_FAULT_Pos),
2251 REMOTE_ACKNOWLEDGE_Pos = 14,
2252 REMOTE_ACKNOWLEDGE_Msk = (0x1 << REMOTE_FAULT_Pos),
2253 REMOTE_ACKNOWLEDGE_NONE = (0x0 << REMOTE_FAULT_Pos),
2254 REMOTE_ACKNOWLEDGE_ACKED = (0x1 << REMOTE_FAULT_Pos),
2255 NEXT_PAGE_Pos = 15,
2256 NEXT_PAGE_Msk = (0x1F << NEXT_PAGE_Pos),
2257 NEXT_PAGE_NOT_CAPABLE = (0x0 << NEXT_PAGE_Pos),
2258 NEXT_PAGE_CAPABLE = (0x1 << NEXT_PAGE_Pos),
2259 };
2260
2261 inline uint32_t SELECTOR(uint32_t _x)
2262 { return (((_x) << SELECTOR_Pos) & SELECTOR_Msk); }
2263
2264}
2265namespace PHY_A_NEG_EXP {
2266 enum {
2267 LP_A_NEG_Pos = 0,
2268 LP_A_NEG_Msk = (0x1 << LP_A_NEG_Pos),
2269 LP_A_NEG_NOT_CAPABLE = (0x0 << LP_A_NEG_Pos) & LP_A_NEG_Msk,
2270 LP_A_NEG_CAPABLE = (0x1 << LP_A_NEG_Pos) & LP_A_NEG_Msk,
2271 PAGE_RX_Pos = 1,
2272 PAGE_RX_Msk = (0x1 << PAGE_RX_Pos),
2273 PAGE_RX_WAITING = (0x0 << PAGE_RX_Pos) & PAGE_RX_Msk,
2274 PAGE_RX_RXED = (0x1 << PAGE_RX_Pos) & PAGE_RX_Msk,
2275 LOCAL_NEXT_PAGE_Pos = 2,
2276 LOCAL_NEXT_PAGE_Msk = (0x1 << LOCAL_NEXT_PAGE_Pos),
2277 LOCAL_NEXT_PAGE_NOT_CAPABLE = (0x0 << LOCAL_NEXT_PAGE_Pos) & LOCAL_NEXT_PAGE_Msk,
2278 LOCAL_NEXT_PAGE_CAPABLE = (0x1 << LOCAL_NEXT_PAGE_Pos) & LOCAL_NEXT_PAGE_Msk,
2279 LPA_NEXT_PAGE_Pos = 3,
2280 LPA_NEXT_PAGE_Msk = (0x1 << LPA_NEXT_PAGE_Pos),
2281 LPA_NEXT_PAGE_NOT_CAPABLE = (0x0 << LPA_NEXT_PAGE_Pos) & LPA_NEXT_PAGE_Msk,
2282 LPA_NEXT_PAGE_CAPABLE = (0x1 << LPA_NEXT_PAGE_Pos) & LPA_NEXT_PAGE_Msk,
2283 PARALLEL_FAULT_Pos = 0,
2284 PARALLEL_FAULT_Msk = (0x1 << PARALLEL_FAULT_Pos),
2285 PARALLEL_FAULT_NONE = (0x0 << PARALLEL_FAULT_Pos) & PARALLEL_FAULT_Msk,
2286 PARALLEL_FAULT_DETECTED = (0x1 << PARALLEL_FAULT_Pos) & PARALLEL_FAULT_Msk,
2287 };
2288
2289}
2290namespace PHY_A_NEG_NEXT_PG {
2291 enum {
2292 MESSAGE_Pos = 0,
2293 MESSAGE_Msk = (0x7FF << MESSAGE_Pos),
2294 TOGGLE_Pos = 11,
2295 TOGGLE_Msk = (0x1 << TOGGLE_Pos),
2296 ACKNOWLEDGE2_Pos = 12,
2297 ACKNOWLEDGE2_Msk = (0x1 << ACKNOWLEDGE2_Pos),
2298 ACKNOWLEDGE2_NACK = (0x0 << ACKNOWLEDGE2_Pos),
2299 ACKNOWLEDGE2_ACK = (0x1 << ACKNOWLEDGE2_Pos),
2300 PAGE_TYPE_Pos = 13,
2301 PAGE_TYPE_Msk = (0x1 << PAGE_TYPE_Pos),
2302 PAGE_TYPE_UNFORMATTED = (0x0 << PAGE_TYPE_Pos),
2303 PAGE_TYPE_MESSAGE = (0x1 << PAGE_TYPE_Pos),
2304 NEXT_PAGE_Pos = 15,
2305 NEXT_PAGE_Msk = (0x1 << NEXT_PAGE_Pos),
2306 NEXT_PAGE_LAST = (0x0 << NEXT_PAGE_Pos),
2307 NEXT_PAGE_MORE_FOLLOW = (0x1 << NEXT_PAGE_Pos),
2308 };
2309
2310 inline uint32_t MESSAGE(uint32_t _x)
2311 { return (((_x) << MESSAGE_Pos) & MESSAGE_Msk); }
2312 inline uint32_t TOGGLE(uint32_t _x)
2313 { return (((_x) << TOGGLE_Pos) & TOGGLE_Msk); }
2314
2315}
2316namespace PHY_LP_NEXT_PG_ABIL {
2317 enum {
2318 MESSAGE_Pos = 0,
2319 MESSAGE_Msk = (0x7FF << MESSAGE_Pos),
2320 TOGGLE_Pos = 11,
2321 TOGGLE_Msk = (0x1 << TOGGLE_Pos),
2322 ACKNOWLEDGE2_Pos = 12,
2323 ACKNOWLEDGE2_Msk = (0x1 << ACKNOWLEDGE2_Pos),
2324 ACKNOWLEDGE2_NACK = (0x0 << ACKNOWLEDGE2_Pos),
2325 ACKNOWLEDGE2_ACK = (0x1 << ACKNOWLEDGE2_Pos),
2326 PAGE_TYPE_Pos = 13,
2327 PAGE_TYPE_Msk = (0x1 << PAGE_TYPE_Pos),
2328 PAGE_TYPE_UNFORMATTED = (0x0 << PAGE_TYPE_Pos),
2329 PAGE_TYPE_MESSAGE = (0x1 << PAGE_TYPE_Pos),
2330 ACKNOWLEDGE_Pos = 14,
2331 ACKNOWLEDGE_Msk = (0x1 << ACKNOWLEDGE_Pos),
2332 ACKNOWLEDGE_NACK = (0x0 << ACKNOWLEDGE_Pos),
2333 ACKNOWLEDGE_ACK = (0x1 << ACKNOWLEDGE_Pos),
2334 NEXT_PAGE_Pos = 15,
2335 NEXT_PAGE_Msk = (0x1 << NEXT_PAGE_Pos),
2336 NEXT_PAGE_LAST = (0x0 << NEXT_PAGE_Pos),
2337 NEXT_PAGE_MORE_FOLLOW = (0x1 << NEXT_PAGE_Pos),
2338 };
2339
2340 inline uint32_t MESSAGE(uint32_t _x)
2341 { return (((_x) << MESSAGE_Pos) & MESSAGE_Msk); }
2342 inline uint32_t TOGGLE(uint32_t _x)
2343 { return (((_x) << TOGGLE_Pos) & TOGGLE_Msk); }
2344
2345}
2346namespace PHY_GBCR {
2347 enum {
2348 _1000BT_HD_Pos = 8,
2349 _1000BT_HD_Msk = (0x1 << _1000BT_HD_Pos),
2350 _1000BT_HD_NOT_CAPABLE = (0x0 << _1000BT_HD_Pos),
2351 _1000BT_HD_CAPABLE = (0x1 << _1000BT_HD_Pos),
2352 _1000BT_FD_Pos = 9,
2353 _1000BT_FD_Msk = (0x1 << _1000BT_FD_Pos),
2354 _1000BT_FD_NOT_CAPABLE = (0x0 << _1000BT_FD_Pos),
2355 _1000BT_FD_CAPABLE = (0x1 << _1000BT_FD_Pos),
2356 DEVICE_TYPE_Pos = 10,
2357 DEVICE_TYPE_Msk = (0x1 << DEVICE_TYPE_Pos),
2358 DEVICE_TYPE_SINGLE_PORT = (0x0 << DEVICE_TYPE_Pos),
2359 DEVICE_TYPE_MULTI_PORT = (0x1 << DEVICE_TYPE_Pos),
2360 MANUAL_ROLE_CFG_Pos = 11,
2361 MANUAL_ROLE_CFG_Msk = (0x1 << MANUAL_ROLE_CFG_Pos),
2362 MANUAL_ROLE_CFG_SLAVE = (0x0 << MANUAL_ROLE_CFG_Pos),
2363 MANUAL_ROLE_CFG_MASTER = (0x1 << MANUAL_ROLE_CFG_Pos),
2364 MANUAL_ROLE_Pos = 12,
2365 MANUAL_ROLE_Msk = (0x1 << MANUAL_ROLE_Pos),
2366 MANUAL_ROLE_DISABLED = (0x0 << MANUAL_ROLE_Pos),
2367 MANUAL_ROLE_ENABLED = (0x1 << MANUAL_ROLE_Pos),
2368 TX_TEST_MODE_Pos = 13,
2369 TX_TEST_MODE_Msk = (0x7 << TX_TEST_MODE_Pos),
2370 TX_TEST_MODE_NORMAL_OPS = (0x0 << TX_TEST_MODE_Pos),
2371 TX_TEST_MODE_MODE_1_WAVE = (0x1 << TX_TEST_MODE_Pos),
2372 TX_TEST_MODE_MODE_2_JITTER_MASTER = (0x2 << TX_TEST_MODE_Pos),
2373 TX_TEST_MODE_MODE_3_JITTER_SLAVE = (0x3 << TX_TEST_MODE_Pos),
2374 TX_TEST_MODE_MODE_4_DISTORTION = (0x4 << TX_TEST_MODE_Pos),
2375 };
2376
2377}
2378namespace PHY_GBSR {
2379 enum {
2380 IDLE_ERR_CNT_Pos = 0,
2381 IDLE_ERR_CNT_Msk = (0xFF << IDLE_ERR_CNT_Pos),
2382 LP_1000BT_HD_Pos = 10,
2383 LP_1000BT_HD_Msk = (0x1 << LP_1000BT_HD_Pos),
2384 LP_1000BT_HD_NOT_CAPABLE = (0x0 << LP_1000BT_HD_Pos),
2385 LP_1000BT_HD_CAPABLE = (0x1 << LP_1000BT_HD_Pos),
2386 LP_1000BT_FD_Pos = 11,
2387 LP_1000BT_FD_Msk = (0x1 << LP_1000BT_FD_Pos),
2388 LP_1000BT_FD_NOT_CAPABLE = (0x0 << LP_1000BT_FD_Pos),
2389 LP_1000BT_FD_CAPABLE = (0x1 << LP_1000BT_FD_Pos),
2390 REMOTE_RX_STAT_Pos = 12,
2391 REMOTE_RX_STAT_Msk = (0x1 << REMOTE_RX_STAT_Pos),
2392 REMOTE_RX_STAT_NOT_OK = (0x0 << REMOTE_RX_STAT_Pos),
2393 REMOTE_RX_STAT_OK = (0x1 << REMOTE_RX_STAT_Pos),
2394 LOCAL_RX_STAT_Pos = 13,
2395 LOCAL_RX_STAT_Msk = (0x1 << LOCAL_RX_STAT_Pos),
2396 LOCAL_RX_STAT_NOT_OK = (0x0 << LOCAL_RX_STAT_Pos),
2397 LOCAL_RX_STAT_OK = (0x1 << LOCAL_RX_STAT_Pos),
2398 LOCAL_ROLE_Pos = 14,
2399 LOCAL_ROLE_Msk = (0x1 << LOCAL_ROLE_Pos),
2400 LOCAL_ROLE_SLAVE = (0x0 << LOCAL_ROLE_Pos),
2401 LOCAL_ROLE_MASTER = (0x1 << LOCAL_ROLE_Pos),
2402 ROLE_FAULT_Pos = 15,
2403 ROLE_FAULT_Msk = (0x1 << ROLE_FAULT_Pos),
2404 ROLE_FAULT_NONE = (0x0 << ROLE_FAULT_Pos),
2405 ROLE_FAULT_DETECTED = (0x1 << ROLE_FAULT_Pos),
2406 };
2407
2408}
2409namespace PHY_MMD_SETUP {
2410 enum {
2411 DEV_ADDR_Pos = 0,
2412 DEV_ADDR_Msk = (0x1F << DEV_ADDR_Pos),
2413 OP_MODE_Pos = 14,
2414 OP_MODE_Msk = (0x3 << OP_MODE_Pos),
2415 OP_MODE_REGISTER = (0x00 << OP_MODE_Pos),
2416 OP_MODE_DATA = (0x01 << OP_MODE_Pos),
2417 OP_MODE_DATA_INCR = (0x02 << OP_MODE_Pos),
2418 OP_MODE_DATA_INCR_WRITE = (0x03 << OP_MODE_Pos),
2419 };
2420
2421 inline uint32_t DEV_ADDR(uint32_t _x)
2422 { return (((_x) << DEV_ADDR_Pos) & DEV_ADDR_Pos); }
2423 inline uint32_t OP_MODE(uint32_t _x)
2424 { return (((_x) << OP_MODE_Pos) & OP_MODE_Pos); }
2425
2426}
2427namespace PHY_EXT_STATUS {
2428 enum {
2429 _1000BT_HD_Pos = 12,
2430 _1000BT_HD_Msk = (0x1 << _1000BT_HD_Pos),
2431 _1000BT_HD_NOT_CAPABLE = (0x0 << _1000BT_HD_Pos),
2432 _1000BT_HD_CAPABLE = (0x1 << _1000BT_HD_Pos),
2433 _1000BT_FD_Pos = 13,
2434 _1000BT_FD_Msk = (0x1 << _1000BT_FD_Pos),
2435 _1000BT_FD_NOT_CAPABLE = (0x0 << _1000BT_FD_Pos),
2436 _1000BT_FD_CAPABLE = (0x1 << _1000BT_FD_Pos),
2437 _1000BX_HD_Pos = 14,
2438 _1000BX_HD_Msk = (0x1 << _1000BX_HD_Pos),
2439 _1000BX_HD_NOT_CAPABLE = (0x0 << _1000BX_HD_Pos),
2440 _1000BX_HD_CAPABLE = (0x1 << _1000BX_HD_Pos),
2441 _1000BX_FD_Pos = 15,
2442 _1000BX_FD_Msk = (0x1 << _1000BX_FD_Pos),
2443 _1000BX_FD_NOT_CAPABLE = (0x0 << _1000BX_FD_Pos),
2444 _1000BX_FD_CAPABLE = (0x1 << _1000BX_FD_Pos),
2445 };
2446
2447}
2448namespace PHY_REMOTE_LOOPBACK {
2449 enum {
2450 LINK_MD_PASS_Pos = 0,
2451 LINK_MD_PASS_Msk = (0x1 << LINK_MD_PASS_Pos),
2452 LINK_MD_PASS_DISABLED = (0x0 << LINK_MD_PASS_Pos),
2453 LINK_MD_PASS_ENABLED = (0x1 << LINK_MD_PASS_Pos),
2454 LINK_MD_10BT_Pos = 1,
2455 LINK_MD_10BT_Msk = (0x1 << LINK_MD_10BT_Pos),
2456 LINK_MD_10BT_DISABLED = (0x0 << LINK_MD_10BT_Pos),
2457 LINK_MD_10BT_ENABLED = (0x1 << LINK_MD_10BT_Pos),
2458 _10BT_PREAMBLE_Pos = 2,
2459 _10BT_PREAMBLE_Msk = (0x1 << _10BT_PREAMBLE_Pos),
2460 _10BT_PREAMBLE_DISABLED = (0x0 << _10BT_PREAMBLE_Pos),
2461 _10BT_PREAMBLE_ENABLED = (0x1 << _10BT_PREAMBLE_Pos),
2462 LED_CTRL_TEST_Pos = 3,
2463 LED_CTRL_TEST_Msk = (0x1 << LED_CTRL_TEST_Pos),
2464 LED_CTRL_TEST_DISABLED = (0x0 << LED_CTRL_TEST_Pos),
2465 LED_CTRL_TEST_ENABLED = (0x1 << LED_CTRL_TEST_Pos),
2466 LED_CTRL_Pos = 4,
2467 LED_CTRL_Msk = (0x1 << LED_CTRL_Pos),
2468 LED_CTRL_DISABLED = (0x0 << LED_CTRL_Pos),
2469 LED_CTRL_ENABLED = (0x1 << LED_CTRL_Pos),
2470 LED_SEL_Pos = 6,
2471 LED_SEL_Msk = (0x1 << LED_SEL_Pos),
2472 LED_SEL_DISABLED = (0x0 << LED_SEL_Pos),
2473 LED_SEL_ENABLED = (0x1 << LED_SEL_Pos),
2474 REMOTE_LOOPBACK_Pos = 8,
2475 REMOTE_LOOPBACK_Msk = (0x1 << REMOTE_LOOPBACK_Pos),
2476 REMOTE_LOOPBACK_DISABLED = (0x0 << REMOTE_LOOPBACK_Pos),
2477 REMOTE_LOOPBACK_ENABLED = (0x1 << REMOTE_LOOPBACK_Pos),
2478 };
2479
2480}
2481namespace PHY_LINK_MD {
2482 enum {
2483 CABLE_STATUS_Pos = 8,
2484 CABLE_STATUS_Msk = (0x3 << CABLE_STATUS_Pos),
2485 CABLE_STATUS_NORMAL = (0x0 << CABLE_STATUS_Pos),
2486 CABLE_STATUS_OPEN = (0x1 << CABLE_STATUS_Pos),
2487 CABLE_STATUS_SHORT = (0x2 << CABLE_STATUS_Pos),
2488 TEST_PAIR_Pos = 12,
2489 TEST_PAIR_Msk = (0x3 << TEST_PAIR_Pos),
2490 TEST_PAIR_A = (0x0 << TEST_PAIR_Pos),
2491 TEST_PAIR_B = (0x1 << TEST_PAIR_Pos),
2492 TEST_PAIR_C = (0x2 << TEST_PAIR_Pos),
2493 TEST_PAIR_D = (0x3 << TEST_PAIR_Pos),
2494 LINX_TX_Pos = 14,
2495 LINX_TX_Msk = (0x1 << LINX_TX_Pos),
2496 LINX_TX_ENABLED = (0x0 << LINX_TX_Pos),
2497 LINX_TX_DISABLED = (0x1 << LINX_TX_Pos),
2498 CABLE_TEST_Pos = 15,
2499 CABLE_TEST_Msk = (0x1 << CABLE_TEST_Pos),
2500 CABLE_TEST_DONE = (0x0 << CABLE_TEST_Pos),
2501 CABLE_TEST_DISABLED = (0x0 << CABLE_TEST_Pos),
2502 CABLE_TEST_ENABLED = (0x1 << CABLE_TEST_Pos),
2503 CABLE_TEST_IN_PROGRESS = (0x1 << CABLE_TEST_Pos),
2504 };
2505
2506}
2507namespace PHY_PMA_STATUS {
2508 enum {
2509 _100BTX_LINK_STATUS_Pos = 0,
2510 _100BTX_LINK_STATUS_Msk = (0x3 << _100BTX_LINK_STATUS_Pos),
2511 _100BTX_LINK_STATUS_DOWN = (0x0 << _100BTX_LINK_STATUS_Pos),
2512 _100BTX_LINK_STATUS_UP = (0x1 << _100BTX_LINK_STATUS_Pos),
2513 _1000BT_LINK_STATUS_Pos = 0,
2514 _1000BT_LINK_STATUS_Msk = (0x3 << _1000BT_LINK_STATUS_Pos),
2515 _1000BT_LINK_STATUS_DOWN = (0x0 << _1000BT_LINK_STATUS_Pos),
2516 _1000BT_LINK_STATUS_UP = (0x1 << _1000BT_LINK_STATUS_Pos),
2517 };
2518
2519}
2520namespace PHY_INT {
2521 enum {
2522 LINK_UP_IRQ_Pos = 0,
2523 LINK_UP_IRQ_Msk = (0x1 << LINK_UP_IRQ_Pos),
2524 REMOTE_FAULT_IRQ_Pos = 1,
2525 REMOTE_FAULT_IRQ_Msk = (0x1 << REMOTE_FAULT_IRQ_Pos),
2526 LINK_DOWN_IRQ_Pos = 2,
2527 LINK_DOWN_IRQ_Msk = (0x1 << LINK_DOWN_IRQ_Pos),
2528 LP_ACK_IRQ_Pos = 3,
2529 LP_ACK_IRQ_Msk = (0x1 << LP_ACK_IRQ_Pos),
2530 PARALLEL_FAULT_IRQ_Pos = 4,
2531 PARALLEL_FAULT_IRQ_Msk = (0x1 << PARALLEL_FAULT_IRQ_Pos),
2532 PG_RX_IRQ_Pos = 5,
2533 PG_RX_IRQ_Msk = (0x1 << PG_RX_IRQ_Pos),
2534 RX_ERR_IRQ_Pos = 6,
2535 RX_ERR_IRQ_Msk = (0x1 << RX_ERR_IRQ_Pos),
2536 JABBER_IRQ_Pos = 7,
2537 JABBER_IRQ_Msk = (0x1 << JABBER_IRQ_Pos),
2538 LINK_UP_Pos = 8,
2539 LINK_UP_Msk = (0x1 << LINK_UP_Pos),
2540 LINK_UP_DISABLED = (0x0 << LINK_UP_Pos),
2541 LINK_UP_ENABLED = (0x1 << LINK_UP_Pos),
2542 REMOTE_FAULT_Pos = 9,
2543 REMOTE_FAULT_Msk = (0x1 << REMOTE_FAULT_Pos),
2544 REMOTE_FAULT_DISABLED = (0x0 << REMOTE_FAULT_Pos),
2545 REMOTE_FAULT_ENABLED = (0x1 << REMOTE_FAULT_Pos),
2546 LINK_DOWN_Pos = 10,
2547 LINK_DOWN_Msk = (0x1 << LINK_DOWN_Pos),
2548 LINK_DOWN_DISABLED = (0x0 << LINK_DOWN_Pos),
2549 LINK_DOWN_ENABLED = (0x1 << LINK_DOWN_Pos),
2550 PARALLEL_FAULT_Pos = 11,
2551 PARALLEL_FAULT_Msk = (0x1 << PARALLEL_FAULT_Pos),
2552 PARALLEL_FAULT_DISABLED = (0x0 << PARALLEL_FAULT_Pos),
2553 PARALLEL_FAULT_ENABLED = (0x1 << PARALLEL_FAULT_Pos),
2554 PG_RX_Pos = 12,
2555 PG_RX_Msk = (0x1 << PG_RX_Pos),
2556 PG_RX_DISABLED = (0x0 << PG_RX_Pos),
2557 PG_RX_ENABLED = (0x1 << PG_RX_Pos),
2558 RX_ERR_Pos = 13,
2559 RX_ERR_Msk = (0x1 << RX_ERR_Pos),
2560 RX_ERR_DISABLED = (0x0 << RX_ERR_Pos),
2561 RX_ERR_ENABLED = (0x1 << RX_ERR_Pos),
2562 JABBER_Pos = 14,
2563 JABBER_Msk = (0x1 << JABBER_Pos),
2564 JABBER_DISABLED = (0x0 << JABBER_Pos),
2565 JABBER_ENABLED = (0x1 << JABBER_Pos),
2566 _100BTX_LINK_STATUS_Pos = 15,
2567 _100BTX_LINK_STATUS_Msk = (0x1 << _100BTX_LINK_STATUS_Pos),
2568 _100BTX_LINK_STATUS_DISABLED = (0x0 << _100BTX_LINK_STATUS_Pos),
2569 _100BTX_LINK_STATUS_ENABLED = (0x1 << _100BTX_LINK_STATUS_Pos),
2570 };
2571
2572}
2573namespace PHY_AUTO_MDIX {
2574 enum {
2575 AUTO_MDIX_DISABLE_Pos = 6,
2576 AUTO_MDIX_DISABLE_Msk = (0x1 << AUTO_MDIX_DISABLE_Pos),
2577 AUTO_MDIX_DISABLE_DISABLED = (0x1 << AUTO_MDIX_DISABLE_Pos),
2578 AUTO_MDIX_DISABLE_ENABLED = (0x0 << AUTO_MDIX_DISABLE_Pos),
2579 MDI_MODE_Pos = 7,
2580 MDI_MODE_Msk = (0x1 << MDI_MODE_Pos),
2581 MDI_MODE_MDI = (0x0 << MDI_MODE_Pos),
2582 MDI_MODE_MDIX = (0x1 << MDI_MODE_Pos),
2583 };
2584
2585}
2586namespace PHY_CTL_2 {
2587 enum {
2588 _1000BT_ROLE_Pos = 2,
2589 _1000BT_ROLE_Msk = (0x1 << _1000BT_ROLE_Pos),
2590 _1000BT_ROLE_MASTER = (0x1 << _1000BT_ROLE_Pos),
2591 _1000BT_ROLE_SLAVE = (0x0 << _1000BT_ROLE_Pos),
2592 DUPLEX_Pos = 3,
2593 DUPLEX_Msk = (0x1 << DUPLEX_Pos),
2594 DUPLEX_FULL = (0x1 << DUPLEX_Pos),
2595 DUPLEX_HALF = (0x0 << DUPLEX_Pos),
2596 SPEED_IS_10BT_Pos = 4,
2597 SPEED_IS_10BT_Msk = (0x1 << SPEED_IS_10BT_Pos),
2598 SPEED_IS_10BT_TRUE = (0x1 << SPEED_IS_10BT_Pos),
2599 SPEED_IS_10BT_FALSE = (0x0 << SPEED_IS_10BT_Pos),
2600 SPEED_IS_100BTX_Pos = 5,
2601 SPEED_IS_100BTX_Msk = (0x1 << SPEED_IS_100BTX_Pos),
2602 SPEED_IS_100BTX_TRUE = (0x1 << SPEED_IS_100BTX_Pos),
2603 SPEED_IS_100BTX_FALSE = (0x0 << SPEED_IS_100BTX_Pos),
2604 SPEED_IS_1000BT_Pos = 6,
2605 SPEED_IS_1000BT_Msk = (0x1 << SPEED_IS_1000BT_Pos),
2606 SPEED_IS_1000BT_TRUE = (0x1 << SPEED_IS_1000BT_Pos),
2607 SPEED_IS_1000BT_FALSE = (0x0 << SPEED_IS_1000BT_Pos),
2608 JABBER_COUNTER_Pos = 9,
2609 JABBER_COUNTER_Msk = (0x1 << JABBER_COUNTER_Pos),
2610 JABBER_COUNTER_DISABLED = (0x0 << JABBER_COUNTER_Pos),
2611 JABBER_COUNTER_ENABLED = (0x1 << JABBER_COUNTER_Pos),
2612 };
2613
2614}
2615
2616namespace PORT_XMII_CTRL {
2617 enum {
2618 RGMII_IBS_LINK_STATUS_Pos = 0,
2619 RGMII_IBS_LINK_STATUS_Msk = (0x1 << RGMII_IBS_LINK_STATUS_Pos),
2620 RGMII_IBS_LINK_STATUS_UP = (0x1 << RGMII_IBS_LINK_STATUS_Pos),
2621 RGMII_IBS_LINK_STATUS_DOWN = (0x0 << RGMII_IBS_LINK_STATUS_Pos),
2622 RGMII_IBS_RCLK_SPD_Pos = 1,
2623 RGMII_IBS_RCLK_SPD_Msk = (0x3 << RGMII_IBS_RCLK_SPD_Pos),
2624 RGMII_IBS_RCLK_SPD_2_5M = (0x0 << RGMII_IBS_RCLK_SPD_Pos),
2625 RGMII_IBS_RCLK_SPD_25M = (0x1 << RGMII_IBS_RCLK_SPD_Pos),
2626 RGMII_IBS_RCLK_SPD_125M = (0x2 << RGMII_IBS_RCLK_SPD_Pos),
2627 RGMII_IBS_DUPLEX_Pos = 3,
2628 RGMII_IBS_DUPLEX_Msk = (0x1 << RGMII_IBS_DUPLEX_Pos),
2629 RGMII_IBS_DUPLEX_FULL = (0x1 << RGMII_IBS_DUPLEX_Pos),
2630 RGMII_IBS_DUPLEX_HALF = (0x0 << RGMII_IBS_DUPLEX_Pos),
2631 MII_MODE_Pos = 16,
2632 MII_MODE_Msk = (0x3 << MII_MODE_Pos),
2633 MII_MODE_MII = (0x0 << MII_MODE_Pos),
2634 MII_MODE_RMII = (0x1 << MII_MODE_Pos),
2635 MII_MODE_GMII = (0x2 << MII_MODE_Pos),
2636 MII_MODE_RGMII = (0x3 << MII_MODE_Pos),
2637 MII_CFG_Pos = 18,
2638 MII_CFG_Msk = (0x1 << MII_CFG_Pos),
2639 MII_CFG_MII_PHY = (0x0 << MII_CFG_Pos),
2640 MII_CFG_MII_MAC = (0x1 << MII_CFG_Pos),
2641 MII_CFG_RMII_CLK_IN = (0x0 << MII_CFG_Pos),
2642 MII_CFG_RMII_CLK_OUT = (0x1 << MII_CFG_Pos),
2643 MII_CFG_RGMII_IBS_DISABLED = (0x0 << MII_CFG_Pos),
2644 MII_CFG_RGMII_IBS_ENABLED = (0x1 << MII_CFG_Pos),
2645 RGMII_EGRESS_DLY_Pos = 19,
2646 RGMII_EGRESS_DLY_Msk = (0x1 << RGMII_EGRESS_DLY_Pos),
2647 RGMII_EGRESS_DLY_ENABLED = (0x1 << RGMII_EGRESS_DLY_Pos),
2648 RGMII_EGRESS_DLY_DISABLED = (0x0 << RGMII_EGRESS_DLY_Pos),
2649 RGMII_INGRESS_DLY_Pos = 20,
2650 RGMII_INGRESS_DLY_Msk = (0x1 << RGMII_INGRESS_DLY_Pos),
2651 RGMII_INGRESS_DLY_ENABLED = (0x1 << RGMII_INGRESS_DLY_Pos),
2652 RGMII_INGRESS_DLY_DISABLED = (0x0 << RGMII_INGRESS_DLY_Pos),
2653 MII_SEL_EDGE_Pos = 21,
2654 MII_SEL_EDGE_Msk = (0x1 << MII_SEL_EDGE_Pos),
2655 MII_SEL_EDGE_FALLINg = (0x1 << MII_SEL_EDGE_Pos),
2656 MII_SEL_EDGE_RISING = (0x0 << MII_SEL_EDGE_Pos),
2657 MII_1000M_Pos = 22,
2658 MII_1000M_Msk = (0x1 << MII_1000M_Pos),
2659 MII_1000M_1000M = (0x1 << MII_1000M_Pos),
2660 MII_1000M_10_OR_100M = (0x0 << MII_1000M_Pos),
2661 MII_CLK_SEL_Pos = 23,
2662 MII_CLK_SEL_Msk = (0x1 << MII_CLK_SEL_Pos),
2663 MII_CLK_SEL_MASTER = (0x1 << MII_CLK_SEL_Pos),
2664 MII_CLK_SEL_SLAVE = (0x0 << MII_CLK_SEL_Pos),
2665 GRXC_Pos = 24,
2666 GRXC_Msk = (0x1 << GRXC_Pos),
2667 GRXC_ENABLED = (0x1 << GRXC_Pos),
2668 GRXC_DISABLED = (0x0 << GRXC_Pos),
2669 RX_FLOW_CTRL_Pos = 27,
2670 RX_FLOW_CTRL_Msk = (0x1 << RX_FLOW_CTRL_Pos),
2671 RX_FLOW_CTRL_ENABLED = (0x1 << RX_FLOW_CTRL_Pos),
2672 RX_FLOW_CTRL_DISABLED = (0x0 << RX_FLOW_CTRL_Pos),
2673 MII_SPEED_Pos = 28,
2674 MII_SPEED_Msk = (0x1 << MII_SPEED_Pos),
2675 MII_SPEED_100M = (0x1 << MII_SPEED_Pos),
2676 MII_SPEED_10M = (0x0 << MII_SPEED_Pos),
2677 TX_FLOW_CTRL_Pos = 29,
2678 TX_FLOW_CTRL_Msk = (0x1 << TX_FLOW_CTRL_Pos),
2679 TX_FLOW_CTRL_ENABLED = (0x1 << TX_FLOW_CTRL_Pos),
2680 TX_FLOW_CTRL_DISABLED = (0x0 << TX_FLOW_CTRL_Pos),
2681 DUPLEX_Pos = 30,
2682 DUPLEX_Msk = (0x1 << DUPLEX_Pos),
2683 DUPLEX_FULL = (0x1 << DUPLEX_Pos),
2684 DUPLEX_HALF = (0x0 << DUPLEX_Pos),
2685 SGMII_MODE_Pos = 3,
2686 SGMII_MODE_Msk = (0x1 << SGMII_MODE_Pos),
2687 SGMII_MODE_ENABLED = (0x1 << SGMII_MODE_Pos),
2688 SGMII_MODE_DISABLED = (0x0 << SGMII_MODE_Pos),
2689 };
2690
2691}
2692
2693namespace PORT_MAC_CTRL {
2694 enum {
2695 COUNT_PREAMBLE_Pos = 0,
2696 COUNT_PREAMBLE_Msk = (0x1 << COUNT_PREAMBLE_Pos),
2697 COUNT_PREAMBLE_ENABLED = (0x1 << COUNT_PREAMBLE_Pos),
2698 COUNT_PREAMBLE_DISABLED = (0x0 << COUNT_PREAMBLE_Pos),
2699 COUNT_IFG_Pos = 1,
2700 COUNT_IFG_Msk = (0x1 << COUNT_IFG_Pos),
2701 COUNT_IFG_ENABLED = (0x1 << COUNT_IFG_Pos),
2702 COUNT_IFG_DISABLED = (0x0 << COUNT_IFG_Pos),
2703 IN_LIMIT_MODE_Pos = 2,
2704 IN_LIMIT_MODE_Msk = (0x3 << IN_LIMIT_MODE_Pos),
2705 IN_LIMIT_MODE_ALL = (0x0 << IN_LIMIT_MODE_Pos),
2706 IN_LIMIT_MODE_UCAST = (0x1 << IN_LIMIT_MODE_Pos),
2707 IN_LIMIT_MODE_MCAST = (0x2 << IN_LIMIT_MODE_Pos),
2708 IN_LIMIT_MODE_BCAST = (0x3 << IN_LIMIT_MODE_Pos),
2709 IN_FLOW_CTRL_Pos = 4,
2710 IN_FLOW_CTRL_Msk = (0x1 << IN_FLOW_CTRL_Pos),
2711 IN_FLOW_CTRL_ENABLED = (0x1 << IN_FLOW_CTRL_Pos),
2712 IN_FLOW_CTRL_DISABLED = (0x0 << IN_FLOW_CTRL_Pos),
2713 IN_PKT_RATE_Pos = 5,
2714 IN_PKT_RATE_Msk = (0x1 << IN_PKT_RATE_Pos),
2715 IN_PKT_RATE_ENABLED = (0x1 << IN_PKT_RATE_Pos),
2716 IN_PKT_RATE_DISABLED = (0x0 << IN_PKT_RATE_Pos),
2717 IN_RATE_Pos = 6,
2718 IN_RATE_Msk = (0x1 << IN_RATE_Pos),
2719 IN_RATE_PORT = (0x1 << IN_RATE_Pos),
2720 IN_RATE_PRIO = (0x0 << IN_RATE_Pos),
2721 _1000BT_EEE_Pos = 14,
2722 _1000BT_EEE_Msk = (0x1 << _1000BT_EEE_Pos),
2723 _1000BT_EEE_ENABLED = (0x0 << _1000BT_EEE_Pos),
2724 _1000BT_EEE_DISABLED = (0x1 << _1000BT_EEE_Pos),
2725 _100BTX_EEE_Pos = 15,
2726 _100BTX_EEE_Msk = (0x1 << _100BTX_EEE_Pos),
2727 _100BTX_EEE_ENABLED = (0x0 << _100BTX_EEE_Pos),
2728 _100BTX_EEE_DISABLED = (0x1 << _100BTX_EEE_Pos),
2729 PASS_ALL_Pos = 16,
2730 PASS_ALL_Msk = (0x1 << PASS_ALL_Pos),
2731 PASS_ALL_ENABLED = (0x1 << PASS_ALL_Pos),
2732 PASS_ALL_DISABLED = (0x0 << PASS_ALL_Pos),
2733 BACK_PRESSURE_Pos = 17,
2734 BACK_PRESSURE_Msk = (0x1 << BACK_PRESSURE_Pos),
2735 BACK_PRESSURE_ENABLED = (0x1 << BACK_PRESSURE_Pos),
2736 BACK_PRESSURE_DISABLED = (0x0 << BACK_PRESSURE_Pos),
2737 JUMBO_FRAME_Pos = 24,
2738 JUMBO_FRAME_Msk = (0x1 << JUMBO_FRAME_Pos),
2739 BCAST_STORM_PROT_Pos = 25,
2740 BCAST_STORM_PROT_Msk = (0x1 << BCAST_STORM_PROT_Pos),
2741 BCAST_STORM_PROT_ENABLED = (0x1 << BCAST_STORM_PROT_Pos),
2742 BCAST_STORM_PROT_DISABLED = (0x0 << BCAST_STORM_PROT_Pos),
2743 };
2744
2745}
2746namespace PORT_IN_RATE_0 {
2747 enum {
2748 RATE_LIMIT_Pos = 0,
2749 RATE_LIMIT_Msk = (0x7F << RATE_LIMIT_Pos),
2750 RATE_LIMIT_640 = (101 << RATE_LIMIT_Pos),
2751 RATE_LIMIT_1280 = (102 << RATE_LIMIT_Pos),
2752 RATE_LIMIT_2560 = (103 << RATE_LIMIT_Pos),
2753 RATE_LIMIT_3840 = (104 << RATE_LIMIT_Pos),
2754 RATE_LIMIT_5120 = (105 << RATE_LIMIT_Pos),
2755 RATE_LIMIT_6400 = (106 << RATE_LIMIT_Pos),
2756 RATE_LIMIT_7680 = (107 << RATE_LIMIT_Pos),
2757 RATE_LIMIT_8960 = (108 << RATE_LIMIT_Pos),
2758 RATE_LIMIT_10240 = (109 << RATE_LIMIT_Pos),
2759 RATE_LIMIT_11520 = (110 << RATE_LIMIT_Pos),
2760 RATE_LIMIT_12800 = (111 << RATE_LIMIT_Pos),
2761 RATE_LIMIT_14080 = (112 << RATE_LIMIT_Pos),
2762 RATE_LIMIT_15360 = (113 << RATE_LIMIT_Pos),
2763 RATE_LIMIT_16640 = (114 << RATE_LIMIT_Pos),
2764 RATE_LIMIT_17920 = (115 << RATE_LIMIT_Pos),
2765 };
2766
2767 inline uint32_t RATE_LIMIT(uint32_t _x)
2768 { return (((_x) << RATE_LIMIT_Pos) & RATE_LIMIT_Msk); }
2769
2770}
2771namespace PORT_IN_RATE_1 {
2772 enum {
2773 RATE_LIMIT_Pos = 0,
2774 RATE_LIMIT_Msk = (0x7F << RATE_LIMIT_Pos),
2775 RATE_LIMIT_640 = (101 << RATE_LIMIT_Pos),
2776 RATE_LIMIT_1280 = (102 << RATE_LIMIT_Pos),
2777 RATE_LIMIT_2560 = (103 << RATE_LIMIT_Pos),
2778 RATE_LIMIT_3840 = (104 << RATE_LIMIT_Pos),
2779 RATE_LIMIT_5120 = (105 << RATE_LIMIT_Pos),
2780 RATE_LIMIT_6400 = (106 << RATE_LIMIT_Pos),
2781 RATE_LIMIT_7680 = (107 << RATE_LIMIT_Pos),
2782 RATE_LIMIT_8960 = (108 << RATE_LIMIT_Pos),
2783 RATE_LIMIT_10240 = (109 << RATE_LIMIT_Pos),
2784 RATE_LIMIT_11520 = (110 << RATE_LIMIT_Pos),
2785 RATE_LIMIT_12800 = (111 << RATE_LIMIT_Pos),
2786 RATE_LIMIT_14080 = (112 << RATE_LIMIT_Pos),
2787 RATE_LIMIT_15360 = (113 << RATE_LIMIT_Pos),
2788 RATE_LIMIT_16640 = (114 << RATE_LIMIT_Pos),
2789 RATE_LIMIT_17920 = (115 << RATE_LIMIT_Pos),
2790 };
2791
2792 inline uint32_t RATE_LIMIT(uint32_t _x)
2793 { return (((_x) << RATE_LIMIT_Pos) & RATE_LIMIT_Msk); }
2794
2795}
2796namespace PORT_IN_RATE_2 {
2797 enum {
2798 RATE_LIMIT_Pos = 0,
2799 RATE_LIMIT_Msk = (0x7F << RATE_LIMIT_Pos),
2800 RATE_LIMIT_640 = (101 << RATE_LIMIT_Pos),
2801 RATE_LIMIT_1280 = (102 << RATE_LIMIT_Pos),
2802 RATE_LIMIT_2560 = (103 << RATE_LIMIT_Pos),
2803 RATE_LIMIT_3840 = (104 << RATE_LIMIT_Pos),
2804 RATE_LIMIT_5120 = (105 << RATE_LIMIT_Pos),
2805 RATE_LIMIT_6400 = (106 << RATE_LIMIT_Pos),
2806 RATE_LIMIT_7680 = (107 << RATE_LIMIT_Pos),
2807 RATE_LIMIT_8960 = (108 << RATE_LIMIT_Pos),
2808 RATE_LIMIT_10240 = (109 << RATE_LIMIT_Pos),
2809 RATE_LIMIT_11520 = (110 << RATE_LIMIT_Pos),
2810 RATE_LIMIT_12800 = (111 << RATE_LIMIT_Pos),
2811 RATE_LIMIT_14080 = (112 << RATE_LIMIT_Pos),
2812 RATE_LIMIT_15360 = (113 << RATE_LIMIT_Pos),
2813 RATE_LIMIT_16640 = (114 << RATE_LIMIT_Pos),
2814 RATE_LIMIT_17920 = (115 << RATE_LIMIT_Pos),
2815 };
2816
2817 inline uint32_t RATE_LIMIT(uint32_t _x)
2818 { return (((_x) << RATE_LIMIT_Pos) & RATE_LIMIT_Msk); }
2819
2820}
2821namespace PORT_IN_RATE_3 {
2822 enum {
2823 RATE_LIMIT_Pos = 0,
2824 RATE_LIMIT_Msk = (0x7F << RATE_LIMIT_Pos),
2825 RATE_LIMIT_640 = (101 << RATE_LIMIT_Pos),
2826 RATE_LIMIT_1280 = (102 << RATE_LIMIT_Pos),
2827 RATE_LIMIT_2560 = (103 << RATE_LIMIT_Pos),
2828 RATE_LIMIT_3840 = (104 << RATE_LIMIT_Pos),
2829 RATE_LIMIT_5120 = (105 << RATE_LIMIT_Pos),
2830 RATE_LIMIT_6400 = (106 << RATE_LIMIT_Pos),
2831 RATE_LIMIT_7680 = (107 << RATE_LIMIT_Pos),
2832 RATE_LIMIT_8960 = (108 << RATE_LIMIT_Pos),
2833 RATE_LIMIT_10240 = (109 << RATE_LIMIT_Pos),
2834 RATE_LIMIT_11520 = (110 << RATE_LIMIT_Pos),
2835 RATE_LIMIT_12800 = (111 << RATE_LIMIT_Pos),
2836 RATE_LIMIT_14080 = (112 << RATE_LIMIT_Pos),
2837 RATE_LIMIT_15360 = (113 << RATE_LIMIT_Pos),
2838 RATE_LIMIT_16640 = (114 << RATE_LIMIT_Pos),
2839 RATE_LIMIT_17920 = (115 << RATE_LIMIT_Pos),
2840 };
2841
2842 inline uint32_t RATE_LIMIT(uint32_t _x)
2843 { return (((_x) << RATE_LIMIT_Pos) & RATE_LIMIT_Msk); }
2844
2845}
2846namespace PORT_IN_RATE_4 {
2847 enum {
2848 RATE_LIMIT_Pos = 0,
2849 RATE_LIMIT_Msk = (0x7F << RATE_LIMIT_Pos),
2850 RATE_LIMIT_640 = (101 << RATE_LIMIT_Pos),
2851 RATE_LIMIT_1280 = (102 << RATE_LIMIT_Pos),
2852 RATE_LIMIT_2560 = (103 << RATE_LIMIT_Pos),
2853 RATE_LIMIT_3840 = (104 << RATE_LIMIT_Pos),
2854 RATE_LIMIT_5120 = (105 << RATE_LIMIT_Pos),
2855 RATE_LIMIT_6400 = (106 << RATE_LIMIT_Pos),
2856 RATE_LIMIT_7680 = (107 << RATE_LIMIT_Pos),
2857 RATE_LIMIT_8960 = (108 << RATE_LIMIT_Pos),
2858 RATE_LIMIT_10240 = (109 << RATE_LIMIT_Pos),
2859 RATE_LIMIT_11520 = (110 << RATE_LIMIT_Pos),
2860 RATE_LIMIT_12800 = (111 << RATE_LIMIT_Pos),
2861 RATE_LIMIT_14080 = (112 << RATE_LIMIT_Pos),
2862 RATE_LIMIT_15360 = (113 << RATE_LIMIT_Pos),
2863 RATE_LIMIT_16640 = (114 << RATE_LIMIT_Pos),
2864 RATE_LIMIT_17920 = (115 << RATE_LIMIT_Pos),
2865 };
2866
2867 inline uint32_t RATE_LIMIT(uint32_t _x)
2868 { return (((_x) << RATE_LIMIT_Pos) & RATE_LIMIT_Msk); }
2869
2870}
2871namespace PORT_IN_RATE_5 {
2872 enum {
2873 RATE_LIMIT_Pos = 0,
2874 RATE_LIMIT_Msk = (0x7F << RATE_LIMIT_Pos),
2875 RATE_LIMIT_640 = (101 << RATE_LIMIT_Pos),
2876 RATE_LIMIT_1280 = (102 << RATE_LIMIT_Pos),
2877 RATE_LIMIT_2560 = (103 << RATE_LIMIT_Pos),
2878 RATE_LIMIT_3840 = (104 << RATE_LIMIT_Pos),
2879 RATE_LIMIT_5120 = (105 << RATE_LIMIT_Pos),
2880 RATE_LIMIT_6400 = (106 << RATE_LIMIT_Pos),
2881 RATE_LIMIT_7680 = (107 << RATE_LIMIT_Pos),
2882 RATE_LIMIT_8960 = (108 << RATE_LIMIT_Pos),
2883 RATE_LIMIT_10240 = (109 << RATE_LIMIT_Pos),
2884 RATE_LIMIT_11520 = (110 << RATE_LIMIT_Pos),
2885 RATE_LIMIT_12800 = (111 << RATE_LIMIT_Pos),
2886 RATE_LIMIT_14080 = (112 << RATE_LIMIT_Pos),
2887 RATE_LIMIT_15360 = (113 << RATE_LIMIT_Pos),
2888 RATE_LIMIT_16640 = (114 << RATE_LIMIT_Pos),
2889 RATE_LIMIT_17920 = (115 << RATE_LIMIT_Pos),
2890 };
2891
2892 inline uint32_t RATE_LIMIT(uint32_t _x)
2893 { return (((_x) << RATE_LIMIT_Pos) & RATE_LIMIT_Msk); }
2894
2895}
2896namespace PORT_IN_RATE_6 {
2897 enum {
2898 RATE_LIMIT_Pos = 0,
2899 RATE_LIMIT_Msk = (0x7F << RATE_LIMIT_Pos),
2900 RATE_LIMIT_640 = (101 << RATE_LIMIT_Pos),
2901 RATE_LIMIT_1280 = (102 << RATE_LIMIT_Pos),
2902 RATE_LIMIT_2560 = (103 << RATE_LIMIT_Pos),
2903 RATE_LIMIT_3840 = (104 << RATE_LIMIT_Pos),
2904 RATE_LIMIT_5120 = (105 << RATE_LIMIT_Pos),
2905 RATE_LIMIT_6400 = (106 << RATE_LIMIT_Pos),
2906 RATE_LIMIT_7680 = (107 << RATE_LIMIT_Pos),
2907 RATE_LIMIT_8960 = (108 << RATE_LIMIT_Pos),
2908 RATE_LIMIT_10240 = (109 << RATE_LIMIT_Pos),
2909 RATE_LIMIT_11520 = (110 << RATE_LIMIT_Pos),
2910 RATE_LIMIT_12800 = (111 << RATE_LIMIT_Pos),
2911 RATE_LIMIT_14080 = (112 << RATE_LIMIT_Pos),
2912 RATE_LIMIT_15360 = (113 << RATE_LIMIT_Pos),
2913 RATE_LIMIT_16640 = (114 << RATE_LIMIT_Pos),
2914 RATE_LIMIT_17920 = (115 << RATE_LIMIT_Pos),
2915 };
2916
2917 inline uint32_t RATE_LIMIT(uint32_t _x)
2918 { return (((_x) << RATE_LIMIT_Pos) & RATE_LIMIT_Msk); }
2919
2920}
2921namespace PORT_IN_RATE_7 {
2922 enum {
2923 RATE_LIMIT_Pos = 0,
2924 RATE_LIMIT_Msk = (0x7F << RATE_LIMIT_Pos),
2925 RATE_LIMIT_640 = (101 << RATE_LIMIT_Pos),
2926 RATE_LIMIT_1280 = (102 << RATE_LIMIT_Pos),
2927 RATE_LIMIT_2560 = (103 << RATE_LIMIT_Pos),
2928 RATE_LIMIT_3840 = (104 << RATE_LIMIT_Pos),
2929 RATE_LIMIT_5120 = (105 << RATE_LIMIT_Pos),
2930 RATE_LIMIT_6400 = (106 << RATE_LIMIT_Pos),
2931 RATE_LIMIT_7680 = (107 << RATE_LIMIT_Pos),
2932 RATE_LIMIT_8960 = (108 << RATE_LIMIT_Pos),
2933 RATE_LIMIT_10240 = (109 << RATE_LIMIT_Pos),
2934 RATE_LIMIT_11520 = (110 << RATE_LIMIT_Pos),
2935 RATE_LIMIT_12800 = (111 << RATE_LIMIT_Pos),
2936 RATE_LIMIT_14080 = (112 << RATE_LIMIT_Pos),
2937 RATE_LIMIT_15360 = (113 << RATE_LIMIT_Pos),
2938 RATE_LIMIT_16640 = (114 << RATE_LIMIT_Pos),
2939 RATE_LIMIT_17920 = (115 << RATE_LIMIT_Pos),
2940 };
2941
2942 inline uint32_t RATE_LIMIT(uint32_t _x)
2943 { return (((_x) << RATE_LIMIT_Pos) & RATE_LIMIT_Msk); }
2944
2945}
2946namespace PORT_OUT_RATE_0 {
2947 enum {
2948 RATE_LIMIT_Pos = 0,
2949 RATE_LIMIT_Msk = (0x7F << RATE_LIMIT_Pos),
2950 RATE_LIMIT_640 = (101 << RATE_LIMIT_Pos),
2951 RATE_LIMIT_1280 = (102 << RATE_LIMIT_Pos),
2952 RATE_LIMIT_2560 = (103 << RATE_LIMIT_Pos),
2953 RATE_LIMIT_3840 = (104 << RATE_LIMIT_Pos),
2954 RATE_LIMIT_5120 = (105 << RATE_LIMIT_Pos),
2955 RATE_LIMIT_6400 = (106 << RATE_LIMIT_Pos),
2956 RATE_LIMIT_7680 = (107 << RATE_LIMIT_Pos),
2957 RATE_LIMIT_8960 = (108 << RATE_LIMIT_Pos),
2958 RATE_LIMIT_10240 = (109 << RATE_LIMIT_Pos),
2959 RATE_LIMIT_11520 = (110 << RATE_LIMIT_Pos),
2960 RATE_LIMIT_12800 = (111 << RATE_LIMIT_Pos),
2961 RATE_LIMIT_14080 = (112 << RATE_LIMIT_Pos),
2962 RATE_LIMIT_15360 = (113 << RATE_LIMIT_Pos),
2963 RATE_LIMIT_16640 = (114 << RATE_LIMIT_Pos),
2964 RATE_LIMIT_17920 = (115 << RATE_LIMIT_Pos),
2965 };
2966
2967 inline uint32_t RATE_LIMIT(uint32_t _x)
2968 { return (((_x) << RATE_LIMIT_Pos) & RATE_LIMIT_Msk); }
2969
2970}
2971namespace PORT_OUT_RATE_1 {
2972 enum {
2973 RATE_LIMIT_Pos = 0,
2974 RATE_LIMIT_Msk = (0x7F << RATE_LIMIT_Pos),
2975 RATE_LIMIT_640 = (101 << RATE_LIMIT_Pos),
2976 RATE_LIMIT_1280 = (102 << RATE_LIMIT_Pos),
2977 RATE_LIMIT_2560 = (103 << RATE_LIMIT_Pos),
2978 RATE_LIMIT_3840 = (104 << RATE_LIMIT_Pos),
2979 RATE_LIMIT_5120 = (105 << RATE_LIMIT_Pos),
2980 RATE_LIMIT_6400 = (106 << RATE_LIMIT_Pos),
2981 RATE_LIMIT_7680 = (107 << RATE_LIMIT_Pos),
2982 RATE_LIMIT_8960 = (108 << RATE_LIMIT_Pos),
2983 RATE_LIMIT_10240 = (109 << RATE_LIMIT_Pos),
2984 RATE_LIMIT_11520 = (110 << RATE_LIMIT_Pos),
2985 RATE_LIMIT_12800 = (111 << RATE_LIMIT_Pos),
2986 RATE_LIMIT_14080 = (112 << RATE_LIMIT_Pos),
2987 RATE_LIMIT_15360 = (113 << RATE_LIMIT_Pos),
2988 RATE_LIMIT_16640 = (114 << RATE_LIMIT_Pos),
2989 RATE_LIMIT_17920 = (115 << RATE_LIMIT_Pos),
2990 };
2991
2992 inline uint32_t RATE_LIMIT(uint32_t _x)
2993 { return (((_x) << RATE_LIMIT_Pos) & RATE_LIMIT_Msk); }
2994
2995}
2996namespace PORT_OUT_RATE_2 {
2997 enum {
2998 RATE_LIMIT_Pos = 0,
2999 RATE_LIMIT_Msk = (0x7F << RATE_LIMIT_Pos),
3000 RATE_LIMIT_640 = (101 << RATE_LIMIT_Pos),
3001 RATE_LIMIT_1280 = (102 << RATE_LIMIT_Pos),
3002 RATE_LIMIT_2560 = (103 << RATE_LIMIT_Pos),
3003 RATE_LIMIT_3840 = (104 << RATE_LIMIT_Pos),
3004 RATE_LIMIT_5120 = (105 << RATE_LIMIT_Pos),
3005 RATE_LIMIT_6400 = (106 << RATE_LIMIT_Pos),
3006 RATE_LIMIT_7680 = (107 << RATE_LIMIT_Pos),
3007 RATE_LIMIT_8960 = (108 << RATE_LIMIT_Pos),
3008 RATE_LIMIT_10240 = (109 << RATE_LIMIT_Pos),
3009 RATE_LIMIT_11520 = (110 << RATE_LIMIT_Pos),
3010 RATE_LIMIT_12800 = (111 << RATE_LIMIT_Pos),
3011 RATE_LIMIT_14080 = (112 << RATE_LIMIT_Pos),
3012 RATE_LIMIT_15360 = (113 << RATE_LIMIT_Pos),
3013 RATE_LIMIT_16640 = (114 << RATE_LIMIT_Pos),
3014 RATE_LIMIT_17920 = (115 << RATE_LIMIT_Pos),
3015 };
3016
3017 inline uint32_t RATE_LIMIT(uint32_t _x)
3018 { return (((_x) << RATE_LIMIT_Pos) & RATE_LIMIT_Msk); }
3019
3020}
3021namespace PORT_OUT_RATE_3 {
3022 enum {
3023 RATE_LIMIT_Pos = 0,
3024 RATE_LIMIT_Msk = (0x7F << RATE_LIMIT_Pos),
3025 RATE_LIMIT_640 = (101 << RATE_LIMIT_Pos),
3026 RATE_LIMIT_1280 = (102 << RATE_LIMIT_Pos),
3027 RATE_LIMIT_2560 = (103 << RATE_LIMIT_Pos),
3028 RATE_LIMIT_3840 = (104 << RATE_LIMIT_Pos),
3029 RATE_LIMIT_5120 = (105 << RATE_LIMIT_Pos),
3030 RATE_LIMIT_6400 = (106 << RATE_LIMIT_Pos),
3031 RATE_LIMIT_7680 = (107 << RATE_LIMIT_Pos),
3032 RATE_LIMIT_8960 = (108 << RATE_LIMIT_Pos),
3033 RATE_LIMIT_10240 = (109 << RATE_LIMIT_Pos),
3034 RATE_LIMIT_11520 = (110 << RATE_LIMIT_Pos),
3035 RATE_LIMIT_12800 = (111 << RATE_LIMIT_Pos),
3036 RATE_LIMIT_14080 = (112 << RATE_LIMIT_Pos),
3037 RATE_LIMIT_15360 = (113 << RATE_LIMIT_Pos),
3038 RATE_LIMIT_16640 = (114 << RATE_LIMIT_Pos),
3039 RATE_LIMIT_17920 = (115 << RATE_LIMIT_Pos),
3040 };
3041
3042 inline uint32_t RATE_LIMIT(uint32_t _x)
3043 { return (((_x) << RATE_LIMIT_Pos) & RATE_LIMIT_Msk); }
3044
3045}
3046
3047namespace PORT_MIB_CTRL_STAT {
3048 enum {
3049 MIB_COUNTER_HI_Pos = 0,
3050 MIB_COUNTER_HI_Msk = (0xF << MIB_COUNTER_HI_Pos),
3051 MIB_INDEX_Pos = 16,
3052 MIB_INDEX_Msk = (0xFF << MIB_INDEX_Pos),
3053 FLUSH_AND_FREEZE_Pos = 24,
3054 FLUSH_AND_FREEZE_Msk = (0x1 << FLUSH_AND_FREEZE_Pos),
3055 FLUSH_AND_FREEZE_DISABLED = (0x0 << FLUSH_AND_FREEZE_Pos),
3056 FLUSH_AND_FREEZE_ENABLED = (0x1 << FLUSH_AND_FREEZE_Pos),
3057 MIB_COUNTER_RD_ENABLE_Pos = 25,
3058 MIB_COUNTER_RD_ENABLE_Msk = (0x1 << MIB_COUNTER_RD_ENABLE_Pos),
3059 MIB_COUNTER_RD_ENABLE_ENABLED = (0x1 << MIB_COUNTER_RD_ENABLE_Pos),
3060 MIB_COUNTER_VALID_Pos = 30,
3061 MIB_COUNTER_VALID_Msk = (0x1 << MIB_COUNTER_VALID_Pos),
3062 MIB_COUNTER_VALID_VALID = (0x0 << MIB_COUNTER_VALID_Pos),
3063 MIB_COUNTER_VALID_INVALID = (0x1 << MIB_COUNTER_VALID_Pos),
3064 COUNTER_OVERFLOW_Pos = 31,
3065 COUNTER_OVERFLOW_Msk = (0x1 << COUNTER_OVERFLOW_Pos),
3066 };
3067
3068 inline uint32_t MIB_COUNTER_HI(uint32_t _x)
3069 { return (((_x) << MIB_COUNTER_HI_Pos) & MIB_COUNTER_HI_Msk); }
3070 inline uint32_t MIB_INDEX(uint32_t _x)
3071 { return (((_x) << MIB_INDEX_Pos) & MIB_INDEX_Msk); }
3072
3073}
3074
3075namespace PORT_ACL_ACCESS {
3076 enum {
3077 MAC_ADDR_4_Pos = 0,
3078 MAC_ADDR_4_Msk = (0xFF << MAC_ADDR_4_Pos),
3079 MAC_ADDR_5_Pos = 8,
3080 MAC_ADDR_5_Msk = (0xFF << MAC_ADDR_5_Pos),
3081 COMP_MATCH_Pos = 16,
3082 COMP_MATCH_Msk = (0x1 << COMP_MATCH_Pos),
3083 COMP_MATCH_EQUAL = (0x1 << COMP_MATCH_Pos),
3084 COMP_MATCH_NOT_EQUAL = (0x0 << COMP_MATCH_Pos),
3085 SRC_DEST_Pos = 17,
3086 SRC_DEST_Msk = (0x1 << SRC_DEST_Pos),
3087 SRC_DEST_SRC = (0x1 << SRC_DEST_Pos),
3088 SRC_DEST_DEST = (0x0 << COMP_MATCH_Pos),
3089 ENABLE_Pos = 18,
3090 ENABLE_Msk = (0x3 << ENABLE_Pos),
3091 MODE_Pos = 18,
3092 MODE_Msk = (0x3 << MODE_Pos),
3093 MODE_NO_ACTION = (0x0 << MODE_Pos),
3094 MODE_L2_MAC_HDR = (0x1 << MODE_Pos),
3095 MODE_L3_IP_ADDR = (0x2 << MODE_Pos),
3096 MODE_L4_TPORT_IPROT = (0x3 << MODE_Pos),
3097 FIRST_RULE_NUM_Pos = 24,
3098 FIRST_RULE_NUM_Msk = (0xF << FIRST_RULE_NUM_Pos),
3099 };
3100
3101 inline uint32_t MAC_ADDR_4(uint32_t _x)
3102 { return (((_x) << MAC_ADDR_4_Pos) & MAC_ADDR_4_Msk); }
3103 inline uint32_t MAC_ADDR_5(uint32_t _x)
3104 { return (((_x) << MAC_ADDR_5_Pos) & MAC_ADDR_5_Msk); }
3105 inline uint32_t ENABLE(uint32_t _x)
3106 { return (((_x) << ENABLE_Pos) & ENABLE_Msk); }
3107 inline uint32_t FIRST_RULE_NUM(uint32_t _x)
3108 { return (((_x) << FIRST_RULE_NUM_Pos) & FIRST_RULE_NUM_Msk); }
3109
3110}
3111namespace PORT_ACL_ACCESS2 {
3112 enum {
3113 MAC_ADDR_0_Pos = 0,
3114 MAC_ADDR_0_Msk = (0xFF << MAC_ADDR_0_Pos),
3115 MAC_ADDR_1_Pos = 8,
3116 MAC_ADDR_1_Msk = (0xFF << MAC_ADDR_1_Pos),
3117 MAC_ADDR_2_Pos = 16,
3118 MAC_ADDR_2_Msk = (0xFF << MAC_ADDR_2_Pos),
3119 MAC_ADDR_3_Pos = 24,
3120 MAC_ADDR_3_Msk = (0xFF << MAC_ADDR_3_Pos),
3121 };
3122
3123 inline uint32_t MAC_ADDR_0(uint32_t _x)
3124 { return (((_x) << MAC_ADDR_0_Pos) & MAC_ADDR_0_Msk); }
3125 inline uint32_t MAC_ADDR_1(uint32_t _x)
3126 { return (((_x) << MAC_ADDR_1_Pos) & MAC_ADDR_1_Msk); }
3127 inline uint32_t MAC_ADDR_2(uint32_t _x)
3128 { return (((_x) << MAC_ADDR_2_Pos) & MAC_ADDR_2_Msk); }
3129 inline uint32_t MAC_ADDR_3(uint32_t _x)
3130 { return (((_x) << MAC_ADDR_3_Pos) & MAC_ADDR_3_Msk); }
3131
3132}
3133namespace PORT_ACL_ACCESS3 {
3134 enum {
3135 MAP_MODE_Pos = 5,
3136 MAP_MODE_Msk = (0x3 << MAP_MODE_Pos),
3137 REMARK_PRIO_Pos = 7,
3138 REMARK_PRIO_Msk = (0x7 << REMARK_PRIO_Pos),
3139 REMARK_PRIO_ENABLE_Pos = 10,
3140 REMARK_PRIO_ENABLE_Msk = (0x1 << REMARK_PRIO_ENABLE_Pos),
3141 REMARK_PRIO_ENABLE_ENABLED = (0x1 << REMARK_PRIO_ENABLE_Pos),
3142 REMARK_PRIO_ENABLE_DISABLED = (0x0 << REMARK_PRIO_ENABLE_Pos),
3143 PRIORITY_Pos = 11,
3144 PRIORITY_Msk = (0x7 << PRIORITY_Pos),
3145 PRIO_MODE_Pos = 14,
3146 PRIO_MODE_Msk = (0x3 << PRIO_MODE_Pos),
3147 ETHER_TYPE_Pos = 16,
3148 ETHER_TYPE_Msk = (0xFFFF << ETHER_TYPE_Pos),
3149 };
3150
3151 inline uint32_t MAP_MODE(uint32_t _x)
3152 { return (((_x) << MAP_MODE_Pos) & MAP_MODE_Msk); }
3153 inline uint32_t REMARK_PRIO(uint32_t _x)
3154 { return (((_x) << REMARK_PRIO_Pos) & REMARK_PRIO_Msk); }
3155 inline uint32_t PRIORITY(uint32_t _x)
3156 { return (((_x) << PRIORITY_Pos) & PRIORITY_Msk); }
3157 inline uint32_t PRIO_MODE(uint32_t _x)
3158 { return (((_x) << PRIO_MODE_Pos) & PRIO_MODE_Msk); }
3159 inline uint32_t ETHER_TYPE(uint32_t _x)
3160 { return (((_x) << ETHER_TYPE_Pos) & ETHER_TYPE_Msk); }
3161
3162}
3163namespace PORT_ACL_ACCESS4 {
3164 enum {
3165 RULESET_Pos = 0,
3166 RULESET_Msk = (0xFFFF << RULESET_Pos),
3167 FORWARD_MAP_Pos = 16,
3168 FORWARD_MAP_Msk = (0xFF << FORWARD_MAP_Pos),
3169 };
3170
3171 inline uint32_t RULESET(uint32_t _x)
3172 { return (((_x) << RULESET_Pos) & RULESET_Msk); }
3173 inline uint32_t FORWARD_MAP(uint32_t _x)
3174 { return (((_x) << FORWARD_MAP_Pos) & FORWARD_MAP_Msk); }
3175
3176}
3177namespace PORT_ACL_EN_CTRL {
3178 enum {
3179 ACL_IDX_Pos = 8,
3180 ACL_IDX_Msk = (0xF << ACL_IDX_Pos),
3181 RW_Pos = 12,
3182 RW_Msk = (0x1 << RW_Pos),
3183 RW_WRITE = (0x1 << RW_Pos),
3184 RW_READ = (0x0 << RW_Pos),
3185 RD_STATUS_Pos = 13,
3186 RD_STATUS_Msk = (0x1 << RD_STATUS_Pos),
3187 RD_STATUS_COMPLETE = (0x1 << RD_STATUS_Pos),
3188 RD_STATUS_IN_PROGRESS = (0x0 << RD_STATUS_Pos),
3189 WR_STATUS_Pos = 14,
3190 WR_STATUS_Msk = (0x1 << WR_STATUS_Pos),
3191 WR_STATUS_COMPLETE = (0x1 << WR_STATUS_Pos),
3192 WR_STATUS_IN_PROGRESS = (0x0 << WR_STATUS_Pos),
3193 BYTE_EN_MAP_Pos = 16,
3194 BYTE_EN_MAP_Msk = (0xFFFF << BYTE_EN_MAP_Pos),
3195 };
3196
3197 inline uint32_t ACL_IDX(uint32_t _x)
3198 { return (((_x) << ACL_IDX_Pos) & ACL_IDX_Msk); }
3199 inline uint32_t BYTE_EN_MAP(uint32_t _x)
3200 { return (((_x) << BYTE_EN_MAP_Pos) & BYTE_EN_MAP_Msk); }
3201
3202}
3203
3204namespace PORT_MIRROR_CTRL {
3205 enum {
3206 SNIFFER_PORT_Pos = 1,
3207 SNIFFER_PORT_Msk = (0x1 << SNIFFER_PORT_Pos),
3208 SNIFFER_PORT_THIS_PORT = (0x1 << SNIFFER_PORT_Pos),
3209 SNIFFER_PORT_NOT_THIS_PORT = (0x0 << SNIFFER_PORT_Pos),
3210 TX_SNIFF_Pos = 5,
3211 TX_SNIFF_Msk = (0x1 << TX_SNIFF_Pos),
3212 TX_SNIFF_ENABLED = (0x1 << TX_SNIFF_Pos),
3213 TX_SNIFF_DISABLED = (0x0 << TX_SNIFF_Pos),
3214 RX_SNIFF_Pos = 6,
3215 RX_SNIFF_Msk = (0x1 << RX_SNIFF_Pos),
3216 RX_SNIFF_ENABLED = (0x1 << RX_SNIFF_Pos),
3217 RX_SNIFF_DISABLED = (0x0 << RX_SNIFF_Pos),
3218 };
3219
3220}
3221namespace PORT_PRIO_CTRL {
3222 enum {
3223 ACL_PRIO_CLASS_Pos = 0,
3224 ACL_PRIO_CLASS_Msk = (0x1 << ACL_PRIO_CLASS_Pos),
3225 ACL_PRIO_CLASS_ENABLED = (0x1 << ACL_PRIO_CLASS_Pos),
3226 ACL_PRIO_CLASS_DISABLED = (0x0 << ACL_PRIO_CLASS_Pos),
3227 DIFFSERV_PRIO_CLASS_Pos = 1,
3228 DIFFSERV_PRIO_CLASS_Msk = (0x1 << DIFFSERV_PRIO_CLASS_Pos),
3229 DIFFSERV_PRIO_CLASS_ENABLED = (0x1 << DIFFSERV_PRIO_CLASS_Pos),
3230 DIFFSERV_PRIO_CLASS_DISABLED = (0x0 << DIFFSERV_PRIO_CLASS_Pos),
3231 _802_1P_PRIO_CLASS_Pos = 2,
3232 _802_1P_PRIO_CLASS_Msk = (0x1 << _802_1P_PRIO_CLASS_Pos),
3233 _802_1P_PRIO_CLASS_ENABLED = (0x1 << _802_1P_PRIO_CLASS_Pos),
3234 _802_1P_PRIO_CLASS_DISABLED = (0x0 << _802_1P_PRIO_CLASS_Pos),
3235 VLAN_PRIO_CLASS_Pos = 2,
3236 VLAN_PRIO_CLASS_Msk = (0x1 << VLAN_PRIO_CLASS_Pos),
3237 VLAN_PRIO_CLASS_ENABLED = (0x1 << VLAN_PRIO_CLASS_Pos),
3238 VLAN_PRIO_CLASS_DISABLED = (0x0 << VLAN_PRIO_CLASS_Pos),
3239 MAC_ADDR_PRIO_CLASS_Pos = 4,
3240 MAC_ADDR_PRIO_CLASS_Msk = (0x1 << MAC_ADDR_PRIO_CLASS_Pos),
3241 MAC_ADDR_PRIO_CLASS_ENABLED = (0x1 << MAC_ADDR_PRIO_CLASS_Pos),
3242 MAC_ADDR_PRIO_CLASS_DISABLED = (0x0 << MAC_ADDR_PRIO_CLASS_Pos),
3243 BOOLEAN_OR_PRIO_Pos = 6,
3244 BOOLEAN_OR_PRIO_Msk = (0x1 << BOOLEAN_OR_PRIO_Pos),
3245 BOOLEAN_OR_PRIO_ENABLED = (0x1 << BOOLEAN_OR_PRIO_Pos),
3246 BOOLEAN_OR_PRIO_DISABLED = (0x0 << BOOLEAN_OR_PRIO_Pos),
3247 HIGHEST_PRIO_Pos = 6,
3248 HIGHEST_PRIO_Msk = (0x1 << HIGHEST_PRIO_Pos),
3249 HIGHEST_PRIO_ENABLED = (0x1 << HIGHEST_PRIO_Pos),
3250 HIGHEST_PRIO_DISABLED = (0x0 << HIGHEST_PRIO_Pos),
3251 };
3252
3253}
3254namespace PORT_IN_MAC_CTRL {
3255 enum {
3256 PORT_DEF_PRIO_CLASS_Pos = 0,
3257 PORT_DEF_PRIO_CLASS_Msk = (0x7 << PORT_DEF_PRIO_CLASS_Pos),
3258 DISCARD_TAGGED_Pos = 3,
3259 DISCARD_TAGGED_Msk = (0x1 << DISCARD_TAGGED_Pos),
3260 DISCARD_TAGGED_ENABLED = (0x1 << DISCARD_TAGGED_Pos),
3261 DISCARD_TAGGED_DISABLED = (0x0 << DISCARD_TAGGED_Pos),
3262 DISCARD_UNTAGGED_Pos = 4,
3263 DISCARD_UNTAGGED_Msk = (0x1 << DISCARD_UNTAGGED_Pos),
3264 DISCARD_UNTAGGED_ENABLED = (0x1 << DISCARD_UNTAGGED_Pos),
3265 DISCARD_UNTAGGED_DISABLED = (0x0 << DISCARD_UNTAGGED_Pos),
3266 USER_PRIO_CEIL_Pos = 7,
3267 USER_PRIO_CEIL_Msk = (0x1 << USER_PRIO_CEIL_Pos),
3268 USER_PRIO_CEIL_ENABLED = (0x1 << USER_PRIO_CEIL_Pos),
3269 USER_PRIO_CEIL_DISABLED = (0x0 << USER_PRIO_CEIL_Pos),
3270 };
3271
3272 inline uint32_t PORT_DEF_PRIO_CLASS(uint32_t _x)
3273 { return (((_x) << PORT_DEF_PRIO_CLASS_Pos) & PORT_DEF_PRIO_CLASS_Msk); }
3274
3275}
3276namespace PORT_AUTH_CTRL {
3277 enum {
3278 AUTH_MODE_Pos = 0,
3279 AUTH_MODE_Msk = (0x3 << AUTH_MODE_Msk),
3280 ACL_Pos = 3,
3281 ACL_Msk = (0x1 << ACL_Pos),
3282 ACL_ENABLED = (0x1 << ACL_Pos),
3283 ACL_DISABLED = (0x0 << ACL_Pos),
3284 };
3285
3286 inline uint32_t AUTH_MODE(uint32_t _x)
3287 { return (((_x) << AUTH_MODE_Pos) & AUTH_MODE_Msk); }
3288
3289}
3290namespace PORT_POINTER {
3291 enum {
3292 QUEUE_Pos = 0,
3293 QUEUE_Msk = (0x3 << QUEUE_Pos),
3294 PORT_IDX_Pos = 16,
3295 PORT_IDX_Msk = (0x7 << PORT_IDX_Pos),
3296 };
3297
3298 inline uint32_t QUEUE(uint32_t _x)
3299 { return (((_x) << QUEUE_Pos) & QUEUE_Msk); }
3300 inline uint32_t PORT_IDX(uint32_t _x)
3301 { return (((_x) << PORT_IDX_Pos) & PORT_IDX_Msk); }
3302
3303}
3304namespace PORT_PRIO_QUEUE_MAP {
3305 enum {
3306 };
3307
3308 inline uint32_t PRIO_Pos(uint32_t _p)
3309 { return ((_p & 0x7)<< 2); }
3310 inline uint32_t PRIO_Msk(uint32_t _p)
3311 { return ((0x3) << ((_p & 0x7)<< 2)); }
3312 inline uint32_t PRIO(uint32_t _p, uint32_t _x)
3313 { return ((_x << PRIO_Pos(_p)) & PRIO_Msk(_p))); }
3314
3315}
3316namespace PORT_POLICE_CTRL {
3317 enum {
3318 POLICE_ENABLE_Pos = 0,
3319 POLICE_ENABLE_Msk = (0x1 << POLICE_ENABLE_Pos),
3320 POLICE_ENABLE_ENABLED = (0x1 << POLICE_ENABLE_Pos),
3321 POLICE_ENABLE_DISABLED = (0x0 << POLICE_ENABLE_Pos),
3322 POLICE_MODE_Pos = 1,
3323 POLICE_MODE_Msk = (0x1 << POLICE_MODE_Pos),
3324 POLICE_MODE_COLORBLIND = (0x1 << POLICE_MODE_Pos),
3325 POLICE_MODE_RACIST = (0x0 << POLICE_MODE_Pos),
3326 DROP_SRP_Pos = 2,
3327 DROP_SRP_Msk = (0x1 << DROP_SRP_Pos),
3328 DROP_SRP_ENABLED = (0x1 << DROP_SRP_Pos),
3329 DROP_SRP_DISABLED = (0x0 << DROP_SRP_Pos),
3330 COLOR_REMAP_Pos = 3,
3331 COLOR_REMAP_Msk = (0x1 << COLOR_REMAP_Pos),
3332 COLOR_REMAP_ENABLED = (0x1 << COLOR_REMAP_Pos),
3333 COLOR_REMAP_DISABLED = (0x0 << COLOR_REMAP_Pos),
3334 COLOR_MARK_Pos = 4,
3335 COLOR_MARK_Msk = (0x1 << COLOR_MARK_Pos),
3336 COLOR_MARK_ENABLED = (0x1 << COLOR_MARK_Pos),
3337 COLOR_MARK_DISABLED = (0x0 << COLOR_MARK_Pos),
3338 NONDSCP_COLOR_Pos = 5,
3339 NONDSCP_COLOR_Msk = (0x3 << NONDSCP_COLOR_Pos),
3340 PORT_BASED_POLICING_Pos = 7,
3341 PORT_BASED_POLICING_Msk = (0x1 << PORT_BASED_POLICING_Pos),
3342 PORT_BASED_POLICING_ENABLED = (0x1 << PORT_BASED_POLICING_Pos),
3343 PORT_BASED_POLICING_DISABLED = (0x0 << PORT_BASED_POLICING_Pos),
3344 PKT_TYPE_Pos = 8,
3345 PKT_TYPE_Msk = (0x3 << PKT_TYPE_Pos),
3346 DROP_ALL_Pos = 10,
3347 DROP_ALL_Msk = (0x1 << DROP_ALL_Pos),
3348 DROP_ALL_ENABLED = (0x1 << DROP_ALL_Pos),
3349 DROP_ALL_DISABLED = (0x0 << DROP_ALL_Pos),
3350 PMON_DROPPED_COLOR_Pos = 11,
3351 PMON_DROPPED_COLOR_Msk = (0x1 << PMON_DROPPED_COLOR_Pos),
3352 PMON_DROPPED_COLOR_ENABLED = (0x1 << PMON_DROPPED_COLOR_Pos),
3353 PMON_DROPPED_COLOR_DISABLED = (0x0 << PMON_DROPPED_COLOR_Pos),
3354 };
3355
3356 inline uint32_t NONDSCP_COLOR(uint32_t _x)
3357 { return (((_x) << NONDSCP_COLOR_Pos) & NONDSCP_COLOR_Msk); }
3358 inline uint32_t PKT_TYPE(uint32_t _x)
3359 { return (((_x) << PKT_TYPE_Pos) & PKT_TYPE_Msk); }
3360
3361}
3362
3363namespace PORT_TX_QUEUE_IDX {
3364 enum {
3365 QUEUE_IDX_Pos = 0,
3366 QUEUE_IDX_Msk = (0x3 << QUEUE_IDX_Pos),
3367 };
3368
3369 inline uint32_t QUEUE_IDX(uint32_t _x)
3370 { return (((_x) << QUEUE_IDX_Pos) & QUEUE_IDX_Msk); }
3371
3372}
3373namespace PORT_TX_QUEUE_PVID {
3374 enum {
3375 PORT_VID_REPLACE_Pos = 0,
3376 PORT_VID_REPLACE_Msk = (0x1 << PORT_VID_REPLACE_Pos),
3377 PORT_VID_REPLACE_ENABLED = (0x1 << PORT_VID_REPLACE_Pos),
3378 PORT_VID_REPLACE_DISABLED = (0x0 << PORT_VID_REPLACE_Pos),
3379 };
3380
3381}
3382namespace PORT_TX_QUEUE_CTRL {
3383 enum {
3384 QUEUE_WEIGHT_4_WRR_Pos = 0,
3385 QUEUE_WEIGHT_4_WRR_Msk = (0x7F << QUEUE_WEIGHT_4_WRR_Pos),
3386 SCHED_MODE_Pos = 14,
3387 SCHED_MODE_Msk = (0x3 << SCHED_MODE_Pos),
3388 };
3389
3390 inline uint32_t QUEUE_WEIGHT_4_WRR(uint32_t _x)
3391 { return (((_x) << QUEUE_WEIGHT_4_WRR_Pos) & QUEUE_WEIGHT_4_WRR_Msk); }
3392 inline uint32_t SCHED_MODE(uint32_t _x)
3393 { return (((_x) << SCHED_MODE_Pos) & SCHED_MODE_Msk); }
3394
3395}
3396
3397
3398namespace PORT_LUE_CTRL {
3399 enum {
3400 SELF_ADDR_FILT_Pos = 3,
3401 SELF_ADDR_FILT_Msk = (0x1 << SELF_ADDR_FILT_Pos),
3402 SELF_ADDR_FILT_ENABLED = (0x1 << SELF_ADDR_FILT_Pos),
3403 SELF_ADDR_FILT_DISABLED = (0x0 << SELF_ADDR_FILT_Pos),
3404 MAC_8021X_Pos = 4,
3405 MAC_8021X_Msk = (0x1 << MAC_8021X_Pos),
3406 MAC_8021X_ENABLED = (0x1 << MAC_8021X_Pos),
3407 MAC_8021X_DISABLED = (0x0 << MAC_8021X_Pos),
3408 DISCARD_NON_PVID_Pos = 5,
3409 DISCARD_NON_PVID_Msk = (0x1 << DISCARD_NON_PVID_Pos),
3410 DISCARD_NON_PVID_ENABLED = (0x1 << DISCARD_NON_PVID_Pos),
3411 DISCARD_NON_PVID_DISABLED = (0x0 << DISCARD_NON_PVID_Pos),
3412 INGRESS_VLAN_FILT_Pos = 6,
3413 INGRESS_VLAN_FILT_Msk = (0x1 << INGRESS_VLAN_FILT_Pos),
3414 INGRESS_VLAN_FILT_ENABLED = (0x1 << INGRESS_VLAN_FILT_Pos),
3415 INGRESS_VLAN_FILT_DISABLED = (0x0 << INGRESS_VLAN_FILT_Pos),
3416 NULL_VID_LOOKUP_Pos = 7,
3417 NULL_VID_LOOKUP_Msk = (0x1 << NULL_VID_LOOKUP_Pos),
3418 NULL_VID_LOOKUP_ENABLED = (0x1 << NULL_VID_LOOKUP_Pos),
3419 NULL_VID_LOOKUP_DISABLED = (0x0 << NULL_VID_LOOKUP_Pos),
3420 };
3421
3422}
3423namespace PORT_MSTP_STATE {
3424 enum {
3425 PORT_LEARNING_Pos = 0,
3426 PORT_LEARNING_Msk = (0x1 << PORT_LEARNING_Pos),
3427 PORT_LEARNING_ENABLED = (0x0 << PORT_LEARNING_Pos),
3428 PORT_LEARNING_DISABLED = (0x1 << PORT_LEARNING_Pos),
3429 PORT_RX_Pos = 1,
3430 PORT_RX_Msk = (0x1 << PORT_RX_Pos),
3431 PORT_RX_ENABLED = (0x1 << PORT_RX_Pos),
3432 PORT_RX_DISABLED = (0x0 << PORT_RX_Pos),
3433 PORT_TX_Pos = 2,
3434 PORT_TX_Msk = (0x1 << PORT_TX_Pos),
3435 PORT_TX_ENABLED = (0x1 << PORT_TX_Pos),
3436 PORT_TX_DISABLED = (0x0 << PORT_TX_Pos),
3437 };
3438
3439 inline uint32_t ACL_IDX(uint32_t _x)
3440 { return (((_x) << ACL_IDX_Pos) & SNIFFER_PORT_Msk); }
3441
3442}
3443
3444#endif