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qspiBsp.h
1/*NB_REVISION*/
2
3/*NB_COPYRIGHT*/
4
5#ifndef _QSPI_BSP_H_
6#define _QSPI_BSP_H_
7#include <basictypes.h>
8/*
9 *****************************************************************************-
10 *
11 * Definitions
12 *
13 *****************************************************************************-
14 */
15/*
16 * Interrupt controller settings for:
17 * MOD5270
18 * SB70
19 * MOD5213
20 * PK70
21 * MOD5282
22 * MOD5234
23 */
24/* Interrupt source (vector) */
25#define QSPI_INTERRUPT_SOURCE (18)
26
27/* Interrupt level */
28#define QSPI_INTERRUPT_LEVEL (2)
29
30/* Interrupt level */
31#define QSPI_INTERRUPT_PRIORITY (7)
32
33/*
34 * RAM addresses
35 */
36#define QSPI_RAM_ENTRIES (16)
37#define QSPI_RAM_TRANSMIT_START (0x00)
38#define QSPI_RAM_RECEIVE_START (0x10)
39#define QSPI_RAM_COMMAND_START (0x20)
40
41/*
42 *****************************************************************************-
43 *
44 * Structures
45 *
46 *****************************************************************************-
47 */
48/*
49 QSPI Mode Register (QMR)
50 mstr - Master mode, must be one
51 dohie - DOUT high impedance or driven when idle?
52 bits - Transfer size 8 through 16 (1000-1111 & 0000 )
53 cpol - Clock polarity (is inactive level)
54 cpha - Clock phase of data capture, 0 leading, 1 falling
55 baud - Baud rate divider 0 disables, 2-255
56
57 */
58typedef struct _QmrFields
59{
60 uint16_t mstr : 1;
61 uint16_t dohie : 1;
62 uint16_t bits : 4;
63 uint16_t cpol : 1;
64 uint16_t cpha : 1;
65 uint16_t baud : 8;
66
67} __attribute__((packed)) QmrFields;
68
69typedef union _Qmr
70{
71 QmrFields field;
72 uint16_t content;
73
74} __attribute__((packed)) Qmr;
75
76/*
77 QSPI Delay Register (QDLYR)
78 spe - Enable
79 qcd - Chip select to valid clock (dsck bit in command RAM)
80 dtl - Delay after transfer (dt bit in command RAM)
81
82 */
83typedef struct _QdlyrFields
84{
85 uint16_t spe : 1;
86 uint16_t qcd : 7;
87 uint16_t dtl : 8;
88
89} __attribute__((packed)) QdlyrFields;
90
91typedef union _Qdlyr
92{
93 QdlyrFields field;
94 uint16_t content;
95
96} __attribute__((packed)) Qdlyr;
97
98/*
99 QSPI Wrap Register (QWR)
100 halt - Halts transfer
101 wren - Wrap around enabled
102 wrto - Wrap around location
103 csiv - Chip select inactive level
104 endqp - End of queue pointer
105 cptqp - Completed queue entry pointer (R)
106 newqp - Start of queue pointer
107
108 */
109typedef struct _QwrFields
110{
111 uint16_t halt : 1;
112 uint16_t wren : 1;
113 uint16_t wrto : 1;
114 uint16_t csiv : 1;
115 uint16_t endqp : 4;
116 uint16_t cptqp : 4;
117 uint16_t newqp : 4;
118
119} __attribute__((packed)) QwrFields;
120
121typedef union _Qwr
122{
123 QwrFields field;
124 uint16_t content;
125
126} __attribute__((packed)) Qwr;
127
128/*
129 QSPI Interrupt Register (QIR)
130 wcefb - Write collision access error enable
131 abrtb - Abort access error enable
132 abrtl - Abort lockout
133 wcefe - Write collision interrupt enable
134 abrte - Abort interrupt enable
135 spife - Finished interrupt enable
136 wcef - Write collision error flag
137 abrt - Abort flag
138 spif - Finished flag
139
140 */
141typedef struct _QirFields
142{
143 uint16_t wcefb : 1;
144 uint16_t abrtb : 1;
145 uint16_t mbz_13 : 1;
146 uint16_t abrtl : 1;
147 uint16_t wcefe : 1;
148 uint16_t abrte : 1;
149 uint16_t mbz_09 : 1;
150 uint16_t spife : 1;
151 uint16_t mbz_04_07 : 4;
152 uint16_t wcef : 1;
153 uint16_t abrt : 1;
154 uint16_t mbz_01 : 1;
155 uint16_t spif : 1;
156
157} __attribute__((packed)) QirFields;
158
159typedef union _Qir
160{
161 QirFields field;
162 uint16_t content;
163
164} __attribute__((packed)) Qir;
165
166/*
167 QSPI Command Register(s) (QCR)
168 cont - Continuous (0-stop, 1-go)
169 bitse - Eight bits or qmr.field.bits
170 dt - Delay after transfer (0-default, 1-qdlyr.dtl)
171 dsck - Chip select to valid clock (0-1/2 clock, 1-qdlyr.qcd)
172 qspi_cs - Chip select mask [3:0]
173
174 */
175typedef struct _QcrFields
176{
177 uint16_t cont : 1;
178 uint16_t bitse : 1;
179 uint16_t dt : 1;
180 uint16_t dsck : 1;
181 uint16_t qspi_cs : 4;
182 uint16_t mbz_00_07 : 8;
183
184} __attribute__((packed)) QcrFields;
185
186typedef union _Qcr
187{
188 QcrFields field;
189 uint16_t content;
190
191} __attribute__((packed)) Qcr;
192
193/*
194 ******************************************************************************
195 *
196 * Routines
197 *
198 ******************************************************************************
199 */
200
201/*
202 ******************************************************************************
203
204 Interrupt service routine (ISR)
205
206 Parameters:
207 None
208
209 Return:
210 None
211
212 Notes:
213 None
214
215 ******************************************************************************
216 */
217typedef void(QspiIsr)(void);
218
219/*
220 ******************************************************************************
221
222 Setup QSPI module
223
224 Parameters:
225 setHighDrive - Drive strength TRUE high, FALSE low
226
227 Return:
228 0 - OK, all else problems
229
230 Notes:
231 Set assigned pins QSPI_DOUT, QSPI_DIN, QSPI_CLK and drive strength install
232 BSP Isr.
233
234 ******************************************************************************
235 */
236int QspiSetupHardware(BOOL setHighDrive);
237
238/*
239 ******************************************************************************
240
241 Attach chip select to QSPI module
242
243 Parameters:
244 controlledChipSelects - Chip selects [3:0] respectively
245
246 Return:
247 0 - OK, all else problems
248
249 Notes:
250 Driver user can let the module assert/de-assert chip select by attaching
251 or use QspiSelectChip and QspiDeselectChip based on device requirements.
252 The last call to QspiAttachChipSelects/QspiDetachChipSelects is the one
253 controlling.
254
255 ******************************************************************************
256 */
257int QspiAttachChipSelects(uint8_t controlledChipSelects);
258
259/*
260 ******************************************************************************
261
262 Detach chip selects from QSPI module set as GPIO pins
263
264 Parameters:
265 controlledChipSelects - Chip selects [3:0] respectively
266
267 Return:
268 0 - OK, all else problems
269
270 Notes:
271 User can assert/de-assert chip select by detaching and calling
272 QspiAssertChipSelects and QspiDeassertChipSelects.
273 The last call to QspiAttachChipSelects/QspiDetachChipSelects is the one
274 controlling.
275
276 ******************************************************************************
277 */
278int QspiDetachChipSelects(uint8_t controlledChipSelects);
279
280/*
281 ******************************************************************************
282
283 Asserts chip selects
284
285 Parameters:
286 controlledChipSelects - Chip selects [3:0] respectively
287 isChipSelectActiveLow - Chips select phase
288 TRUE Active low, inactive high
289 TRUE Active high, inactive low
290
291
292 Return:
293 Notes
294
295 Notes:
296 Driver must call QspiAttachChipSelects/QspiDetachChipSelects.
297
298 ******************************************************************************
299 */
300void QspiAssertChipSelects(uint8_t controlledChipSelects, BOOL isChipSelectActiveLow);
301
302/*
303 ******************************************************************************
304
305 Deasserts chip selects
306
307 Parameters:
308 controlledChipSelects - Chip selects [3:0] respectively
309 isChipSelectActiveLow - Chips select phase
310 TRUE Active low, inactive high
311 TRUE Active high, inactive low
312
313
314 Return:
315 Notes
316
317 Notes:
318 Driver must call QspiAttachChipSelects/QspiDetachChipSelects.
319
320 ******************************************************************************
321 */
322void QspiDeassertChipSelects(uint8_t controlledChipSelects, BOOL isChipSelectActiveLow);
323
324/*
325 ******************************************************************************
326
327 Installs interrupt service routine
328
329 Parameters:
330 isr - "C" interrupt service routine
331
332 Return:
333 None
334
335 Notes:
336 None
337
338 ******************************************************************************
339 */
340void QspiSetupIsr(QspiIsr isr);
341
342/*
343 ******************************************************************************
344
345 Get baud rate setting
346
347 Parameters:
348 baudRateInMhz - Baud rate requested in Mhz
349
350 Return:
351 Lowest near integral setting within processor/module limits.
352
353 Notes:
354 Base on processor and clock speed.
355
356 ******************************************************************************
357 */
358uint8_t QspiGetBaudSetting(unsigned long baudRateInMhz);
359
360/*
361 ******************************************************************************
362
363 Get current baud rate setting
364
365 Parameters:
366 None
367
368 Return:
369 Baud rate setting in Mhz
370
371 Notes:
372 Base on processor and clock speed.
373
374 ******************************************************************************
375 */
376unsigned long QspiGetCurrentBaudSetting(void);
377
378/*
379 ******************************************************************************
380
381 Enable module interrupt
382
383 Parameters:
384 None
385
386 Return:
387 None
388
389 Notes:
390 None
391
392 ******************************************************************************
393 */
394void QspiEnableIsr(void);
395
396/*
397 ******************************************************************************
398
399 Disable module interrupt
400
401 Parameters:
402 None
403
404 Return:
405 None
406
407 Notes:
408 None
409
410 ******************************************************************************
411 */
412void QspiDisableIsr(void);
413
414/*
415 ******************************************************************************
416
417 Get module registers
418
419 Parameters:
420 None
421
422 Return:
423 None
424
425 Notes:
426 None
427
428 ******************************************************************************
429 */
430void QspiGetRegisters(volatile uint16_t **qmrPtr,
431 volatile uint16_t **qdlyrPtr,
432 volatile uint16_t **qwrPtr,
433 volatile uint16_t **qirPtr,
434 volatile uint16_t **qarPtr,
435 volatile uint16_t **qdrPtr);
436
437#endif /* _QSPI_BSP_H_ */