plat_cfg_ethernet.h

#ifndef  __PLAT_CFG_ETHERNET_H
#define  __PLAT_CFG_ETHERNET_H
/*NB_REVISION*/
 
/*NB_COPYRIGHT*/
 
#define ENET_TXCLK      Pin_DISP_B2_05
#define ENET_TX_EN      Pin_DISP_B2_04
#define ENET_TXD0       Pin_DISP_B2_02
#define ENET_TXD1       Pin_DISP_B2_03
#define ENET_TXD2       PinIO()
#define ENET_TXD3       PinIO()
#define ENET_CRS_DV     Pin_DISP_B2_08
#define ENET_RXD0       Pin_DISP_B2_06
#define ENET_RXD1       Pin_DISP_B2_07
#define ENET_RXD2       PinIO()
#define ENET_RXD3       PinIO()
#define ENET_RXCLK      PinIO()
#define ENET_RXER       Pin_DISP_B2_09
#define ENET_MDC        Pin_AD_32
#define ENET_MDIO       Pin_AD_33
#define ENET_SDO        PinIO()
#define ENET_SCS        PinIO()
#define ENET_RESET      Pin_LPSR_12
#define ENET_IRQ        Pin_AD_12
#define ENET_SPEED_LED  Pin_AD_14 //FIXME
#define ENET_RESET_POL  0
#define ENET_IRQ_POL    0
 
#define ENET_1G_TX_EN     Pin_DISP_B1_10
#define ENET_1G_TXCLK     Pin_DISP_B1_11
#define ENET_1G_TXD0      Pin_DISP_B1_09
#define ENET_1G_TXD1      Pin_DISP_B1_08
#define ENET_1G_TXD2      Pin_DISP_B1_07
#define ENET_1G_TXD3      Pin_DISP_B1_06
#define ENET_1G_RXD0      Pin_DISP_B1_02
#define ENET_1G_RXD1      Pin_DISP_B1_03
#define ENET_1G_RXD2      Pin_DISP_B1_04
#define ENET_1G_RXD3      Pin_DISP_B1_05
#define ENET_1G_RXER      PinIO()
#define ENET_1G_RXCLK     Pin_DISP_B1_01
#define ENET_1G_CRS_DV    Pin_DISP_B1_00
#define ENET_1G_MDC       Pin_EMC_B2_19
#define ENET_1G_MDIO      Pin_EMC_B2_20
#define ENET_1G_SDO       PinIO()
#define ENET_1G_SCS       PinIO()
#define ENET_1G_RESET     Pin_SNVS_02
#define ENET_1G_IRQ       Pin_SNVS_03
#define ENET_1G_RESET_POL 1
#define ENET_1G_IRQ_POL   0
 
#define ENET_1G_TX_EN_FN     PinIO::PIN_FN_1
#define ENET_1G_TXC_FN       PinIO::PIN_FN_1
#define ENET_1G_TXD0_FN      PinIO::PIN_FN_1
#define ENET_1G_TXD1_FN      PinIO::PIN_FN_1
#define ENET_1G_TXD2_FN      PinIO::PIN_FN_1
#define ENET_1G_TXD3_FN      PinIO::PIN_FN_1
#define ENET_1G_RXD0_FN      PinIO::PIN_FN_1
#define ENET_1G_RXD1_FN      PinIO::PIN_FN_1
#define ENET_1G_RXD2_FN      PinIO::PIN_FN_1
#define ENET_1G_RXD3_FN      PinIO::PIN_FN_1
#define ENET_1G_RXC_FN       PinIO::PIN_FN_1
#define ENET_1G_MDC_FN       PinIO::PIN_FN_2
#define ENET_1G_MDIO_FN      PinIO::PIN_FN_2
#define ENET_1G_RESET_FN     PinIO::PIN_FN_OUT
#define ENET_1G_SPEED_LED     Pin_AD_04
 
 
#define ALT_ENET_1G_TXCLK     PinIO()
#define ALT_ENET_1G_TX_EN     PinIO()
#define ALT_ENET_1G_TXD0      PinIO()
#define ALT_ENET_1G_TXD1      PinIO()
#define ALT_ENET_1G_TXD2      PinIO()
#define ALT_ENET_1G_TXD3      PinIO()
#define ALT_ENET_1G_CRS_DV    PinIO()
#define ALT_ENET_1G_RXD0      PinIO()
#define ALT_ENET_1G_RXD1      PinIO()
#define ALT_ENET_1G_RXD2      PinIO()
#define ALT_ENET_1G_RXD3      PinIO()
#define ALT_ENET_1G_RXER      PinIO()
#define ALT_ENET_1G_RXCLK     PinIO()
#define ALT_ENET_1G_MDC       PinIO()
#define ALT_ENET_1G_MDIO      PinIO()
#define ALT_ENET_1G_SDO       PinIO()
#define ALT_ENET_1G_SCS       PinIO()
#define ALT_ENET_1G_RESET     PinIO()
#define ALT_ENET_1G_SPEED_LED PinIO()
#define ALT_ENET_1G_IRQ       PinIO()
#define ALT_ENET_1G_RESET_POL 1
#define ALT_ENET_1G_IRQ_POL   0
 
 
#endif   /* ----- #ifndef __PLAT_CFG_ETHERNET_H  ----- */