NetBurner 3.5.6
PDF Version
periph_clocks.h
1
#ifndef __PERIPH_CLOCKS_H
2
#define __PERIPH_CLOCKS_H
3
4
#include <sim5441x.h>
5
6
// Peripheral Power Management Low Register 0
7
#define PERIPH_CLOCK_FLEXBUS 2
8
#define PERIPH_CLOCK_CAN_0 8
9
#define PERIPH_CLOCK_CAN_1 9
10
#define PERIPH_CLOCK_I2C_1 14
11
#define PERIPH_CLOCK_DSPI_1 15
12
#define PERIPH_CLOCK_DMA 17
13
#define PERIPH_CLOCK_INTC_0 18
14
#define PERIPH_CLOCK_INTC_1 19
15
#define PERIPH_CLOCK_INTC_2 20
16
#define PERIPH_CLOCK_I2C_0 22
17
#define PERIPH_CLOCK_DSPI_0 23
18
#define PERIPH_CLOCK_UART_0 24
19
#define PERIPH_CLOCK_UART_1 25
20
#define PERIPH_CLOCK_UART_2 26
21
#define PERIPH_CLOCK_UART_3 27
22
#define PERIPH_CLOCK_DMA_TMR_0 28
23
#define PERIPH_CLOCK_DMA_TMR_1 29
24
#define PERIPH_CLOCK_DMA_TMR_2 30
25
#define PERIPH_CLOCK_DMA_TMR_3 31
26
27
// Peripheral Power Management High Register 0
28
#define PERIPH_CLOCK_PIT_0 32
29
#define PERIPH_CLOCK_PIT_1 33
30
#define PERIPH_CLOCK_PIT_2 34
31
#define PERIPH_CLOCK_PIT_3 35
32
#define PERIPH_CLOCK_EDGE_PORT 36
33
#define PERIPH_CLOCK_ADC 37
34
#define PERIPH_CLOCK_DAC_0 38
35
#define PERIPH_CLOCK_RTC 42
36
#define PERIPH_CLOCK_SIM 43
37
#define PERIPH_CLOCK_USB_OTG 44
38
#define PERIPH_CLOCK_USB_HOST 45
39
#define PERIPH_CLOCK_DDR 46
40
#define PERIPH_CLOCK_SSI_0 47
41
#define PERIPH_CLOCK_PLL 48
42
#define PERIPH_CLOCK_RNG 49
43
#define PERIPH_CLOCK_SSI_1 50
44
#define PERIPH_CLOCK_SDHC 52
45
#define PERIPH_CLOCK_MACNET_0 53
46
#define PERIPH_CLOCK_MACNET_1 54
47
#define PERIPH_CLOCK_ETHERNET_SWITCH_0 55
48
#define PERIPH_CLOCK_ETHERNET_SWITCH_1 56
49
#define PERIPH_CLOCK_NAND_FLASH 63
50
51
// Peripheral Power Management High Register 1
52
#define PERIPH_CLOCK_PWM 34
53
#define PERIPH_CLOCK_CCM_RESET 36
54
#define PERIPH_CLOCK_GPIO 37
55
56
// Peripheral Power Management Low Register 1
57
#define PERIPH_CLOCK_1_WIRE 2
58
#define PERIPH_CLOCK_I2C_2 4
59
#define PERIPH_CLOCK_I2C_3 5
60
#define PERIPH_CLOCK_I2C_4 6
61
#define PERIPH_CLOCK_I2C_5 7
62
#define PERIPH_CLOCK_DSPI_2 14
63
#define PERIPH_CLOCK_DSPI_3 15
64
#define PERIPH_CLOCK_UART_4 24
65
#define PERIPH_CLOCK_UART_5 25
66
#define PERIPH_CLOCK_UART_6 26
67
#define PERIPH_CLOCK_UART_7 27
68
#define PERIPH_CLOCK_UART_8 28
69
#define PERIPH_CLOCK_UART_9 29
70
71
// Disable clocks in Power Management Low Register 0
72
#define PERIPH_DISABLE_FLEXBUS sim2.scm.ppmsr0 = PERIPH_CLOCK_FLEXBUS
73
#define PERIPH_DISABLE_CAN_0 sim2.scm.ppmsr0 = PERIPH_CLOCK_CAN_0
74
#define PERIPH_DISABLE_CAN_1 sim2.scm.ppmsr0 = PERIPH_CLOCK_CAN_1
75
#define PERIPH_DISABLE_I2C_1 sim2.scm.ppmsr0 = PERIPH_CLOCK_I2C_1
76
#define PERIPH_DISABLE_DSPI_1 sim2.scm.ppmsr0 = PERIPH_CLOCK_DSPI_1
77
#define PERIPH_DISABLE_DMA sim2.scm.ppmsr0 = PERIPH_CLOCK_DMA
78
#define PERIPH_DISABLE_INTC_0 sim2.scm.ppmsr0 = PERIPH_CLOCK_INTC_0
79
#define PERIPH_DISABLE_INTC_1 sim2.scm.ppmsr0 = PERIPH_CLOCK_INTC_1
80
#define PERIPH_DISABLE_INTC_2 sim2.scm.ppmsr0 = PERIPH_CLOCK_INTC_2
81
#define PERIPH_DISABLE_I2C_0 sim2.scm.ppmsr0 = PERIPH_CLOCK_I2C_0
82
#define PERIPH_DISABLE_DSPI_0 sim2.scm.ppmsr0 = PERIPH_CLOCK_DSPI_0
83
#define PERIPH_DISABLE_UART_0 sim2.scm.ppmsr0 = PERIPH_CLOCK_UART_0
84
#define PERIPH_DISABLE_UART_1 sim2.scm.ppmsr0 = PERIPH_CLOCK_UART_1
85
#define PERIPH_DISABLE_UART_2 sim2.scm.ppmsr0 = PERIPH_CLOCK_UART_2
86
#define PERIPH_DISABLE_UART_3 sim2.scm.ppmsr0 = PERIPH_CLOCK_UART_3
87
#define PERIPH_DISABLE_DMA_TMR_0 sim2.scm.ppmsr0 = PERIPH_CLOCK_DMA_TMR_0
88
#define PERIPH_DISABLE_DMA_TMR_1 sim2.scm.ppmsr0 = PERIPH_CLOCK_DMA_TMR_1
89
#define PERIPH_DISABLE_DMA_TMR_2 sim2.scm.ppmsr0 = PERIPH_CLOCK_DMA_TMR_2
90
91
// Enable clocks in Power Management Low Register 0
92
#define PERIPH_ENABLE_FLEXBUS sim2.scm.ppmcr0 = PERIPH_CLOCK_FLEXBUS
93
#define PERIPH_ENABLE_CAN_0 sim2.scm.ppmcr0 = PERIPH_CLOCK_CAN_0
94
#define PERIPH_ENABLE_CAN_1 sim2.scm.ppmcr0 = PERIPH_CLOCK_CAN_1
95
#define PERIPH_ENABLE_I2C_1 sim2.scm.ppmcr0 = PERIPH_CLOCK_I2C_1
96
#define PERIPH_ENABLE_DSPI_1 sim2.scm.ppmcr0 = PERIPH_CLOCK_DSPI_1
97
#define PERIPH_ENABLE_DMA sim2.scm.ppmcr0 = PERIPH_CLOCK_DMA
98
#define PERIPH_ENABLE_INTC_0 sim2.scm.ppmcr0 = PERIPH_CLOCK_INTC_0
99
#define PERIPH_ENABLE_INTC_1 sim2.scm.ppmcr0 = PERIPH_CLOCK_INTC_1
100
#define PERIPH_ENABLE_INTC_2 sim2.scm.ppmcr0 = PERIPH_CLOCK_INTC_2
101
#define PERIPH_ENABLE_I2C_0 sim2.scm.ppmcr0 = PERIPH_CLOCK_I2C_0
102
#define PERIPH_ENABLE_DSPI_0 sim2.scm.ppmcr0 = PERIPH_CLOCK_DSPI_0
103
#define PERIPH_ENABLE_UART_0 sim2.scm.ppmcr0 = PERIPH_CLOCK_UART_0
104
#define PERIPH_ENABLE_UART_1 sim2.scm.ppmcr0 = PERIPH_CLOCK_UART_1
105
#define PERIPH_ENABLE_UART_2 sim2.scm.ppmcr0 = PERIPH_CLOCK_UART_2
106
#define PERIPH_ENABLE_UART_3 sim2.scm.ppmcr0 = PERIPH_CLOCK_UART_3
107
#define PERIPH_ENABLE_DMA_TMR_0 sim2.scm.ppmcr0 = PERIPH_CLOCK_DMA_TMR_0
108
#define PERIPH_ENABLE_DMA_TMR_1 sim2.scm.ppmcr0 = PERIPH_CLOCK_DMA_TMR_1
109
#define PERIPH_ENABLE_DMA_TMR_2 sim2.scm.ppmcr0 = PERIPH_CLOCK_DMA_TMR_2
110
111
// Disable clocks in Power Management High Register 0
112
#define PERIPH_DISABLE_PIT_0 sim2.scm.ppmsr0 = PERIPH_CLOCK_PIT_0
113
#define PERIPH_DISABLE_PIT_1 sim2.scm.ppmsr0 = PERIPH_CLOCK_PIT_1
114
#define PERIPH_DISABLE_PIT_2 sim2.scm.ppmsr0 = PERIPH_CLOCK_PIT_2
115
#define PERIPH_DISABLE_PIT_3 sim2.scm.ppmsr0 = PERIPH_CLOCK_PIT_3
116
#define PERIPH_DISABLE_EDGE_PORT sim2.scm.ppmsr0 = PERIPH_CLOCK_EDGE_PORT
117
#define PERIPH_DISABLE_ADC sim2.scm.ppmsr0 = PERIPH_CLOCK_ADC
118
#define PERIPH_DISABLE_DAC_0 sim2.scm.ppmsr0 = PERIPH_CLOCK_DAC_0
119
#define PERIPH_DISABLE_RTC sim2.scm.ppmsr0 = PERIPH_CLOCK_RTC
120
#define PERIPH_DISABLE_SIM sim2.scm.ppmsr0 = PERIPH_CLOCK_SIM
121
#define PERIPH_DISABLE_USB_OTG sim2.scm.ppmsr0 = PERIPH_CLOCK_USB_OTG
122
#define PERIPH_DISABLE_USB_HOST sim2.scm.ppmsr0 = PERIPH_CLOCK_USB_HOST
123
#define PERIPH_DISABLE_DDR sim2.scm.ppmsr0 = PERIPH_CLOCK_DDR
124
#define PERIPH_DISABLE_SSI_0 sim2.scm.ppmsr0 = PERIPH_CLOCK_SSI_0
125
#define PERIPH_DISABLE_PLL sim2.scm.ppmsr0 = PERIPH_CLOCK_PLL
126
#define PERIPH_DISABLE_RNG sim2.scm.ppmsr0 = PERIPH_CLOCK_RNG
127
#define PERIPH_DISABLE_SSI_1 sim2.scm.ppmsr0 = PERIPH_CLOCK_SSI_1
128
#define PERIPH_DISABLE_SDHC sim2.scm.ppmsr0 = PERIPH_CLOCK_SDHC
129
#define PERIPH_DISABLE_MACNET_0 sim2.scm.ppmsr0 = PERIPH_CLOCK_MACNET_0
130
#define PERIPH_DISABLE_MACNET_1 sim2.scm.ppmsr0 = PERIPH_CLOCK_MACNET_1
131
#define PERIPH_DISABLE_ETHERNET_SWITCH_0 sim2.scm.ppmsr0 = PERIPH_CLOCK_ETHERNET_SWITCH_0
132
#define PERIPH_DISABLE_ETHERNET_SWITCH_1 sim2.scm.ppmsr0 = PERIPH_CLOCK_ETHERNET_SWITCH_1
133
#define PERIPH_DISABLE_NAND_FLASH sim2.scm.ppmsr0 = PERIPH_CLOCK_NAND_FLASH
134
135
// Enable clocks in Power Management High Register 0
136
#define PERIPH_ENABLE_PIT_0 sim2.scm.ppmcr0 = PERIPH_CLOCK_PIT_0
137
#define PERIPH_ENABLE_PIT_1 sim2.scm.ppmcr0 = PERIPH_CLOCK_PIT_1
138
#define PERIPH_ENABLE_PIT_2 sim2.scm.ppmcr0 = PERIPH_CLOCK_PIT_2
139
#define PERIPH_ENABLE_PIT_3 sim2.scm.ppmcr0 = PERIPH_CLOCK_PIT_3
140
#define PERIPH_ENABLE_EDGE_PORT sim2.scm.ppmcr0 = PERIPH_CLOCK_EDGE_PORT
141
#define PERIPH_ENABLE_ADC sim2.scm.ppmcr0 = PERIPH_CLOCK_ADC
142
#define PERIPH_ENABLE_DAC_0 sim2.scm.ppmcr0 = PERIPH_CLOCK_DAC_0
143
#define PERIPH_ENABLE_RTC sim2.scm.ppmcr0 = PERIPH_CLOCK_RTC
144
#define PERIPH_ENABLE_SIM sim2.scm.ppmcr0 = PERIPH_CLOCK_SIM
145
#define PERIPH_ENABLE_USB_OTG sim2.scm.ppmcr0 = PERIPH_CLOCK_USB_OTG
146
#define PERIPH_ENABLE_USB_HOST sim2.scm.ppmcr0 = PERIPH_CLOCK_USB_HOST
147
#define PERIPH_ENABLE_DDR sim2.scm.ppmcr0 = PERIPH_CLOCK_DDR
148
#define PERIPH_ENABLE_SSI_0 sim2.scm.ppmcr0 = PERIPH_CLOCK_SSI_0
149
#define PERIPH_ENABLE_PLL sim2.scm.ppmcr0 = PERIPH_CLOCK_PLL
150
#define PERIPH_ENABLE_RNG sim2.scm.ppmcr0 = PERIPH_CLOCK_RNG
151
#define PERIPH_ENABLE_SSI_1 sim2.scm.ppmcr0 = PERIPH_CLOCK_SSI_1
152
#define PERIPH_ENABLE_SDHC sim2.scm.ppmcr0 = PERIPH_CLOCK_SDHC
153
#define PERIPH_ENABLE_MACNET_0 sim2.scm.ppmcr0 = PERIPH_CLOCK_MACNET_0
154
#define PERIPH_ENABLE_MACNET_1 sim2.scm.ppmcr0 = PERIPH_CLOCK_MACNET_1
155
#define PERIPH_ENABLE_ETHERNET_SWITCH_0 sim2.scm.ppmcr0 = PERIPH_CLOCK_ETHERNET_SWITCH_0
156
#define PERIPH_ENABLE_ETHERNET_SWITCH_1 sim2.scm.ppmcr0 = PERIPH_CLOCK_ETHERNET_SWITCH_1
157
#define PERIPH_ENABLE_NAND_FLASH sim2.scm.ppmcr0 = PERIPH_CLOCK_NAND_FLASH
158
159
// Disable clocks in Power Management Low Register 1
160
#define PERIPH_DISABLE_1_WIRE sim2.scm.ppmsr1 = PERIPH_CLOCK_1_WIRE
161
#define PERIPH_DISABLE_I2C_2 sim2.scm.ppmsr1 = PERIPH_CLOCK_I2C_2
162
#define PERIPH_DISABLE_I2C_3 sim2.scm.ppmsr1 = PERIPH_CLOCK_I2C_3
163
#define PERIPH_DISABLE_I2C_4 sim2.scm.ppmsr1 = PERIPH_CLOCK_I2C_4
164
#define PERIPH_DISABLE_I2C_5 sim2.scm.ppmsr1 = PERIPH_CLOCK_I2C_5
165
#define PERIPH_DISABLE_DSPI_2 sim2.scm.ppmsr1 = PERIPH_CLOCK_DSPI_2
166
#define PERIPH_DISABLE_DSPI_3 sim2.scm.ppmsr1 = PERIPH_CLOCK_DSPI_3
167
#define PERIPH_DISABLE_UART_4 sim2.scm.ppmsr1 = PERIPH_CLOCK_UART_4
168
#define PERIPH_DISABLE_UART_5 sim2.scm.ppmsr1 = PERIPH_CLOCK_UART_5
169
#define PERIPH_DISABLE_UART_6 sim2.scm.ppmsr1 = PERIPH_CLOCK_UART_6
170
#define PERIPH_DISABLE_UART_7 sim2.scm.ppmsr1 = PERIPH_CLOCK_UART_7
171
#define PERIPH_DISABLE_UART_8 sim2.scm.ppmsr1 = PERIPH_CLOCK_UART_8
172
#define PERIPH_DISABLE_UART_9 sim2.scm.ppmsr1 = PERIPH_CLOCK_UART_9
173
174
// Enable clocks in Power Management Low Register 1
175
#define PERIPH_ENABLE_1_WIRE sim2.scm.ppmcr1 = PERIPH_CLOCK_1_WIRE
176
#define PERIPH_ENABLE_I2C_2 sim2.scm.ppmcr1 = PERIPH_CLOCK_I2C_2
177
#define PERIPH_ENABLE_I2C_3 sim2.scm.ppmcr1 = PERIPH_CLOCK_I2C_3
178
#define PERIPH_ENABLE_I2C_4 sim2.scm.ppmcr1 = PERIPH_CLOCK_I2C_4
179
#define PERIPH_ENABLE_I2C_5 sim2.scm.ppmcr1 = PERIPH_CLOCK_I2C_5
180
#define PERIPH_ENABLE_DSPI_2 sim2.scm.ppmcr1 = PERIPH_CLOCK_DSPI_2
181
#define PERIPH_ENABLE_DSPI_3 sim2.scm.ppmcr1 = PERIPH_CLOCK_DSPI_3
182
#define PERIPH_ENABLE_UART_4 sim2.scm.ppmcr1 = PERIPH_CLOCK_UART_4
183
#define PERIPH_ENABLE_UART_5 sim2.scm.ppmcr1 = PERIPH_CLOCK_UART_5
184
#define PERIPH_ENABLE_UART_6 sim2.scm.ppmcr1 = PERIPH_CLOCK_UART_6
185
#define PERIPH_ENABLE_UART_7 sim2.scm.ppmcr1 = PERIPH_CLOCK_UART_7
186
#define PERIPH_ENABLE_UART_8 sim2.scm.ppmcr1 = PERIPH_CLOCK_UART_8
187
#define PERIPH_ENABLE_UART_9 sim2.scm.ppmcr1 = PERIPH_CLOCK_UART_9
188
189
// Disable clocks in Power Management High Register 1
190
#define PERIPH_DISABLE_PWM sim2.scm.ppmsr1 = PERIPH_CLOCK_PWM
191
#define PERIPH_DISABLE_CCM_RESET sim2.scm.ppmsr1 = PERIPH_CLOCK_CCM_RESET
192
#define PERIPH_DISABLE_GPIO sim2.scm.ppmsr1 = PERIPH_CLOCK_GPIO
193
194
// Enable clocks in Power Management High Register 1
195
#define PERIPH_ENABLE_PWM sim2.scm.ppmcr1 = PERIPH_CLOCK_PWM
196
#define PERIPH_ENABLE_CCM_RESET sim2.scm.ppmcr1 = PERIPH_CLOCK_CCM_RESET
197
#define PERIPH_ENABLE_GPIO sim2.scm.ppmcr1 = PERIPH_CLOCK_GPIO
198
199
#endif
/* ----- #ifndef __PERIPH_CLOCKS_H ----- */
