mcan_internal.h

 
#ifndef __MCAN_INTERNAL_H__
#define __MCAN_INTERNAL_H__
 
#include <same70q21_sim.h>
 
/* -------- MCAN_RX_ELEMENT_R0 : (MCAN RX element: 0x00) (R/W 32) Rx Element R0 Configuration -------- */
typedef union
{
    struct
    {
        /* bit:  0..28  Identifier */
        uint32_t ID:29;
        /* bit:  29     Remote Transmission Request */
        uint32_t RTR:1;
        /* bit:  30     Extended Identifier */
        uint32_t XTD:1;
        /* bit:  31     Error State Indicator */
        uint32_t ESI:1;
    } bit;
    /* Type used for register access */
    uint32_t reg;
} MCAN_RX_ELEMENT_R0_Type;
 
#define MCAN_RX_ELEMENT_R0_ID_Pos          0
#define MCAN_RX_ELEMENT_R0_ID_Msk          (0x1FFFFFFFul << MCAN_RX_ELEMENT_R0_ID_Pos)
#define MCAN_RX_ELEMENT_R0_ID(value)       ((MCAN_RX_ELEMENT_R0_ID_Msk & ((value) << MCAN_RX_ELEMENT_R0_ID_Pos)))
#define MCAN_RX_ELEMENT_R0_RTR_Pos         29
#define MCAN_RX_ELEMENT_R0_RTR             (0x1ul << MCAN_RX_ELEMENT_R0_RTR_Pos)
#define MCAN_RX_ELEMENT_R0_XTD_Pos         30
#define MCAN_RX_ELEMENT_R0_XTD             (0x1ul << MCAN_RX_ELEMENT_R0_XTD_Pos)
#define MCAN_RX_ELEMENT_R0_ESI_Pos         31
#define MCAN_RX_ELEMENT_R0_ESI             (0x1ul << MCAN_RX_ELEMENT_R0_ESI_Pos)
 
/* -------- MCAN_RX_ELEMENT_R1 : (MCAN RX element: 0x01) (R/W 32) Rx Element R1 Configuration -------- */
typedef union
{
    struct
    {
        /* bit: 0..15   Rx Timestamp */
        uint32_t RXTS:16;
        /* bit: 16..19  Data Length Code */
        uint32_t DLC:4;
        /* bit: 20      Bit Rate Switch */
        uint32_t BRS:1;
        /* bit: 21      FD Format */
        uint32_t EDL:1;
        /* bit: 22..23  Reserved */
        uint32_t :2;
        /* bit: 24..30  Filter Index */
        uint32_t FIDX:7;
        /* bit: 31      Accepted Non-matching Frame */
        uint32_t ANMF:1;
    } bit;
    /* Type used for register access */
    uint32_t reg;
} MCAN_RX_ELEMENT_R1_Type;
 
#define MCAN_RX_ELEMENT_R1_RXTS_Pos        0
#define MCAN_RX_ELEMENT_R1_RXTS_Msk        (0xFFFFul << MCAN_RX_ELEMENT_R1_RXTS_Pos)
#define MCAN_RX_ELEMENT_R1_RXTS(value)     ((MCAN_RX_ELEMENT_R1_RXTS_Msk & ((value) << MCAN_RX_ELEMENT_R1_RXTS_Pos)))
#define MCAN_RX_ELEMENT_R1_DLC_Pos         16
#define MCAN_RX_ELEMENT_R1_DLC_Msk         (0xFul << MCAN_RX_ELEMENT_R1_DLC_Pos)
#define MCAN_RX_ELEMENT_R1_DLC(value)      ((MCAN_RX_ELEMENT_R1_DLC_Msk & ((value) << MCAN_RX_ELEMENT_R1_DLC_Pos)))
#define MCAN_RX_ELEMENT_R1_BRS_Pos         20
#define MCAN_RX_ELEMENT_R1_BRS             (0x1ul << MCAN_RX_ELEMENT_R1_BRS_Pos)
#define MCAN_RX_ELEMENT_R1_FDF_Pos         21
#define MCAN_RX_ELEMENT_R1_FDF             (0x1ul << MCAN_RX_ELEMENT_R1_FDF_Pos)
#define MCAN_RX_ELEMENT_R1_FIDX_Pos        24
#define MCAN_RX_ELEMENT_R1_FIDX_Msk        (0x7Ful << MCAN_RX_ELEMENT_R1_FIDX_Pos)
#define MCAN_RX_ELEMENT_R1_FIDX(value)     ((MCAN_RX_ELEMENT_R1_FIDX_Msk & ((value) << MCAN_RX_ELEMENT_R1_FIDX_Pos)))
#define MCAN_RX_ELEMENT_R1_ANMF_Pos        31
#define MCAN_RX_ELEMENT_R1_ANMF            (0x1ul << MCAN_RX_ELEMENT_R1_ANMF_Pos)
 
struct mcan_rx_element_buffer
{
    __IO MCAN_RX_ELEMENT_R0_Type R0;
    __IO MCAN_RX_ELEMENT_R1_Type R1;
    uint8_t data[CONF_MCAN_ELEMENT_DATA_SIZE];
};
 
 
/* -------- MCAN_TX_ELEMENT_T0 : (MCAN TX element: 0x00) (R/W 32) Tx Element T0 Configuration -------- */
typedef union
{
    struct
    {
        /* bit:  0..28  Identifier */
        uint32_t ID:29;
        /* bit:  29     Remote Transmission Request */
        uint32_t RTR:1;
        /* bit:  30     Extended Identifier */
        uint32_t XTD:1;
#if (SAMV71B || SAME70B || SAMV70B)
        /* bit:  31     Error State Indicator */
        uint32_t ESI:1;        
#else
        /* bit:  31     Reserved */
        uint32_t :1;
#endif        
    } bit;
    /* Type used for register access */
    uint32_t reg;
} MCAN_TX_ELEMENT_T0_Type;
 
#define MCAN_TX_ELEMENT_T0_EXTENDED_ID_Pos          0
#define MCAN_TX_ELEMENT_T0_EXTENDED_ID_Msk          (0x1FFFFFFFul << MCAN_TX_ELEMENT_T0_EXTENDED_ID_Pos)
#define MCAN_TX_ELEMENT_T0_EXTENDED_ID(value)       ((MCAN_TX_ELEMENT_T0_EXTENDED_ID_Msk & ((value) << MCAN_TX_ELEMENT_T0_EXTENDED_ID_Pos)))
#define MCAN_TX_ELEMENT_T0_STANDARD_ID_Pos          18
#define MCAN_TX_ELEMENT_T0_STANDARD_ID_Msk          (0x7FFul << MCAN_TX_ELEMENT_T0_STANDARD_ID_Pos)
#define MCAN_TX_ELEMENT_T0_STANDARD_ID(value)       ((MCAN_TX_ELEMENT_T0_STANDARD_ID_Msk & ((value) << MCAN_TX_ELEMENT_T0_STANDARD_ID_Pos)))
#define MCAN_TX_ELEMENT_T0_RTR_Pos         29
#define MCAN_TX_ELEMENT_T0_RTR             (0x1ul << MCAN_TX_ELEMENT_T0_RTR_Pos)
#define MCAN_TX_ELEMENT_T0_XTD_Pos         30
#define MCAN_TX_ELEMENT_T0_XTD             (0x1ul << MCAN_TX_ELEMENT_T0_XTD_Pos)
#if (SAMV71B || SAME70B || SAMV70B)
    #define MCAN_TX_ELEMENT_T0_ESI_Pos         31
    #define MCAN_TX_ELEMENT_T0_ESI             (0x1ul << MCAN_TX_ELEMENT_T0_ESI_Pos)
#endif 
 
/* -------- MCAN_TX_ELEMENT_T1 : (MCAN TX element: 0x01) (R/W 32) Tx Element T1 Configuration -------- */
typedef union
{
    struct
    {
        /* bit: 0..15   Reserved */
        uint32_t :16;
        /* bit: 16..19  Data Length Code */
        uint32_t DLC:4;
#if (SAMV71B || SAME70B || SAMV70B)
        /* bit: 20      Bit Rate Switch */
        uint32_t BRS:1;
        /* bit: 21      FD Format */
        uint32_t FDF:1;
        /* bit: 22  Reserved */
        uint32_t :1;
#else
        /* bit: 20..22  Reserved */
        uint32_t :3;
#endif  
        /* bit: 23      Event FIFO Control */
        uint32_t EFCC:1;
        /* bit: 24..31  Message Marker */
        uint32_t MM:8;
    } bit;
    /* Type used for register access */
    uint32_t reg;
} MCAN_TX_ELEMENT_T1_Type;
 
#define MCAN_TX_ELEMENT_T1_DLC_Pos         16
#define MCAN_TX_ELEMENT_T1_DLC_Msk         (0xFul << MCAN_TX_ELEMENT_T1_DLC_Pos)
#define MCAN_TX_ELEMENT_T1_DLC(value)      ((MCAN_TX_ELEMENT_T1_DLC_Msk & ((value) << MCAN_TX_ELEMENT_T1_DLC_Pos)))
#define MCAN_TX_ELEMENT_T1_DLC_DATA8_Val        0x8ul
#define MCAN_TX_ELEMENT_T1_DLC_DATA12_Val       0x9ul
#define MCAN_TX_ELEMENT_T1_DLC_DATA16_Val       0xAul
#define MCAN_TX_ELEMENT_T1_DLC_DATA20_Val       0xBul
#define MCAN_TX_ELEMENT_T1_DLC_DATA24_Val       0xCul
#define MCAN_TX_ELEMENT_T1_DLC_DATA32_Val       0xDul
#define MCAN_TX_ELEMENT_T1_DLC_DATA48_Val       0xEul
#define MCAN_TX_ELEMENT_T1_DLC_DATA64_Val       0xFul
#if (SAMV71B || SAME70B || SAMV70B)
    #define MCAN_TX_ELEMENT_T1_BRS_Pos         20
    #define MCAN_TX_ELEMENT_T1_BRS             (0x1ul << MCAN_TX_ELEMENT_T1_BRS_Pos)
    #define MCAN_TX_ELEMENT_T1_FDF_Pos         21
    #define MCAN_TX_ELEMENT_T1_FDF             (0x1ul << MCAN_TX_ELEMENT_T1_FDF_Pos)
#endif
#define MCAN_TX_ELEMENT_T1_EFC_Pos         23
#define MCAN_TX_ELEMENT_T1_EFC             (0x1ul << MCAN_TX_ELEMENT_T1_EFC_Pos)
#define MCAN_TX_ELEMENT_T1_MM_Pos          24
#define MCAN_TX_ELEMENT_T1_MM_Msk          (0xFFul << MCAN_TX_ELEMENT_T1_MM_Pos)
#define MCAN_TX_ELEMENT_T1_MM(value)       ((MCAN_TX_ELEMENT_T1_MM_Msk & ((value) << MCAN_TX_ELEMENT_T1_MM_Pos)))
 
struct mcan_tx_element
{
    __IO MCAN_TX_ELEMENT_T0_Type T0;
    __IO MCAN_TX_ELEMENT_T1_Type T1;
    uint8_t data[CONF_MCAN_ELEMENT_DATA_SIZE];
};
 
/* -------- MCAN_TX_EVENT_ELEMENT_E0 : (MCAN TX event element: 0x00) (R/W 32) Tx Event Element E0 Configuration -------- */
typedef union
{
    struct
    {
        /* bit: 0..28  Identifier */
        uint32_t ID:29;
        /* bit: 29     Remote Transmission Request */
        uint32_t RTR:1;
        /* bit: 30     Extended Identifier */
        uint32_t XTD:1;
        /* bit: 31     Error State Indicator */
        uint32_t ESI:1;
    } bit;
    /* Type used for register access */
    uint32_t reg;
} MCAN_TX_EVENT_ELEMENT_E0_Type;
 
#define MCAN_TX_EVENT_ELEMENT_E0_ID_Pos          0
#define MCAN_TX_EVENT_ELEMENT_E0_ID_Msk          (0x1FFFFFFFul << MCAN_TX_EVENT_ELEMENT_E0_ID_Pos)
#define MCAN_TX_EVENT_ELEMENT_E0_ID(value)       ((MCAN_TX_EVENT_ELEMENT_E0_ID_Msk & ((value) << MCAN_TX_EVENT_ELEMENT_E0_ID_Pos)))
#define MCAN_TX_EVENT_ELEMENT_E0_RTR_Pos         29
#define MCAN_TX_EVENT_ELEMENT_E0_RTR             (0x1ul << MCAN_TX_EVENT_ELEMENT_E0_RTR_Pos)
#define MCAN_TX_EVENT_ELEMENT_E0_XTD_Pos         30
#define MCAN_TX_EVENT_ELEMENT_E0_XTD             (0x1ul << MCAN_TX_EVENT_ELEMENT_E0_XTD_Pos)
#define MCAN_TX_EVENT_ELEMENT_E0_ESI_Pos         31
#define MCAN_TX_EVENT_ELEMENT_E0_ESI             (0x1ul << MCAN_TX_EVENT_ELEMENT_E0_ESI_Pos)
 
/* -------- MCAN_TX_EVENT_ELEMENT_E1 : (MCAN TX event element: 0x01) (R/W 32) Tx Event Element E1 Configuration -------- */
typedef union
{
    struct
    {
        /* bit: 0..15   Tx Timestamp */
        uint32_t TXTS:16;
        /* bit: 16..19  Data Length Code */
        uint32_t DLC:4;
        /* bit: 20      Bit Rate Switch */
        uint32_t BRS:1;
        /* bit: 21      FD Format */
        uint32_t EDL:1;
        /* bit: 22..23  Event Type */
        uint32_t ET:2;
        /* bit: 24..31  Message Marker */
        uint32_t MM:8;
    } bit;
    /* Type used for register access */
    uint32_t reg;
} MCAN_TX_EVENT_ELEMENT_E1_Type;
 
#define MCAN_TX_EVENT_ELEMENT_E1_TXTS_Pos        0
#define MCAN_TX_EVENT_ELEMENT_E1_TXTS_Msk        (0xFFFFul << MCAN_TX_EVENT_ELEMENT_E1_TXTS_Pos)
#define MCAN_TX_EVENT_ELEMENT_E1_TXTS(value)     ((MCAN_TX_EVENT_ELEMENT_E1_TXTS_Msk & ((value) << MCAN_TX_EVENT_ELEMENT_E1_TXTS_Pos)))
#define MCAN_TX_EVENT_ELEMENT_E1_DLC_Pos         16
#define MCAN_TX_EVENT_ELEMENT_E1_DLC_Msk         (0xFul << MCAN_TX_EVENT_ELEMENT_E1_DLC_Pos)
#define MCAN_TX_EVENT_ELEMENT_E1_DLC(value)      ((MCAN_TX_EVENT_ELEMENT_E1_DLC_Msk & ((value) << MCAN_TX_EVENT_ELEMENT_E1_DLC_Pos)))
#define MCAN_TX_EVENT_ELEMENT_E1_BRS_Pos         20
#define MCAN_TX_EVENT_ELEMENT_E1_BRS             (0x1ul << MCAN_TX_EVENT_ELEMENT_E1_BRS_Pos)
#define MCAN_TX_EVENT_ELEMENT_E1_FDF_Pos         21
#define MCAN_TX_EVENT_ELEMENT_E1_FDF             (0x1ul << MCAN_TX_EVENT_ELEMENT_E1_FDF_Pos)
#define MCAN_TX_EVENT_ELEMENT_E1_ET_Pos          22
#define MCAN_TX_EVENT_ELEMENT_E1_ET_Msk          (0x3ul << MCAN_TX_EVENT_ELEMENT_E1_ET_Pos)
#define MCAN_TX_EVENT_ELEMENT_E1_ET(value)       ((MCAN_TX_EVENT_ELEMENT_E1_ET_Msk & ((value) << MCAN_TX_EVENT_ELEMENT_E1_ET_Pos)))
#define MCAN_TX_EVENT_ELEMENT_E1_MM_Pos          24
#define MCAN_TX_EVENT_ELEMENT_E1_MM_Msk          (0xFFul << MCAN_TX_EVENT_ELEMENT_E1_MM_Pos)
#define MCAN_TX_EVENT_ELEMENT_E1_MM(value)       ((MCAN_TX_EVENT_ELEMENT_E1_MM_Msk & ((value) << MCAN_TX_EVENT_ELEMENT_E1_MM_Pos)))
 
struct mcan_tx_event_element
{
    __IO MCAN_TX_EVENT_ELEMENT_E0_Type E0;
    __IO MCAN_TX_EVENT_ELEMENT_E1_Type E1;
};
 
/* -------- MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0 : (MCAN standard message ID filter element: 0x00) (R/W 32) Standard Message ID Filter Element S0 Configuration -------- */
typedef union
{
    struct
    {
        /* bit: 0..10   Standard Filter ID 2 */
        uint32_t SFID2:11;
        /* bit: 11..15  Reserved */
        uint32_t :5;
        /* bit: 16..26  Standard Filter ID 1 */
        uint32_t SFID1:11;
        /* bit: 27..29  Standard Filter Element Configuration */
        uint32_t SFEC:3;
        /* bit: 30..31  Standard Filter Type */
        uint32_t SFT:2;
    } bit;
    /* Type used for register access */
    uint32_t reg;
} MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_Type;
 
#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID2_Pos          0
#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID2_Msk          (0x7FFul << MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID2_Pos)
#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID2(value)       ((MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID2_Msk & ((value) << MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID2_Pos)))
#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID1_Pos          16
#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID1_Msk          (0x7FFul << MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID1_Pos)
#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID1(value)       ((MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID1_Msk & ((value) << MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID1_Pos)))
#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_Pos           27
#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_Msk           (0x7ul << MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_Pos)
#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC(value)        ((MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_Msk & ((value) << MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_Pos)))
#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_DISABLE_Val     0
#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_STF0M_Val       1
#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_STF1M_Val       2
#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_REJECT_Val      3
#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_PRIORITY_Val    4
#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_PRIF0M_Val      5
#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_PRIF1M_Val      6
#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_STRXBUF_Val     7
#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_Pos            30
#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_Msk            (0x3ul << MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_Pos)
#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT(value)         ((MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_Msk & ((value) << MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_Pos)))
#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_RANGE          MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT(0)
#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_DUAL           MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT(1)
#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_CLASSIC        MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT(2)
 
class mcan_module;
class mcan_standard_message_filter_element
{
private:
        __IO MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_Type S0;
public:
    mcan_standard_message_filter_element() {S0.reg=0;};
    mcan_standard_message_filter_element(int id, int mask=0x7FF) 
    {
     set_id_mask(id,mask); 
    }
    void set_id_mask(int id, int mask=0x7FF);
    void set_exact(int id1, int id2);
    inline void set_exact(int id1) {set_id_mask(id1); };
    friend mcan_module;
};
 
 
 
 
 
 
 
 
 
/* -------- MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0 : (MCAN extended message ID filter element: 0x00) (R/W 32) Extended Message ID Filter Element F0 Configuration -------- */
typedef union
{
    struct
    {
        /* bit: 0..28   Extended Filter ID 1 */
        uint32_t EFID1:29;
        /* bit: 29..31  Extended Filter Element Configuration */
        uint32_t EFEC:3;
    } bit;
    /* Type used for register access */
    uint32_t reg;
} MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_Type;
 
#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFID1_Pos          0
#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFID1_Msk          (0x1FFFFFFFul << MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFID1_Pos)
#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFID1(value)       ((MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFID1_Msk & ((value) << MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFID1_Pos)))
#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_Pos           29
#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_Msk           (0x7ul << MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_Pos)
#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC(value)        ((MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_Msk & ((value) << MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_Pos)))
#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_DISABLE_Val       0
#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_STF0M_Val         1
#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_STF1M_Val         2
#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_REJECT_Val        3
#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_PRIORITY_Val      4
#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_PRIF0M_Val        5
#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_PRIF1M_Val        6
#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_STRXBUF_Val       7
 
/* -------- MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1 : (MCAN extended message ID filter element: 0x01) (R/W 32) Extended Message ID Filter Element F1 Configuration -------- */
typedef union
{
    struct
    {
        /* bit: 0..28  Extended Filter ID 2 */
        uint32_t EFID2:29;
        /* bit: 29     Reserved */
        uint32_t :1;
        /* bit: 30..31 Extended Filter Type */
        uint32_t EFT:2;
    } bit;
    /* Type used for register access */
    uint32_t reg;
} MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_Type;
 
#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFID2_Pos          0
#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFID2_Msk          (0x1FFFFFFFul << MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFID2_Pos)
#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFID2(value)       ((MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFID2_Msk & ((value) << MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFID2_Pos)))
#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_Pos            30
#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_Msk            (0x3ul << MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_Pos)
#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT(value)         ((MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_Msk & ((value) << MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_Pos)))
#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_RANGEM       MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT(0)
#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_DUAL         MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT(1)
#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_CLASSIC      MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT(2)
#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_RANGE        MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT(3)
 
class mcan_extended_message_filter_element
{
private:
    __IO MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_Type F0;
    __IO MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_Type F1;
public:
    mcan_extended_message_filter_element() {F0.reg=0; F1.reg=0; }; 
    mcan_extended_message_filter_element(int id,int mask=0x1FFFFFFF) 
    {
     set_id_mask(id,mask); 
    }
    void set_id_mask(int id, int mask=0x1FFFFFFF);
    void set_exact(int id1, int id2);
    inline void set_exact(int id1) {set_id_mask(id1); };
 friend mcan_module;
};
/* @} */
 
 
enum status_code {
    STATUS_OK               =  0, 
    STATUS_ERR_BUSY         =  0x19,
    STATUS_ERR_DENIED       =  0x1C,
    STATUS_ERR_TIMEOUT      =  0x12,
    ERR_IO_ERROR            =  -1, 
    ERR_FLUSHED             =  -2, 
    ERR_TIMEOUT             =  -3, 
    ERR_BAD_DATA            =  -4, 
    ERR_PROTOCOL            =  -5, 
    ERR_UNSUPPORTED_DEV     =  -6, 
    ERR_NO_MEMORY           =  -7, 
    ERR_INVALID_ARG         =  -8, 
    ERR_BAD_ADDRESS         =  -9, 
    ERR_BUSY                =  -10, 
    ERR_BAD_FORMAT          =  -11, 
    ERR_NO_TIMER            =  -12, 
    ERR_TIMER_ALREADY_RUNNING   =  -13, 
    ERR_TIMER_NOT_RUNNING   =  -14, 
    ERR_ABORTED             =  -15, 
    OPERATION_IN_PROGRESS   = -128,
};
 
 
 
enum mcan_timeout_mode
{
    MCAN_TIMEOUT_CONTINUES = MCAN_TOCC_TOS_CONTINUOUS,
    MCAN_TIMEOUT_TX_EVEN_FIFO = MCAN_TOCC_TOS_TX_EV_TIMEOUT,
    MCAN_TIMEOUT_RX_FIFO_0 = MCAN_TOCC_TOS_RX0_EV_TIMEOUT,
    MCAN_TIMEOUT_RX_FIFO_1 = MCAN_TOCC_TOS_RX1_EV_TIMEOUT,
};
 
 
enum mcan_nonmatching_frames_action
{
    MCAN_NONMATCHING_FRAMES_FIFO_0,
    MCAN_NONMATCHING_FRAMES_FIFO_1,
    MCAN_NONMATCHING_FRAMES_REJECT,
};
 
 
 
enum mcan_interrupt_source
{
    MCAN_RX_FIFO_0_NEW_MESSAGE = MCAN_IE_RF0NE,
    MCAN_RX_FIFO_0_WATERMARK = MCAN_IE_RF0WE,
    MCAN_RX_FIFO_0_FULL = MCAN_IE_RF0FE,
    MCAN_RX_FIFO_0_LOST_MESSAGE = MCAN_IE_RF0LE,
    MCAN_RX_FIFO_1_NEW_MESSAGE = MCAN_IE_RF1NE,
    MCAN_RX_FIFO_1_WATERMARK = MCAN_IE_RF1WE,
    MCAN_RX_FIFO_1_FULL = MCAN_IE_RF1FE,
    MCAN_RX_FIFO_1_MESSAGE_LOST = MCAN_IE_RF1LE,
    MCAN_RX_HIGH_PRIORITY_MESSAGE = MCAN_IE_HPME,
    MCAN_TIMESTAMP_COMPLETE = MCAN_IE_TCE,
    MCAN_TX_CANCELLATION_FINISH = MCAN_IE_TCFE,
    MCAN_TX_FIFO_EMPTY = MCAN_IE_TFEE,
    MCAN_TX_EVENT_FIFO_NEW_ENTRY = MCAN_IE_TEFNE,
    MCAN_TX_EVENT_FIFO_WATERMARK = MCAN_IE_TEFWE,
    MCAN_TX_EVENT_FIFO_FULL = MCAN_IE_TEFFE,
    MCAN_TX_EVENT_FIFO_ELEMENT_LOST = MCAN_IE_TEFLE,
    MCAN_TIMESTAMP_WRAPAROUND = MCAN_IE_TSWE,
    MCAN_MESSAGE_RAM_ACCESS_FAILURE = MCAN_IE_MRAFE,
    MCAN_TIMEOUT_OCCURRED = MCAN_IE_TOOE,
    MCAN_RX_BUFFER_NEW_MESSAGE = MCAN_IE_DRXE,
    MCAN_ERROR_LOGGING_OVERFLOW = MCAN_IE_ELOE,
    MCAN_ERROR_PASSIVE = MCAN_IE_EPE,
    MCAN_WARNING_STATUS = MCAN_IE_EWE,
    MCAN_BUS_OFF = MCAN_IE_BOE,
    MCAN_WATCHDOG = MCAN_IE_WDIE,
    MCAN_CRC_ERROR = MCAN_IE_CRCEE,
    MCAN_BIT_ERROR = MCAN_IE_BEE,
    MCAN_ACKNOWLEDGE_ERROR = MCAN_IE_ACKEE,
    MCAN_FORMAT_ERROR = MCAN_IE_FOEE,
    MCAN_STUFF_ERROR = MCAN_IE_STEE
};
struct tx_record
{
OS_SEM * pSem;
volatile uint32_t when;
};
 
#endif // __MCAN_INTERNAL_H__