mcan.h

 
/*
 * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
 */
 
#ifndef MCAN_H_INCLUDED
#define MCAN_H_INCLUDED
 
#include <conf_mcan.h>
#include <mcan_internal.h>
 
#ifdef DOXYGEN_STUFF 
namespace mcanMODM7AE70
{
#endif

 
 
#define SAME70B 1
 
#define DONT_WAIT (0xFFFFFFFF)  // Non-blocking value for CanRxMessage and GetNewMessage timeout parameter

 
const uint32_t CONF_MCAN_RX_FIFO_0_NUM              = 32; //16     
       
const uint32_t CONF_MCAN_RX_FIFO_1_NUM              = 1;  //16      
     
const uint32_t CONF_MCAN_RX_BUFFER_NUM              = 1;  //16

const uint32_t CONF_MCAN_TX_BUFFER_NUM              = 8;  // 4   
       
const uint32_t CONF_MCAN_TX_FIFO_QUEUE_NUM          = 1;  // 4     
      
const uint32_t CONF_MCAN_TX_EVENT_FIFO              = 8;  // 8             

const uint32_t CONF_MCAN_RX_STANDARD_ID_FILTER_NUM  = 32; //32    

const uint32_t CONF_MCAN_RX_EXTENDED_ID_FILTER_NUM  = 32; //16   
 
/****************WARNING **********************/
/* This is added to 
CONF_MCAN_RX_STANDARD_ID_FILTER_NUM
and
CONF_MCAN_RX_EXTENDED_ID_FILTER_NUMc
and
CONF_MCAN_TX_BUFFER_NUM
 
and the limits above must be ok with the added values.
*/          
const uint32_t CONF_MCAN_RTR_CHANNELS           = 8;

 
 

class mcan_module
{
    private:
        Mcan *hw;
        uint32_t TxBufferIndex;
        OS_SEM TxSem;
        volatile uint32_t standard_receive_index = 0;
        volatile uint32_t extended_receive_index = 0;
 
        __attribute__((__aligned__(0x0800)))
        struct mcan_rx_element_buffer mcan_rx_buffer[CONF_MCAN_RX_BUFFER_NUM];
        struct mcan_rx_element_buffer mcan_rx_fifo_0[CONF_MCAN_RX_FIFO_0_NUM];
        struct mcan_rx_element_buffer mcan_rx_fifo_1[CONF_MCAN_RX_FIFO_1_NUM];
        struct mcan_tx_element mcan_tx_buffer[CONF_MCAN_TX_BUFFER_NUM + CONF_MCAN_TX_FIFO_QUEUE_NUM+CONF_MCAN_RTR_CHANNELS];
        struct mcan_tx_event_element mcan_tx_event_fifo[CONF_MCAN_TX_EVENT_FIFO+CONF_MCAN_RTR_CHANNELS];
        struct mcan_standard_message_filter_element mcan_rx_standard_filter[CONF_MCAN_RX_STANDARD_ID_FILTER_NUM+CONF_MCAN_RTR_CHANNELS];
        struct mcan_extended_message_filter_element mcan_rx_extended_filter[CONF_MCAN_RX_EXTENDED_ID_FILTER_NUM+CONF_MCAN_RTR_CHANNELS];
 
        tx_record mcan_tx_record[CONF_MCAN_TX_BUFFER_NUM];
 
        OS_FIFO * Extended_Fifos[CONF_MCAN_RX_EXTENDED_ID_FILTER_NUM];
        OS_FIFO * Standard_Fifos[CONF_MCAN_RX_STANDARD_ID_FILTER_NUM];
 
        void enable_peripheral_clock();
        void message_memory_init();
        void set_configuration(struct mcan_config *config);
        void clean_up_pending_tx();
 
        void process_isr(void);
 
        void PushToFifo(mcan_rx_element_buffer * pBuffer, OS_FIFO * pFifo);
        void ack_tx(uint32_t index);
        void process_rx(mcan_rx_element_buffer * pBuffer);
 
        static mcan_module * this_Ref[2];
        static inline void dispatch_isr(int n) {if(this_Ref[n]) this_Ref[n]->process_isr(); };
        friend void MCAN0_Handler( void );
        friend void MCAN1_Handler( void );
 
        void set_baudrate(uint32_t baudrate);
        void fd_set_baudrate(uint32_t baudrate);
        void enable_fd_mode();
        void disable_fd_mode();
        void enable_restricted_operation_mode();
        void disable_restricted_operation_mode();
        void enable_bus_monitor_mode();
        void disable_bus_monitor_mode();
        void enable_sleep_mode();
        void disable_sleep_mode();
        void enable_test_mode();
        void disable_test_mode();
        enum status_code set_rx_standard_filter(struct mcan_standard_message_filter_element *sd_filter, uint32_t index);
        enum status_code set_rx_extended_filter(struct mcan_extended_message_filter_element *et_filter, uint32_t index);
        enum status_code get_rx_buffer_element (struct mcan_rx_element_buffer *rx_element, uint32_t index);
        enum status_code get_rx_fifo_0_element (struct mcan_rx_element_buffer *rx_element, uint32_t index);
        enum status_code get_rx_fifo_1_element (struct mcan_rx_element_buffer *rx_element, uint32_t index);
        enum status_code set_tx_buffer_element (struct mcan_tx_element *tx_element, uint32_t index);
        enum status_code get_tx_event_fifo_element(struct mcan_tx_event_element *tx_event_element, uint32_t index);
 
        /*
         * \brief Can read timestamp count value.
         *
         * \param[in] module_inst  Pointer to the MCAN software instance struct
         *
         * \return Timestamp count value.
         */
         inline uint16_t read_timestamp_count_value(){return hw->MCAN_TSCV;};
 
        /*
         * \brief Can read timeout count value.
         *
         * \param[in] module_inst  Pointer to the MCAN software instance struct
         *
         * \return Timeout count value.
         */
         inline uint16_t read_timeout_count_value(){return hw->MCAN_TOCV;};
 
        /*
         * \brief Read high priority message status.
         *
         * \param[in] module_inst  Pointer to the MCAN software instance struct
         *
         * \return High priority message status value.
         */
        inline uint32_t read_high_priority_message_status(){return hw->MCAN_HPMS;}
 
        /*
         * \brief Get Rx buffer status.
         *
         * \param[in] module_inst  Pointer to the MCAN software instance struct
         * \param[in] index  Index offset in Rx buffer
         *
         * \return Rx buffer status value.
         *
         *  \retval true Rx Buffer updated from new message.
         *  \retval false Rx Buffer not updated.
         */
        inline bool rx_get_buffer_status(uint32_t index)
        {
            if (index < 32)
            {
                if (hw->MCAN_NDAT1 & (1 << index))
                {
                    return true;
                } else
                {
                    return false;
                }
            } else
            {
                index -= 32;
                if (hw->MCAN_NDAT2 & (1 << index))
                {
                    return true;
                } else
                {
                    return false;
                }
            }
        };
 
        /*
         * \brief Clear Rx buffer status.
         *
         * \param[in] module_inst   Pointer to the MCAN software instance struct
         * \param[in] index         Index offset in Rx buffer
         */
        inline void rx_clear_buffer_status(uint32_t index)
        {
            if (index < 32)
            {
                hw->MCAN_NDAT1 = (1 << index);
            } else
            {
                index -= 32;
                hw->MCAN_NDAT2 = (1 << index);
            }
        }
 
        /*
         * \brief Get Rx FIFO status.
         *
         * \param[in] module_inst  Pointer to the MCAN software instance struct
         * \param[in] fifo_number  Rx FIFO 0 or 1
         *
         * \return Rx FIFO status value.
         */
        inline uint32_t rx_get_fifo_status(bool fifo_number)
        {
            if (!fifo_number)
            {
                return hw->MCAN_RXF0S;
            } else
            {
                return hw->MCAN_RXF1S;
            }
        }
 
        /*
         * \brief Set Rx acknowledge.
         *
         * \param[in] module_inst  Pointer to the MCAN software instance struct
         * \param[in] fifo_number  Rx FIFO 0 or 1
         * \param[in] index  Index offset in FIFO
         */
        inline void rx_fifo_acknowledge(bool fifo_number, uint32_t index)
        {
            if (!fifo_number)
            {
                hw->MCAN_RXF0A = MCAN_RXF0A_F0AI(index);
            } else
            {
                hw->MCAN_RXF1A = MCAN_RXF1A_F1AI(index);
            }
        }
 
        /*
         * \brief Get Tx FIFO/Queue status.
         *
         * \param[in] module_inst  Pointer to the MCAN software instance struct
         *
         * \return Tx FIFO/Queue status value.
         */
        inline uint32_t tx_get_fifo_queue_status()
        {
            return hw->MCAN_TXFQS;
        }
 
        /*
         * \brief Get Tx buffer request pending status.
         *
         * \param[in] module_inst  Pointer to the MCAN software instance struct
         *
         * \return Bit mask of Tx buffer request pending status value.
         */
        inline uint32_t tx_get_pending_status()
        {
            return hw->MCAN_TXBRP;
        }
 
        /*
         * \brief Tx buffer add transfer request.
         *
         * \param[in] module_inst  Pointer to the MCAN software instance struct
         * \param[in] trig_mask  The mask value to trigger transfer buffer
         *
         *  \return Status of the result.
         *
         *  \retval STATUS_OK   Set the transfer request.
         *  \retval STATUS_ERR_BUSY The module is in configuration.
         */
        inline enum status_code tx_transfer_request( uint32_t trig_mask)
        {
            if (hw->MCAN_CCCR & MCAN_CCCR_CCE)
            {
                return ERR_BUSY;
            }
            hw->MCAN_TXBAR = trig_mask;
            return STATUS_OK;
        }
 
        /*
         * \brief Set Tx Queue operation.
         *
         * \param[in] module_inst  Pointer to the MCAN software instance struct
         * \param[in] trig_mask  The mask value to cancel transfer buffer
         *
         *  \return Status of the result.
         *
         *  \retval STATUS_OK   Set the transfer request.
         *  \retval STATUS_BUSY The module is in configuration.
         */
        inline enum status_code tx_cancel_request( uint32_t trig_mask)
        {
            if (hw->MCAN_CCCR & MCAN_CCCR_CCE)
            {
                return STATUS_ERR_BUSY;
            }
            hw->MCAN_TXBCR = trig_mask;
            return STATUS_OK;
        }
 
        /*
         * \brief Get Tx transmission status.
         *
         * \param[in] module_inst  Pointer to the MCAN software instance struct
         *
         * \return Bit mask of Tx transmission status value.
         */
        inline uint32_t tx_get_transmission_status()
        {
            return hw->MCAN_TXBTO;
        }
 
        /*
         * \brief Get Tx cancellation status.
         *
         * \param[in] module_inst  Pointer to the MCAN software instance struct
         *
         * \return Bit mask of Tx cancellation status value.
         */
        inline uint32_t tx_get_cancellation_status()
        {
            return hw->MCAN_TXBCF;
        }
    
        /*
         * \brief Get Tx event FIFO status.
         *
         * \param[in] module_inst  Pointer to the MCAN software instance struct
         *
         * \return Tx event FIFO status value.
         */
        inline uint32_t tx_get_event_fifo_status()
        {
            return hw->MCAN_TXEFS;
        }
 
        /*
         * \brief Set Tx Queue operation.
         *
         * \param[in] module_inst  Pointer to the MCAN software instance struct
         * \param[in] index  Index for the transfer FIFO
         */
        inline void tx_event_fifo_acknowledge( uint32_t index)
        {
            hw->MCAN_TXEFA = MCAN_TXEFA_EFAI(index);
        }
 
        /*
         * \brief Enable MCAN interrupt.
         *
         * \param[in] module_inst  Pointer to the MCAN software instance struct
         * \param[in] source  Interrupt source type
         */
        inline void enable_interrupt(const enum mcan_interrupt_source source)
        {
            hw->MCAN_IE |= source;
        }
 
        /*
         * \brief Disable MCAN interrupt.
         *
         * \param[in] module_inst  Pointer to the MCAN software instance struct
         * \param[in] source  Interrupt source type
         */
        inline void disable_interrupt(const enum mcan_interrupt_source source)
        {
            hw->MCAN_IE &= ~source;
        }
 
        /*
         * \brief Get MCAN interrupt status.
         *
         * \param[in] module_inst  Pointer to the MCAN software instance struct
         */
        inline uint32_t read_interrupt_status()
        {
            return hw->MCAN_IR;
        }
 
        /*
         * \brief Clear MCAN interrupt status.
         *
         * \param[in] module_inst  Pointer to the MCAN software instance struct
         * \param[in] source  Interrupt source type
         *
         * \return Bit mask of interrupt status value.
         */
        inline void clear_interrupt_status(const enum mcan_interrupt_source source)
        {
            hw->MCAN_IR = source;
        }
 
 
    public:
        mcan_module(Mcan *phw, uint32_t baud);
 
        mcan_module(){};

        void init(Mcan *phw, struct mcan_config *config, uint32_t baud);

        int send_message(uint32_t id_value, uint8_t *data,uint32_t data_length, OS_SEM * pSem=0);

        bool blocking_send_message(uint32_t id_value, uint8_t *data,uint32_t data_length,uint32_t TimeOut);
 

        int RegisterRxFifo(uint32_t composite_id, OS_FIFO *pFifo, int channel = -1 );

        int RegisterRxFifoMask(uint32_t composite_id, uint32_t mask, OS_FIFO *pFifo, int channel = -1 );

        int RegisterRxFifoRange(uint32_t composite_id_low,uint32_t composite_id_hi, OS_FIFO *pFifo, int channel = -1 );

        int UnRegisterFifo(int channel );

        int MultiCanSetRTRMessage(uint32_t id, uint8_t *data, uint8_t len, int channel = -1 );

        int MultiCanReplaceRTRMessage(int channel, uint8_t *data, uint8_t len );

        int MultiCanStopRTRMessage(int channel );

        inline uint32_t read_error_count() { return hw->MCAN_ECR; }

        inline uint32_t read_protocol_status() { return hw->MCAN_PSR; }

        void start();

        void stop();
 
        // Toggle the TX line hi/low and print the result of the RX line.
        void IOTest();
 
};      // end class mcan_module
 


#define CAN_EXTENDED_ID_BIT (0x20000000)

#define ExtToNbId(id ) (id | CAN_EXTENDED_ID_BIT)

#define NormToNbId(id) (id & 0x7ff)

#define IsNBIdExt(id) ( (id & CAN_EXTENDED_ID_BIT)!=0)

#define NbToExtId(id) (id & 0x1FFFFFFF)

#define NbToNormId(id) (id & 0x7FF)
 

 

class mcan_config
{
    public:
        bool run_in_standby;
        uint8_t watchdog_configuration;
        bool transmit_pause;
        bool edge_filtering;
        bool protocol_exception_handling;
        bool automatic_retransmission;
        bool clock_stop_request;
        bool clock_stop_acknowledge;
        uint8_t timestamp_prescaler;
        uint16_t timeout_period;
        enum mcan_timeout_mode timeout_mode;
        bool timeout_enable;
        bool tdc_enable;
        uint8_t delay_compensation_offset;
        uint8_t delay_compensation_filter_window_length;
        enum mcan_nonmatching_frames_action nonmatching_frames_action_standard;
        enum mcan_nonmatching_frames_action nonmatching_frames_action_extended;
        bool remote_frames_standard_reject;
        bool remote_frames_extended_reject;
        uint32_t extended_id_mask;
        bool rx_fifo_0_overwrite;
        uint8_t rx_fifo_0_watermark;
        bool rx_fifo_1_overwrite;
        uint8_t rx_fifo_1_watermark;
        bool tx_queue_mode;
        uint8_t tx_event_fifo_watermark;

    inline void set_config_defaults()
    {
 
        /* Default configuration values */
        run_in_standby = false;
        watchdog_configuration = 0x00;
        transmit_pause = true;
        edge_filtering = true;
        protocol_exception_handling = true;
        automatic_retransmission = true;  //was true
        clock_stop_request = false;
        clock_stop_acknowledge = false;
        timestamp_prescaler = 0;
        timeout_period = 0xFFFF;
        timeout_mode = MCAN_TIMEOUT_CONTINUES;
        timeout_enable = false;
        tdc_enable = false;
        delay_compensation_offset = 0;
        delay_compensation_filter_window_length = 0;
        nonmatching_frames_action_standard = MCAN_NONMATCHING_FRAMES_REJECT;
        nonmatching_frames_action_extended = MCAN_NONMATCHING_FRAMES_REJECT;
        remote_frames_standard_reject = false;
        remote_frames_extended_reject = false;
        extended_id_mask = 0x1FFFFFFF;
        rx_fifo_0_overwrite = true;
        rx_fifo_0_watermark = 0;
        rx_fifo_1_overwrite = true;
        rx_fifo_1_watermark = 0;
        tx_queue_mode = false;
        tx_event_fifo_watermark = 0;
    }
 
};      // end mcan_config class
 
 

#define CAN_DATA_STORE_SIZE (512) 
 
 
struct PrivateCanData;

class CanRxMessage
{
   private:
      PrivateCanData *pData;
      /* Private constructor used for received frames */
      CanRxMessage( PrivateCanData *pData );
 
   public:
      uint8_t GetLength();

      uint8_t CopyData( uint8_t *buffer, uint8_t max_len );
      
      const uint8_t * GetData();

      uint32_t GetId();

      uint16_t GetTimeStamp();

      BOOL IsValid();
 
      /* Constructors */

      CanRxMessage( OS_FIFO *pFifo, uint32_t timeout = WAIT_FOREVER );

      ~CanRxMessage();

      BOOL GetNewMessage( OS_FIFO *pFifo, uint32_t timeout = WAIT_FOREVER );
};
 

 
#ifdef DOXYGEN_STUFF 
}   // namespace
#endif
 
 
#endif /* MCAN_H_INCLUDED */