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Vector offset definitions for predefined ColdFire exception and interrupt vectors. More...
Macros | |
#define | CF_ACCESSERROR_VECTOR 2 |
Access Error Exception Vector (Vector 2) | |
#define | CF_ADDRESSERROR_VECTOR 3 |
Address Error Exception Vector (Vector 3) | |
#define | CF_ILLEGAL_INSTRUCTION_VECTOR 4 |
Illegal Instruction Exception Vector (Vector 4) | |
#define | CF_PRIVLEDGE_VIOLATION_VECTOR 8 |
Privilege Violation Exception Vector (Vector 8) | |
#define | CF_TRACE_VECTOR 9 |
Trace Exception Vector (Vector 9) | |
#define | CF_UNIMPLMENTED_A_VECTOR 10 |
Unimplemented Line-A Opcode Exception Vector (Vector 10) | |
#define | CF_UNIMPLMENTED_F_VECTOR 11 |
Unimplemented Line-F Opcode Exception Vector (Vector 11) | |
#define | CF_DEBUG_INTERRUPT 12 |
Debug Interrupt Exception Vector (Vector 12) | |
#define | CF_FORMAT_ERR_VECTOR 14 |
Format Error Exception Vector (Vector 14) | |
#define | CF_UNINITIALIZED_VECTOR 15 |
Uninitialized Interrupt Exception Vector (Vector 15) | |
#define | CF_SPURIOUS_INT_VECTOR 24 |
Spurious Interrupt Exception Vector (Vector 24) | |
#define | CF_AUTOVECTOR_IRQ1 25 |
Autovector IRQ Level 1 (Vector 25) | |
#define | CF_AUTOVECTOR_IRQ2 26 |
Autovector IRQ Level 2 (Vector 26) | |
#define | CF_AUTOVECTOR_IRQ3 27 |
Autovector IRQ Level 3 (Vector 27) | |
#define | CF_AUTOVECTOR_IRQ4 28 |
Autovector IRQ Level 4 (Vector 28) | |
#define | CF_AUTOVECTOR_IRQ5 29 |
Autovector IRQ Level 5 (Vector 29) | |
#define | CF_AUTOVECTOR_IRQ6 30 |
Autovector IRQ Level 6 (Vector 30) | |
#define | CF_AUTOVECTOR_IRQ7 31 |
Autovector IRQ Level 7 (Vector 31) | |
#define | CF_TRAP0_VECTOR 32 |
TRAP #0 Instruction Vector (Vector 32) | |
#define | CF_TRAP1_VECTOR 33 |
TRAP #1 Instruction Vector (Vector 33) | |
#define | CF_TRAP2_VECTOR 34 |
TRAP #2 Instruction Vector (Vector 34) | |
#define | CF_TRAP3_VECTOR 35 |
TRAP #3 Instruction Vector (Vector 35) | |
#define | CF_TRAP4_VECTOR 36 |
TRAP #4 Instruction Vector (Vector 36) | |
#define | CF_TRAP5_VECTOR 37 |
TRAP #5 Instruction Vector (Vector 37) | |
#define | CF_TRAP6_VECTOR 38 |
TRAP #6 Instruction Vector (Vector 38) | |
#define | CF_TRAP7_VECTOR 39 |
TRAP #7 Instruction Vector (Vector 39) | |
#define | CF_TRAP8_VECTOR 40 |
TRAP #8 Instruction Vector (Vector 40) | |
#define | CF_TRAP9_VECTOR 41 |
TRAP #9 Instruction Vector (Vector 41) | |
#define | CF_TRAP10_VECTOR 42 |
TRAP #10 Instruction Vector (Vector 42) | |
#define | CF_TRAP11_VECTOR 43 |
TRAP #11 Instruction Vector (Vector 43) | |
#define | CF_TRAP12_VECTOR 44 |
TRAP #12 Instruction Vector (Vector 44) | |
#define | CF_TRAP13_VECTOR 45 |
TRAP #13 Instruction Vector (Vector 45) | |
#define | CF_TRAP14_VECTOR 46 |
TRAP #14 Instruction Vector (Vector 46) | |
#define | CF_TRAP15_VECTOR 47 |
TRAP #15 Instruction Vector (Vector 47) | |
#define | CF_USER_BASE_VECTOR 64 |
User-Defined Interrupt Vector Base (Vector 64) | |
Vector offset definitions for predefined ColdFire exception and interrupt vectors.
These definitions specify the vector table offsets for various ColdFire processor exceptions, traps, and interrupt sources. The vector table is an array of function pointers where each entry corresponds to a specific exception or interrupt handler.
The ColdFire vector table is organized into several regions:
Vector offsets are used to install interrupt handlers in the vector table:
#define CF_ACCESSERROR_VECTOR 2 |
#include <cfinter.h>
Access Error Exception Vector (Vector 2)
Triggered when an illegal memory access occurs, such as:
Expand for Example Usage
#define CF_ADDRESSERROR_VECTOR 3 |
#include <cfinter.h>
Address Error Exception Vector (Vector 3)
Triggered when the processor attempts to access a misaligned address or perform an invalid address operation:
#define CF_AUTOVECTOR_IRQ1 25 |
#include <cfinter.h>
Autovector IRQ Level 1 (Vector 25)
Autovectored interrupt request level 1 (lowest priority maskable interrupt).
#define CF_AUTOVECTOR_IRQ2 26 |
#include <cfinter.h>
Autovector IRQ Level 2 (Vector 26)
Autovectored interrupt request level 2.
#define CF_AUTOVECTOR_IRQ3 27 |
#include <cfinter.h>
Autovector IRQ Level 3 (Vector 27)
Autovectored interrupt request level 3.
#define CF_AUTOVECTOR_IRQ4 28 |
#include <cfinter.h>
Autovector IRQ Level 4 (Vector 28)
Autovectored interrupt request level 4.
#define CF_AUTOVECTOR_IRQ5 29 |
#include <cfinter.h>
Autovector IRQ Level 5 (Vector 29)
Autovectored interrupt request level 5.
#define CF_AUTOVECTOR_IRQ6 30 |
#include <cfinter.h>
Autovector IRQ Level 6 (Vector 30)
Autovectored interrupt request level 6.
#define CF_AUTOVECTOR_IRQ7 31 |
#include <cfinter.h>
Autovector IRQ Level 7 (Vector 31)
Autovectored interrupt request level 7 (highest priority, non-maskable).
#define CF_DEBUG_INTERRUPT 12 |
#include <cfinter.h>
Debug Interrupt Exception Vector (Vector 12)
Triggered by the on-chip debug module for hardware breakpoints and debugging. Used by BDM (Background Debug Mode) and JTAG debuggers.
#define CF_FORMAT_ERR_VECTOR 14 |
#include <cfinter.h>
Format Error Exception Vector (Vector 14)
Triggered when the processor encounters an invalid stack frame format during an exception return (RTE instruction).
#define CF_ILLEGAL_INSTRUCTION_VECTOR 4 |
#include <cfinter.h>
Illegal Instruction Exception Vector (Vector 4)
Triggered when the processor attempts to execute:
#define CF_PRIVLEDGE_VIOLATION_VECTOR 8 |
#include <cfinter.h>
Privilege Violation Exception Vector (Vector 8)
Triggered when user mode code attempts to execute a privileged instruction or access a privileged resource that requires supervisor mode.
Privileged operations include:
#define CF_SPURIOUS_INT_VECTOR 24 |
#include <cfinter.h>
Spurious Interrupt Exception Vector (Vector 24)
Triggered when an interrupt is acknowledged but no interrupt source is found. This can occur due to:
Expand for Example Usage
#define CF_TRACE_VECTOR 9 |
#include <cfinter.h>
Trace Exception Vector (Vector 9)
Triggered after each instruction when trace mode is enabled in the status register. Used for single-stepping through code during debugging.
#define CF_TRAP0_VECTOR 32 |
#include <cfinter.h>
TRAP #0 Instruction Vector (Vector 32)
Software interrupt triggered by the TRAP #0 instruction. TRAP instructions provide a mechanism for software-generated exceptions and system calls.
Expand for Example Usage
#define CF_TRAP10_VECTOR 42 |
#include <cfinter.h>
TRAP #10 Instruction Vector (Vector 42)
Software interrupt triggered by the TRAP #10 instruction.
#define CF_TRAP11_VECTOR 43 |
#include <cfinter.h>
TRAP #11 Instruction Vector (Vector 43)
Software interrupt triggered by the TRAP #11 instruction.
#define CF_TRAP12_VECTOR 44 |
#include <cfinter.h>
TRAP #12 Instruction Vector (Vector 44)
Software interrupt triggered by the TRAP #12 instruction.
#define CF_TRAP13_VECTOR 45 |
#include <cfinter.h>
TRAP #13 Instruction Vector (Vector 45)
Software interrupt triggered by the TRAP #13 instruction.
#define CF_TRAP14_VECTOR 46 |
#include <cfinter.h>
TRAP #14 Instruction Vector (Vector 46)
Software interrupt triggered by the TRAP #14 instruction.
#define CF_TRAP15_VECTOR 47 |
#include <cfinter.h>
TRAP #15 Instruction Vector (Vector 47)
Software interrupt triggered by the TRAP #15 instruction.
#define CF_TRAP1_VECTOR 33 |
#include <cfinter.h>
TRAP #1 Instruction Vector (Vector 33)
Software interrupt triggered by the TRAP #1 instruction.
#define CF_TRAP2_VECTOR 34 |
#include <cfinter.h>
TRAP #2 Instruction Vector (Vector 34)
Software interrupt triggered by the TRAP #2 instruction.
#define CF_TRAP3_VECTOR 35 |
#include <cfinter.h>
TRAP #3 Instruction Vector (Vector 35)
Software interrupt triggered by the TRAP #3 instruction.
#define CF_TRAP4_VECTOR 36 |
#include <cfinter.h>
TRAP #4 Instruction Vector (Vector 36)
Software interrupt triggered by the TRAP #4 instruction.
#define CF_TRAP5_VECTOR 37 |
#include <cfinter.h>
TRAP #5 Instruction Vector (Vector 37)
Software interrupt triggered by the TRAP #5 instruction.
#define CF_TRAP6_VECTOR 38 |
#include <cfinter.h>
TRAP #6 Instruction Vector (Vector 38)
Software interrupt triggered by the TRAP #6 instruction.
#define CF_TRAP7_VECTOR 39 |
#include <cfinter.h>
TRAP #7 Instruction Vector (Vector 39)
Software interrupt triggered by the TRAP #7 instruction.
#define CF_TRAP8_VECTOR 40 |
#include <cfinter.h>
TRAP #8 Instruction Vector (Vector 40)
Software interrupt triggered by the TRAP #8 instruction.
#define CF_TRAP9_VECTOR 41 |
#include <cfinter.h>
TRAP #9 Instruction Vector (Vector 41)
Software interrupt triggered by the TRAP #9 instruction.
#define CF_UNIMPLMENTED_A_VECTOR 10 |
#include <cfinter.h>
Unimplemented Line-A Opcode Exception Vector (Vector 10)
Triggered when the processor encounters an instruction with bits 15-12 = 1010 (0xA). These opcodes are reserved and unimplemented on ColdFire processors.
#define CF_UNIMPLMENTED_F_VECTOR 11 |
#include <cfinter.h>
Unimplemented Line-F Opcode Exception Vector (Vector 11)
Triggered when the processor encounters an instruction with bits 15-12 = 1111 (0xF). These opcodes are reserved and unimplemented on ColdFire processors.
#define CF_UNINITIALIZED_VECTOR 15 |
#include <cfinter.h>
Uninitialized Interrupt Exception Vector (Vector 15)
Triggered when an interrupt occurs but the interrupt controller has not been properly initialized or the interrupt vector has not been programmed.
#define CF_USER_BASE_VECTOR 64 |
#include <cfinter.h>
User-Defined Interrupt Vector Base (Vector 64)
Starting vector number for user-defined peripheral interrupts. Vectors 64 and above are available for assignment to custom interrupt sources such as:
The actual vector number for a peripheral interrupt is typically: CF_USER_BASE_VECTOR + peripheral_irq_number
Expand for Example Usage