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fsl_pwm.h
1#ifndef DOXYGEN_SHOULD_SKIP_THIS
2
3/*
4 * Copyright (c) 2015, Freescale Semiconductor, Inc.
5 * Copyright 2016-2022 NXP
6 * All rights reserved.
7 *
8 * SPDX-License-Identifier: BSD-3-Clause
9 */
10#ifndef FSL_PWM_H_
11#define FSL_PWM_H_
12
13#include "fsl_common.h"
14#include "MIMXRT1061_features.h"
15
16
22// netburner
23//#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA 1
24
25
26/*******************************************************************************
27 * Definitions
28 ******************************************************************************/
31#define FSL_PWM_DRIVER_VERSION (MAKE_VERSION(2, 8, 4))
35#define PWM_SUBMODULE_SWCONTROL_WIDTH 2
37#define PWM_SUBMODULE_CHANNEL 2
38
40typedef enum _pwm_submodule
41{
42 kPWM_Module_0 = 0U,
43 kPWM_Module_1,
44 kPWM_Module_2,
45#if defined(FSL_FEATURE_PWM_SUBMODULE_COUNT) && (FSL_FEATURE_PWM_SUBMODULE_COUNT > 3U)
46 kPWM_Module_3
47#endif /* FSL_FEATURE_PWM_SUBMODULE_COUNT */
48} pwm_submodule_t;
49
51typedef enum _pwm_channels
52{
53 kPWM_PwmB = 0U,
54 kPWM_PwmA,
55 kPWM_PwmX
56} pwm_channels_t;
57
59typedef enum _pwm_value_register
60{
61 kPWM_ValueRegister_0 = 0U,
62 kPWM_ValueRegister_1,
63 kPWM_ValueRegister_2,
64 kPWM_ValueRegister_3,
65 kPWM_ValueRegister_4,
66 kPWM_ValueRegister_5
67} pwm_value_register_t;
68
70enum _pwm_value_register_mask
71{
72 kPWM_ValueRegisterMask_0 = (1U << 0),
73 kPWM_ValueRegisterMask_1 = (1U << 1),
74 kPWM_ValueRegisterMask_2 = (1U << 2),
75 kPWM_ValueRegisterMask_3 = (1U << 3),
76 kPWM_ValueRegisterMask_4 = (1U << 4),
77 kPWM_ValueRegisterMask_5 = (1U << 5)
78};
79
81typedef enum _pwm_clock_source
82{
83 kPWM_BusClock = 0U,
84 kPWM_ExternalClock,
85 kPWM_Submodule0Clock
86} pwm_clock_source_t;
87
89typedef enum _pwm_clock_prescale
90{
91 kPWM_Prescale_Divide_1 = 0U,
92 kPWM_Prescale_Divide_2,
93 kPWM_Prescale_Divide_4,
94 kPWM_Prescale_Divide_8,
95 kPWM_Prescale_Divide_16,
96 kPWM_Prescale_Divide_32,
97 kPWM_Prescale_Divide_64,
98 kPWM_Prescale_Divide_128
99} pwm_clock_prescale_t;
100
102typedef enum _pwm_force_output_trigger
103{
104 kPWM_Force_Local = 0U,
105 kPWM_Force_Master,
106 kPWM_Force_LocalReload,
108 kPWM_Force_MasterReload,
109 kPWM_Force_LocalSync,
110 kPWM_Force_MasterSync,
111 kPWM_Force_External,
112 kPWM_Force_ExternalSync
113} pwm_force_output_trigger_t;
114
116typedef enum _pwm_output_state
117{
118 kPWM_HighState = 0,
119 kPWM_LowState,
120 kPWM_NormalState,
121 kPWM_InvertState,
122 kPWM_MaskState
123} pwm_output_state_t;
124
126typedef enum _pwm_init_source
127{
128 kPWM_Initialize_LocalSync = 0U,
129 kPWM_Initialize_MasterReload,
130 kPWM_Initialize_MasterSync,
131 kPWM_Initialize_ExtSync
132} pwm_init_source_t;
133
135typedef enum _pwm_load_frequency
136{
137 kPWM_LoadEveryOportunity = 0U,
138 kPWM_LoadEvery2Oportunity,
139 kPWM_LoadEvery3Oportunity,
140 kPWM_LoadEvery4Oportunity,
141 kPWM_LoadEvery5Oportunity,
142 kPWM_LoadEvery6Oportunity,
143 kPWM_LoadEvery7Oportunity,
144 kPWM_LoadEvery8Oportunity,
145 kPWM_LoadEvery9Oportunity,
146 kPWM_LoadEvery10Oportunity,
147 kPWM_LoadEvery11Oportunity,
148 kPWM_LoadEvery12Oportunity,
149 kPWM_LoadEvery13Oportunity,
150 kPWM_LoadEvery14Oportunity,
151 kPWM_LoadEvery15Oportunity,
152 kPWM_LoadEvery16Oportunity
153} pwm_load_frequency_t;
154
156typedef enum _pwm_fault_input
157{
158 kPWM_Fault_0 = 0U,
159 kPWM_Fault_1,
160 kPWM_Fault_2,
161 kPWM_Fault_3
162} pwm_fault_input_t;
163
165typedef enum _pwm_fault_disable
166{
167 kPWM_FaultDisable_0 = (1U << 0),
168 kPWM_FaultDisable_1 = (1U << 1),
169 kPWM_FaultDisable_2 = (1U << 2),
170 kPWM_FaultDisable_3 = (1U << 3)
171} pwm_fault_disable_t;
172
174typedef enum _pwm_fault_channels
175{
176 kPWM_faultchannel_0 = 0U,
177 kPWM_faultchannel_1
178} pwm_fault_channels_t;
179
181typedef enum _pwm_input_capture_edge
182{
183 kPWM_Disable = 0U,
184 kPWM_FallingEdge,
185 kPWM_RisingEdge,
186 kPWM_RiseAndFallEdge
187} pwm_input_capture_edge_t;
188
190typedef enum _pwm_force_signal
191{
192 kPWM_UsePwm = 0U,
193 kPWM_InvertedPwm,
194 kPWM_SoftwareControl,
195 kPWM_UseExternal
196} pwm_force_signal_t;
197
199typedef enum _pwm_chnl_pair_operation
200{
201 kPWM_Independent = 0U,
202 kPWM_ComplementaryPwmA,
203 kPWM_ComplementaryPwmB
204} pwm_chnl_pair_operation_t;
205
207typedef enum _pwm_register_reload
208{
209 kPWM_ReloadImmediate = 0U,
210 kPWM_ReloadPwmHalfCycle,
211 kPWM_ReloadPwmFullCycle,
212 kPWM_ReloadPwmHalfAndFullCycle
213} pwm_register_reload_t;
214
216typedef enum _pwm_fault_recovery_mode
217{
218 kPWM_NoRecovery = 0U,
219 kPWM_RecoverHalfCycle,
220 kPWM_RecoverFullCycle,
221 kPWM_RecoverHalfAndFullCycle
222} pwm_fault_recovery_mode_t;
223
225typedef enum _pwm_interrupt_enable
226{
227 kPWM_CompareVal0InterruptEnable = (1U << 0),
228 kPWM_CompareVal1InterruptEnable = (1U << 1),
229 kPWM_CompareVal2InterruptEnable = (1U << 2),
230 kPWM_CompareVal3InterruptEnable = (1U << 3),
231 kPWM_CompareVal4InterruptEnable = (1U << 4),
232 kPWM_CompareVal5InterruptEnable = (1U << 5),
233#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX
234 kPWM_CaptureX0InterruptEnable = (1U << 6),
235 kPWM_CaptureX1InterruptEnable = (1U << 7),
236#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX */
237#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB
238 kPWM_CaptureB0InterruptEnable = (1U << 8),
239 kPWM_CaptureB1InterruptEnable = (1U << 9),
240#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB */
241#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA
242 kPWM_CaptureA0InterruptEnable = (1U << 10),
243 kPWM_CaptureA1InterruptEnable = (1U << 11),
244#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA */
245 kPWM_ReloadInterruptEnable = (1U << 12),
246 kPWM_ReloadErrorInterruptEnable = (1U << 13),
247 kPWM_Fault0InterruptEnable = (1U << 16),
248 kPWM_Fault1InterruptEnable = (1U << 17),
249 kPWM_Fault2InterruptEnable = (1U << 18),
250 kPWM_Fault3InterruptEnable = (1U << 19)
251} pwm_interrupt_enable_t;
252
254typedef enum _pwm_status_flags
255{
256 kPWM_CompareVal0Flag = (1U << 0),
257 kPWM_CompareVal1Flag = (1U << 1),
258 kPWM_CompareVal2Flag = (1U << 2),
259 kPWM_CompareVal3Flag = (1U << 3),
260 kPWM_CompareVal4Flag = (1U << 4),
261 kPWM_CompareVal5Flag = (1U << 5),
262#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX
263 kPWM_CaptureX0Flag = (1U << 6),
264 kPWM_CaptureX1Flag = (1U << 7),
265#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX */
266#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB
267 kPWM_CaptureB0Flag = (1U << 8),
268 kPWM_CaptureB1Flag = (1U << 9),
269#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB */
270#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA
271 kPWM_CaptureA0Flag = (1U << 10),
272 kPWM_CaptureA1Flag = (1U << 11),
273#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA */
274 kPWM_ReloadFlag = (1U << 12),
275 kPWM_ReloadErrorFlag = (1U << 13),
276 kPWM_RegUpdatedFlag = (1U << 14),
277 kPWM_Fault0Flag = (1U << 16),
278 kPWM_Fault1Flag = (1U << 17),
279 kPWM_Fault2Flag = (1U << 18),
280 kPWM_Fault3Flag = (1U << 19)
281} pwm_status_flags_t;
282
284typedef enum _pwm_dma_enable
285{
286#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX
287 kPWM_CaptureX0DMAEnable = (1U << 0),
288 kPWM_CaptureX1DMAEnable = (1U << 1),
289#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX */
290#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB
291 kPWM_CaptureB0DMAEnable = (1U << 2),
292 kPWM_CaptureB1DMAEnable = (1U << 3),
293#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB */
294#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA
295 kPWM_CaptureA0DMAEnable = (1U << 4),
296 kPWM_CaptureA1DMAEnable = (1U << 5)
297#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA */
298} pwm_dma_enable_t;
299
301typedef enum _pwm_dma_source_select
302{
303 kPWM_DMARequestDisable = 0U,
304 kPWM_DMAWatermarksEnable,
305 kPWM_DMALocalSync,
306 kPWM_DMALocalReload
307} pwm_dma_source_select_t;
308
310typedef enum _pwm_watermark_control
311{
312 kPWM_FIFOWatermarksOR = 0U,
313 kPWM_FIFOWatermarksAND
314} pwm_watermark_control_t;
315
317typedef enum _pwm_mode
318{
319 kPWM_SignedCenterAligned = 0U,
320 kPWM_CenterAligned,
321 kPWM_SignedEdgeAligned,
322 kPWM_EdgeAligned
323} pwm_mode_t;
324
326typedef enum _pwm_level_select
327{
328 kPWM_HighTrue = 0U,
329 kPWM_LowTrue
330} pwm_level_select_t;
331
333typedef enum _pwm_fault_state
334{
335 kPWM_PwmFaultState0 =
336 0U,
337 kPWM_PwmFaultState1,
338 kPWM_PwmFaultState2,
339 kPWM_PwmFaultState3
340} pwm_fault_state_t;
341
343typedef enum _pwm_reload_source_select
344{
345 kPWM_LocalReload = 0U,
346 kPWM_MasterReload
347} pwm_reload_source_select_t;
348
350typedef enum _pwm_fault_clear
351{
352 kPWM_Automatic = 0U,
353 kPWM_ManualNormal,
354 kPWM_ManualSafety
355} pwm_fault_clear_t;
356
358typedef enum _pwm_module_control
359{
360 kPWM_Control_Module_0 = (1U << 0),
361 kPWM_Control_Module_1 = (1U << 1),
362 kPWM_Control_Module_2 = (1U << 2),
363 kPWM_Control_Module_3 = (1U << 3)
364} pwm_module_control_t;
365
367typedef struct _pwm_signal_param
368{
369 pwm_channels_t pwmChannel;
370 uint8_t dutyCyclePercent;
373 pwm_level_select_t level;
374 uint16_t deadtimeValue;
375 pwm_fault_state_t faultState;
376 bool pwmchannelenable;
377} pwm_signal_param_t;
378
388typedef struct _pwm_config
389{
390 bool enableDebugMode;
392#if !defined(FSL_FEATURE_PWM_HAS_NO_WAITEN) || (!FSL_FEATURE_PWM_HAS_NO_WAITEN)
393 bool enableWait;
395#endif /* FSL_FEATURE_PWM_HAS_NO_WAITEN */
396 pwm_init_source_t initializationControl;
397 pwm_clock_source_t clockSource;
398 pwm_clock_prescale_t prescale;
399 pwm_chnl_pair_operation_t pairOperation;
400 pwm_register_reload_t reloadLogic;
401 pwm_reload_source_select_t reloadSelect;
402 pwm_load_frequency_t reloadFrequency;
404 pwm_force_output_trigger_t forceTrigger;
405} pwm_config_t;
406
408typedef struct _pwm_fault_input_filter_param
409{
410 uint8_t faultFilterCount;
411 uint8_t faultFilterPeriod;
412 bool faultGlitchStretch;
414} pwm_fault_input_filter_param_t;
415
417typedef struct _pwm_fault_param
418{
419 pwm_fault_clear_t faultClearingMode;
420 bool faultLevel;
422 bool enableCombinationalPath;
424 pwm_fault_recovery_mode_t recoverMode;
425} pwm_fault_param_t;
426
430typedef struct _pwm_input_capture_param
431{
432 bool captureInputSel;
434 uint8_t edgeCompareValue;
435 pwm_input_capture_edge_t edge0;
436 pwm_input_capture_edge_t edge1;
437 bool enableOneShotCapture;
439 uint8_t fifoWatermark;
442} pwm_input_capture_param_t;
443
444/*******************************************************************************
445 * API
446 ******************************************************************************/
447
448#if defined(__cplusplus)
449extern "C" {
450#endif
451
468status_t PWM_Init(PWM_Type *base, pwm_submodule_t subModule, const pwm_config_t *config);
469
476void PWM_Deinit(PWM_Type *base, pwm_submodule_t subModule);
477
496void PWM_GetDefaultConfig(pwm_config_t *config);
497
525status_t PWM_SetupPwm(PWM_Type *base,
526 pwm_submodule_t subModule,
527 const pwm_signal_param_t *chnlParams,
528 uint8_t numOfChnls,
529 pwm_mode_t mode,
530 uint32_t pwmFreq_Hz,
531 uint32_t srcClock_Hz);
532
547status_t PWM_SetupPwmPhaseShift(PWM_Type *base,
548 pwm_submodule_t subModule,
549 pwm_channels_t pwmChannel,
550 uint32_t pwmFreq_Hz,
551 uint32_t srcClock_Hz,
552 uint8_t shiftvalue,
553 bool doSync);
554
570void PWM_UpdatePwmDutycycle(PWM_Type *base,
571 pwm_submodule_t subModule,
572 pwm_channels_t pwmSignal,
573 pwm_mode_t currPwmMode,
574 uint8_t dutyCyclePercent);
575
591void PWM_UpdatePwmDutycycleHighAccuracy(
592 PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmSignal, pwm_mode_t currPwmMode, uint16_t dutyCycle);
593
617void PWM_UpdatePwmPeriodAndDutycycle(PWM_Type *base,
618 pwm_submodule_t subModule,
619 pwm_channels_t pwmSignal,
620 pwm_mode_t currPwmMode,
621 uint16_t pulseCnt,
622 uint16_t dutyCycle);
623
637void PWM_SetupInputCapture(PWM_Type *base,
638 pwm_submodule_t subModule,
639 pwm_channels_t pwmChannel,
640 const pwm_input_capture_param_t *inputCaptureParams);
641
648void PWM_SetupFaultInputFilter(PWM_Type *base, const pwm_fault_input_filter_param_t *faultInputFilterParams);
649
659void PWM_SetupFaults(PWM_Type *base, pwm_fault_input_t faultNum, const pwm_fault_param_t *faultParams);
660
673void PWM_FaultDefaultConfig(pwm_fault_param_t *config);
674
686void PWM_SetupForceSignal(PWM_Type *base,
687 pwm_submodule_t subModule,
688 pwm_channels_t pwmChannel,
689 pwm_force_signal_t mode);
690
704void PWM_EnableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask);
705
714void PWM_DisableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask);
715
725uint32_t PWM_GetEnabledInterrupts(PWM_Type *base, pwm_submodule_t subModule);
726
741static inline void PWM_DMAFIFOWatermarkControl(PWM_Type *base,
742 pwm_submodule_t subModule,
743 pwm_watermark_control_t pwm_watermark_control)
744{
745 uint16_t reg = base->SM[subModule].DMAEN;
746 if (pwm_watermark_control == kPWM_FIFOWatermarksOR)
747 {
748 reg &= ~((uint16_t)PWM_DMAEN_FAND_MASK);
749 }
750 else
751 {
752 reg |= ((uint16_t)PWM_DMAEN_FAND_MASK);
753 }
754 base->SM[subModule].DMAEN = reg;
755}
756
764static inline void PWM_DMACaptureSourceSelect(PWM_Type *base,
765 pwm_submodule_t subModule,
766 pwm_dma_source_select_t pwm_dma_source_select)
767{
768 uint16_t reg = base->SM[subModule].DMAEN;
769
770 reg &= ~((uint16_t)PWM_DMAEN_CAPTDE_MASK);
771 reg |= (((uint16_t)pwm_dma_source_select << (uint16_t)PWM_DMAEN_CAPTDE_SHIFT) & (uint16_t)PWM_DMAEN_CAPTDE_MASK);
772
773 base->SM[subModule].DMAEN = reg;
774}
775
785static inline void PWM_EnableDMACapture(PWM_Type *base, pwm_submodule_t subModule, uint16_t mask, bool activate)
786{
787 uint16_t reg = base->SM[subModule].DMAEN;
788 if (activate)
789 {
790 reg |= (uint16_t)(mask);
791 }
792 else
793 {
794 reg &= ~((uint16_t)(mask));
795 }
796 base->SM[subModule].DMAEN = reg;
797}
798
806static inline void PWM_EnableDMAWrite(PWM_Type *base, pwm_submodule_t subModule, bool activate)
807{
808 uint16_t reg = base->SM[subModule].DMAEN;
809 if (activate)
810 {
811 reg |= ((uint16_t)PWM_DMAEN_VALDE_MASK);
812 }
813 else
814 {
815 reg &= ~((uint16_t)PWM_DMAEN_VALDE_MASK);
816 }
817 base->SM[subModule].DMAEN = reg;
818}
819
836uint32_t PWM_GetStatusFlags(PWM_Type *base, pwm_submodule_t subModule);
837
846void PWM_ClearStatusFlags(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask);
847
865static inline void PWM_StartTimer(PWM_Type *base, uint8_t subModulesToStart)
866{
867 base->MCTRL |= PWM_MCTRL_RUN(subModulesToStart);
868}
869
880static inline void PWM_StopTimer(PWM_Type *base, uint8_t subModulesToStop)
881{
882 base->MCTRL &= ~(PWM_MCTRL_RUN(subModulesToStop));
883}
884
900static inline void PWM_SetVALxValue(PWM_Type *base,
901 pwm_submodule_t subModule,
902 pwm_value_register_t valueRegister,
903 uint16_t value)
904{
905 switch (valueRegister)
906 {
907 case kPWM_ValueRegister_0:
908 base->SM[subModule].VAL0 = value;
909 break;
910 case kPWM_ValueRegister_1:
911 base->SM[subModule].VAL1 = value;
912 break;
913 case kPWM_ValueRegister_2:
914 base->SM[subModule].VAL2 = value;
915 break;
916 case kPWM_ValueRegister_3:
917 base->SM[subModule].VAL3 = value;
918 break;
919 case kPWM_ValueRegister_4:
920 base->SM[subModule].VAL4 = value;
921 break;
922 case kPWM_ValueRegister_5:
923 base->SM[subModule].VAL5 = value;
924 break;
925 default:
926 assert(false);
927 break;
928 }
929}
930
939static inline uint16_t PWM_GetVALxValue(PWM_Type *base, pwm_submodule_t subModule, pwm_value_register_t valueRegister)
940{
941 uint16_t temp = 0U;
942
943 switch (valueRegister)
944 {
945 case kPWM_ValueRegister_0:
946 temp = base->SM[subModule].VAL0;
947 break;
948 case kPWM_ValueRegister_1:
949 temp = base->SM[subModule].VAL1;
950 break;
951 case kPWM_ValueRegister_2:
952 temp = base->SM[subModule].VAL2;
953 break;
954 case kPWM_ValueRegister_3:
955 temp = base->SM[subModule].VAL3;
956 break;
957 case kPWM_ValueRegister_4:
958 temp = base->SM[subModule].VAL4;
959 break;
960 case kPWM_ValueRegister_5:
961 temp = base->SM[subModule].VAL5;
962 break;
963 default:
964 assert(false);
965 break;
966 }
967
968 return temp;
969}
970
983static inline void PWM_OutputTriggerEnable(PWM_Type *base,
984 pwm_submodule_t subModule,
985 pwm_value_register_t valueRegister,
986 bool activate)
987{
988 if (activate)
989 {
990 base->SM[subModule].TCTRL |= ((uint16_t)1U << (uint16_t)valueRegister);
991 }
992 else
993 {
994 base->SM[subModule].TCTRL &= ~((uint16_t)1U << (uint16_t)valueRegister);
995 }
996}
997
1008static inline void PWM_ActivateOutputTrigger(PWM_Type *base, pwm_submodule_t subModule, uint16_t valueRegisterMask)
1009{
1010 base->SM[subModule].TCTRL |= (PWM_TCTRL_OUT_TRIG_EN_MASK & (valueRegisterMask));
1011}
1012
1023static inline void PWM_DeactivateOutputTrigger(PWM_Type *base, pwm_submodule_t subModule, uint16_t valueRegisterMask)
1024{
1025 base->SM[subModule].TCTRL &= ~(PWM_TCTRL_OUT_TRIG_EN_MASK & (valueRegisterMask));
1026}
1027
1039static inline void PWM_SetupSwCtrlOut(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, bool value)
1040{
1041 if (value)
1042 {
1043 base->SWCOUT |=
1044 ((uint16_t)1U << (((uint16_t)subModule * (uint16_t)PWM_SUBMODULE_SWCONTROL_WIDTH) + (uint16_t)pwmChannel));
1045 }
1046 else
1047 {
1048 base->SWCOUT &=
1049 ~((uint16_t)1U << (((uint16_t)subModule * (uint16_t)PWM_SUBMODULE_SWCONTROL_WIDTH) + (uint16_t)pwmChannel));
1050 }
1051}
1052
1066static inline void PWM_SetPwmLdok(PWM_Type *base, uint8_t subModulesToUpdate, bool value)
1067{
1068 if (value)
1069 {
1070 base->MCTRL |= PWM_MCTRL_LDOK(subModulesToUpdate);
1071 }
1072 else
1073 {
1074 base->MCTRL |= PWM_MCTRL_CLDOK(subModulesToUpdate);
1075 }
1076}
1077
1091static inline void PWM_SetPwmFaultState(PWM_Type *base,
1092 pwm_submodule_t subModule,
1093 pwm_channels_t pwmChannel,
1094 pwm_fault_state_t faultState)
1095{
1096 uint16_t reg = base->SM[subModule].OCTRL;
1097 switch (pwmChannel)
1098 {
1099 case kPWM_PwmA:
1100 reg &= ~((uint16_t)PWM_OCTRL_PWMAFS_MASK);
1101 reg |= (((uint16_t)faultState << (uint16_t)PWM_OCTRL_PWMAFS_SHIFT) & (uint16_t)PWM_OCTRL_PWMAFS_MASK);
1102 break;
1103 case kPWM_PwmB:
1104 reg &= ~((uint16_t)PWM_OCTRL_PWMBFS_MASK);
1105 reg |= (((uint16_t)faultState << (uint16_t)PWM_OCTRL_PWMBFS_SHIFT) & (uint16_t)PWM_OCTRL_PWMBFS_MASK);
1106 break;
1107 case kPWM_PwmX:
1108 reg &= ~((uint16_t)PWM_OCTRL_PWMXFS_MASK);
1109 reg |= (((uint16_t)faultState << (uint16_t)PWM_OCTRL_PWMXFS_SHIFT) & (uint16_t)PWM_OCTRL_PWMXFS_MASK);
1110 break;
1111 default:
1112 assert(false);
1113 break;
1114 }
1115 base->SM[subModule].OCTRL = reg;
1116}
1117
1133static inline void PWM_SetupFaultDisableMap(PWM_Type *base,
1134 pwm_submodule_t subModule,
1135 pwm_channels_t pwmChannel,
1136 pwm_fault_channels_t pwm_fault_channels,
1137 uint16_t value)
1138{
1139 uint16_t reg = base->SM[subModule].DISMAP[pwm_fault_channels];
1140 switch (pwmChannel)
1141 {
1142 case kPWM_PwmA:
1143 reg &= ~((uint16_t)PWM_DISMAP_DIS0A_MASK);
1144 reg |= (((uint16_t)(value) << (uint16_t)PWM_DISMAP_DIS0A_SHIFT) & (uint16_t)PWM_DISMAP_DIS0A_MASK);
1145 break;
1146 case kPWM_PwmB:
1147 reg &= ~((uint16_t)PWM_DISMAP_DIS0B_MASK);
1148 reg |= (((uint16_t)(value) << (uint16_t)PWM_DISMAP_DIS0B_SHIFT) & (uint16_t)PWM_DISMAP_DIS0B_MASK);
1149 break;
1150 case kPWM_PwmX:
1151 reg &= ~((uint16_t)PWM_DISMAP_DIS0X_MASK);
1152 reg |= (((uint16_t)(value) << (uint16_t)PWM_DISMAP_DIS0X_SHIFT) & (uint16_t)PWM_DISMAP_DIS0X_MASK);
1153 break;
1154 default:
1155 assert(false);
1156 break;
1157 }
1158 base->SM[subModule].DISMAP[pwm_fault_channels] = reg;
1159}
1160
1170static inline void PWM_OutputEnable(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule)
1171{
1172 /* Set PWM output */
1173 switch (pwmChannel)
1174 {
1175 case kPWM_PwmA:
1176 base->OUTEN |= ((uint16_t)1U << ((uint16_t)PWM_OUTEN_PWMA_EN_SHIFT + (uint16_t)subModule));
1177 break;
1178 case kPWM_PwmB:
1179 base->OUTEN |= ((uint16_t)1U << ((uint16_t)PWM_OUTEN_PWMB_EN_SHIFT + (uint16_t)subModule));
1180 break;
1181 case kPWM_PwmX:
1182 base->OUTEN |= ((uint16_t)1U << ((uint16_t)PWM_OUTEN_PWMX_EN_SHIFT + (uint16_t)subModule));
1183 break;
1184 default:
1185 assert(false);
1186 break;
1187 }
1188}
1189
1199static inline void PWM_OutputDisable(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule)
1200{
1201 switch (pwmChannel)
1202 {
1203 case kPWM_PwmA:
1204 base->OUTEN &= ~((uint16_t)1U << ((uint16_t)PWM_OUTEN_PWMA_EN_SHIFT + (uint16_t)subModule));
1205 break;
1206 case kPWM_PwmB:
1207 base->OUTEN &= ~((uint16_t)1U << ((uint16_t)PWM_OUTEN_PWMB_EN_SHIFT + (uint16_t)subModule));
1208 break;
1209 case kPWM_PwmX:
1210 base->OUTEN &= ~((uint16_t)1U << ((uint16_t)PWM_OUTEN_PWMX_EN_SHIFT + (uint16_t)subModule));
1211 break;
1212 default:
1213 assert(false);
1214 break;
1215 }
1216}
1217
1227uint8_t PWM_GetPwmChannelState(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel);
1228
1241status_t PWM_SetOutputToIdle(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule, bool idleStatus);
1242
1250void PWM_SetClockMode(PWM_Type *base, pwm_submodule_t subModule, pwm_clock_prescale_t prescaler);
1251
1261void PWM_SetPwmForceOutputToZero(PWM_Type *base,
1262 pwm_submodule_t subModule,
1263 pwm_channels_t pwmChannel,
1264 bool forcetozero);
1265
1274void PWM_SetChannelOutput(PWM_Type *base,
1275 pwm_submodule_t subModule,
1276 pwm_channels_t pwmChannel,
1277 pwm_output_state_t outputstate);
1278
1279#if defined(FSL_FEATURE_PWM_HAS_PHASE_DELAY) && FSL_FEATURE_PWM_HAS_PHASE_DELAY
1291status_t PWM_SetPhaseDelay(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule, uint16_t delayCycles);
1292#endif
1293
1294#if defined(FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE) && FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE
1303static inline void PWM_SetFilterSampleCount(PWM_Type *base,
1304 pwm_channels_t pwmChannel,
1305 pwm_submodule_t subModule,
1306 uint8_t filterSampleCount)
1307{
1308 switch(pwmChannel)
1309 {
1310#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA
1311 case kPWM_PwmA:
1312 base->SM[subModule].CAPTFILTA &= ~((uint16_t)PWM_CAPTFILTA_CAPTA_FILT_CNT_MASK);
1313 base->SM[subModule].CAPTFILTA |= PWM_CAPTFILTA_CAPTA_FILT_CNT(filterSampleCount);
1314 break;
1315#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA */
1316#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB
1317 case kPWM_PwmB:
1318 base->SM[subModule].CAPTFILTB &= ~((uint16_t)PWM_CAPTFILTB_CAPTB_FILT_CNT_MASK);
1319 base->SM[subModule].CAPTFILTB |= PWM_CAPTFILTB_CAPTB_FILT_CNT(filterSampleCount);
1320 break;
1321#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB */
1322#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX
1323 case kPWM_PwmX:
1324 base->SM[subModule].CAPTFILTX &= ~((uint16_t)PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK);
1325 base->SM[subModule].CAPTFILTX |= PWM_CAPTFILTX_CAPTX_FILT_CNT(filterSampleCount);
1326 break;
1327#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX */
1328 default:
1329 assert(false);
1330 break;
1331 }
1332}
1333
1342static inline void PWM_SetFilterSamplePeriod(PWM_Type *base,
1343 pwm_channels_t pwmChannel,
1344 pwm_submodule_t subModule,
1345 uint8_t filterSamplePeriod)
1346{
1347 switch(pwmChannel)
1348 {
1349#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA
1350 case kPWM_PwmA:
1351 base->SM[subModule].CAPTFILTA &= ~((uint16_t)PWM_CAPTFILTA_CAPTA_FILT_PER_MASK);
1352 base->SM[subModule].CAPTFILTA |= PWM_CAPTFILTA_CAPTA_FILT_PER(filterSamplePeriod);
1353 break;
1354#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA */
1355#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB
1356 case kPWM_PwmB:
1357 base->SM[subModule].CAPTFILTB &= ~((uint16_t)PWM_CAPTFILTB_CAPTB_FILT_PER_MASK);
1358 base->SM[subModule].CAPTFILTB |= PWM_CAPTFILTB_CAPTB_FILT_PER(filterSamplePeriod);
1359 break;
1360#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB */
1361#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX
1362 case kPWM_PwmX:
1363 base->SM[subModule].CAPTFILTX &= ~((uint16_t)PWM_CAPTFILTX_CAPTX_FILT_PER_MASK);
1364 base->SM[subModule].CAPTFILTX |= PWM_CAPTFILTX_CAPTX_FILT_PER(filterSamplePeriod);
1365 break;
1366#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX */
1367 default:
1368 assert(false);
1369 break;
1370 }
1371}
1372#endif
1373
1374#if defined(__cplusplus)
1375}
1376#endif
1377
1380#endif /* FSL_PWM_H_ */
1381
1382#endif // #ifndef DOXYGEN_SHOULD_SKIP_THIS
fsl_common.h
status_t
int32_t status_t
Type used for all status and error return values.
Definition fsl_common.h:228