NetBurner 3.5.6
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MOD5441x Rapid GPIO

Rapid GPIO (RGPIO) Example

Overview

This example demonstrates the high-speed Rapid GPIO functionality unique to the NetBurner MOD5441X platform. The application showcases three different methods to generate extremely fast GPIO pulses, achieving toggle rates up to 62.5 MHz (16ns edge-to-edge timing) using the MCF54415's dedicated Rapid GPIO module connected directly to the processor's local bus.

Supported Platform

  • MOD5441X - MOD54415/MOD54417 core modules only

Hardware Requirements

Essential Components

  • MOD5441X core module - Hardware with MCF54415/MCF54417 processor
  • High-speed oscilloscope - Bandwidth >100MHz recommended for timing measurements
  • High-frequency probe - With very short ground connection (<1 inch)
  • **Connection point** - Access to module pin J2.37

Signal Output Location

  • **Primary test pin**: J2.37 (RGPIO_0 signal)
  • **Processor pin**: N11 (OW_DAT/DACK0 alternate functions)
  • **Ground reference**: Any nearby ground pin on J2 connector

Oscilloscope Setup Requirements

Probe Settings:
- Bandwidth: >200 MHz (for 16ns pulse measurement)
- Coupling: DC
- Ground lead: <1 inch length (critical for accuracy)
- Probe impedance: 10:1 recommended
Trigger Settings:
- Mode: Edge trigger on rising edge
- Level: 1.65V (mid-point of 3.3V logic)
- Time base: 50ns/div (for initial setup)

Features

Rapid GPIO Module Capabilities

  • **16-bit high-speed GPIO** - Connected to processor's 32-bit local bus
  • **Zero wait-state response** - Single data phase cycle completion
  • **Multiple access sizes** - Byte, word, and longword operations supported
  • **Direct register access** - Set, clear, and toggle operations without read-modify-write
  • **Maximum performance** - 1.5-3.5x faster than standard peripheral bus GPIO

Three Performance Implementation Methods

Method 1: Pure Assembly Code (Fastest - 16ns)

  • **Direct register addressing** - Assembly language register manipulation
  • **Unrolled loops** - 50 consecutive toggle operations
  • **Critical section protection** - Interrupt-free execution
  • **Performance**: 62.5 MHz toggle rate

Method 2: Assembly + C Hybrid (Medium - 68ns)

  • **Assembly register setup** - Optimized register addressing
  • **C loop control** - Standard loop structure with assembly toggle
  • **Cache considerations** - NOP instruction for consistent timing
  • **Performance**: ~14.7 MHz toggle rate

Method 3: Pure C Code (Slowest - 94ns)

  • **C pointer access** - Volatile pointer-based register access
  • **Loop-based control** - Standard for-loop implementation
  • Compiler optimization - Relies on compiler efficiency
  • Performance: ~10.6 MHz toggle rate

RGPIO Pin Mapping

RGPIO Bit Module Pin Processor Pin Primary Function Alternate Function
RGPIO_0 J2.37 N11 GPIO OW_DAT/DACK0
RGPIO_1 J2.32 G13 GPIO T3IN/PWM_EXTA3
RGPIO_2 J2.33 H14 GPIO T2IN/PWM_EXTA2
RGPIO_3 J2.34 H13 GPIO T1IN/PWM_EXTA1
RGPIO_4 J2.36 H15 GPIO T0IN/PWM_EXTA0
RGPIO_5 J2.29 E13 GPIO UART0_CTS
RGPIO_6 J2.38 D10 GPIO UART1_RTS
RGPIO_7 J2.24 C10 GPIO UART1_CTS
RGPIO_8 J2.23 B11 GPIO UART0_RTS

Technical Implementation

RGPIO Module Architecture

Memory-Mapped Register Layout

Base Address: 0x8C000000 (RGPIO_BAR)
Register Offsets (16-bit word access):
+0x00: Direction Register (RGPIO_DIR) - Input/Output control
+0x02: Data Register (RGPIO_DAT) - Pin state read/write
+0x04: Enable Register (RGPIO_ENB) - Pin enable control
+0x06: Clear Register (RGPIO_CLR) - Atomic bit clear
+0x0A: Set Register (RGPIO_SET) - Atomic bit set
+0x0E: Toggle Register (RGPIO_TOG) - Atomic bit toggle
read
int read(int fd, char *buf, int nbytes)
Read data from a file descriptor (fd).
write
int write(int fd, const char *buf, int nbytes)
Write data to the stream associated with a file descriptor (fd). Can be used to write data to stdio,...

Register Bit Mapping

Bit Position: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGPIO Signal: - - - - - - - 8 7 6 5 4 3 2 1 0
Module Pin: - - - - - - - 23 24 38 29 36 34 33 32 37

Processor Setup Requirements

RGPIO Module Activation

// Enable RGPIO module access via control register
asm(" move.l #0x8C000035,%d0"); // Base address + enable bit
asm(" movec %d0,#0x009"); // Write to control register

Pin Configuration Sequence

volatile uint16_t *pRGPIO_BAR = (uint16_t *)RGPIO_BAR;
pRGPIO_BAR[RGPIO_DIR] = RGPIO_0; // Configure as output
pRGPIO_BAR[RGPIO_ENB] = RGPIO_0; // Enable pin functionality

Maximum Slew Rate Configuration

// Set all relevant slew rate registers to maximum frequency
sim1.gpio.srcr_dspiow = 0x33; // DSPI0 & One-Wire pins
sim1.gpio.srcr_timer |= 0xFF; // Timer pins
sim1.gpio.srcr_uart |= 0x0F; // UART0/1 pins
sim1.gpio.srcr_sdhc |= 0x03; // SDHC pins

Performance Implementation Details

Method 1: Pure Assembly (16ns edge-to-edge)

void Pulse50() {
USER_ENTER_CRITICAL();
asm(" move.l #0x8C00000E,%d0"); // Toggle register address
asm(" move.l %d0,%a5"); // Load into address register
asm(" move.l #0x01,%d5"); // RGPIO_0 bit mask
// Unrolled 50 toggle operations
asm(" move.w %d5,%a5@"); // Toggle #1
asm(" move.w %d5,%a5@"); // Toggle #2
// ... [48 more identical operations]
USER_EXIT_CRITICAL();
}

Method 2: Assembly + C Hybrid (68ns edge-to-edge)

void Pulse50LoopAsm() {
USER_ENTER_CRITICAL();
asm(" move.l #0x8C00000E,%d0");
asm(" move.l %d0,%a5");
asm(" move.l #0x01,%d5");
for (int i = 0; i < 50; i++) {
asm(" nop"); // Cache consistency
asm(" move.w %d5,%a5@"); // Single toggle
}
USER_EXIT_CRITICAL();
}

Method 3: Pure C Code (94ns edge-to-edge)

void Pulse50LoopC() {
volatile uint16_t *pRGPIO_BAR = (uint16_t *)RGPIO_BAR;
USER_ENTER_CRITICAL();
for (int i = 0; i < 50; i++) {
asm(" nop"); // Cache consistency
pRGPIO_BAR[RGPIO_TOG] = RGPIO_0;
}
USER_EXIT_CRITICAL();
}

Usage Instructions

Setup Process

  1. Hardware connections
    • Connect oscilloscope probe to J2.37 on MOD5441X
    • Use very short ground connection (<1 inch) to nearby J2 ground pin
    • Configure oscilloscope for high-frequency measurements
  2. **Build and deploy**
    make clean
    make
    make load DEVICE_IP=<your_device_ip>
  3. Initial signal verification
    • Application generates slow GPIO toggles during startup
    • Use these to verify correct pin connection
    • Look for clear logic level transitions (0V to 3.3V)

Operation and Measurement

Console Output

Running Rapid GPIO example on Pin J2-37
RB at [8C000000] = 0001 // Direction register
RB at [8C000002] = 0000 // Data register
RB at [8C000004] = 0001 // Enable register
RB at [8C000006] = 0000 // Clear register
RB at [8C00000A] = 0000 // Set register
RB at [8C00000E] = 0000 // Toggle register

Oscilloscope Measurements

Method 1 (Assembly): Expected Waveform**

Timing: 16ns edge-to-edge
Frequency: 62.5 MHz for 800ns burst duration
Pattern: 50 pulses every 1 second
Amplitude: 0V to 3.3V logic levels
Rise time: <2ns (limited by probe/scope bandwidth)
time
time_t time(time_t *pt)
Gets the current system GMT time.

Method 2 (Hybrid): Expected Waveform**

Timing: 68ns edge-to-edge
Frequency: ~14.7 MHz for 3.4us burst duration
Pattern: 50 pulses every 1 second
Amplitude: 0V to 3.3V logic levels

Method 3 (C Code): Expected Waveform**

Timing: 94ns edge-to-edge
Frequency: ~10.6 MHz for 4.7us burst duration
Pattern: 50 pulses every 1 second
Amplitude: 0V to 3.3V logic levels

Performance Measurement Techniques

Oscilloscope Settings for 16ns Pulses

Time Base: 10ns/div (to see individual edges)
Vertical: 500mV/div (for 3.3V logic)
Trigger: Edge, rising, 1.65V level
Bandwidth: Maximum available (>200MHz)
Sampling Rate: >1GSa/s minimum

Measurement Procedures

  1. Single pulse timing: Measure rising edge to rising edge
  2. Burst duration: Time for complete 50-pulse sequence
  3. Amplitude verification: Confirm 0V to 3.3V swings
  4. Rise/fall times: Limited by oscilloscope/probe bandwidth
  5. Jitter analysis: Use persistence display mode

Performance Comparison

Speed Analysis

Method Implementation Edge Timing Frequency Burst Duration
Assembly Unrolled ASM 16ns 62.5 MHz 800ns
Hybrid ASM + C Loop 68ns 14.7 MHz 3.4us
C Code Volatile Pointer 94ns 10.6 MHz 4.7us
Standard GPIO Pin Class >1us <1 MHz >50us

Performance Factors

Speed Advantages of Assembly Method

  • No loop overhead - Unrolled operations eliminate branch instructions
  • Register pre-loading - Address and data values loaded once
  • No compiler optimization - Direct control over instruction sequence
  • Critical section - No interrupt latency during pulse generation

Hybrid Method Considerations

  • Loop overhead - Branch instruction every cycle adds ~52ns
  • Register reuse - Address register loaded once, data register per cycle
  • Cache effects - NOP instruction ensures consistent timing
  • Interrupt protection - Critical section maintains timing accuracy

C Method Limitations

  • Pointer dereferencing - Additional memory access overhead
  • Compiler optimization - Dependent on compiler efficiency
  • Volatile access - Required for memory-mapped registers
  • Loop processing - Standard C loop with increment and comparison

Troubleshooting

Common Measurement Issues

No Signal Observed

Symptoms**: Flat line on oscilloscope Solutions**:

  • Verify connection to correct pin (J2.37)
  • Check ground connection quality (<1 inch)
  • Confirm oscilloscope trigger settings
  • Verify probe compensation
  • Check for proper module power-up

Incorrect Timing Measurements

Symptoms**: Wrong edge-to-edge timing values Solutions**:

  • Increase oscilloscope bandwidth setting
  • Reduce time base to 5-10ns/div
  • Verify probe impedance setting (10:1)
  • Check for ground loop issues
  • Use shortest possible probe ground lead

Inconsistent Pulse Timing

Symptoms**: Variable pulse spacing Solutions**:

  • Verify critical section implementation
  • Check for interrupt activity during measurement
  • Use oscilloscope infinite persistence mode
  • Increase sample rate on oscilloscope
  • Verify stable power supply to module

Amplitude Issues

Symptoms**: Wrong voltage levels Solutions**:

  • Confirm 3.3V logic levels (not 5V)
  • Check probe attenuation setting
  • Verify oscilloscope vertical scale
  • Test with known reference voltage
  • Check for probe loading effects

Debug Procedures

Register Verification

// Display RGPIO register contents
volatile uint16_t *pRGPIO_BAR = (uint16_t *)RGPIO_BAR;
for (int i = 0; i < 8; i++) {
printf("RGPIO[%d] at [%p] = %04X\n", i, pRGPIO_BAR + i, pRGPIO_BAR[i]);
}

Pin Function Verification

// Use slow GPIO to verify correct pin
J2[37].function(PINJ2_37_GPIO);
for (int i = 0; i < 10; i++) {
J2[37] = 1;
OSTimeDly(TICKS_PER_SECOND/10); // 100ms
J2[37] = 0;
OSTimeDly(TICKS_PER_SECOND/10); // 100ms
}
TICKS_PER_SECOND
#define TICKS_PER_SECOND
System clock ticks per second.
Definition constants.h:49

RGPIO Module Status Check

// Verify RGPIO module is properly enabled
printf("RGPIO Direction: 0x%04X\n", pRGPIO_BAR[RGPIO_DIR]);
printf("RGPIO Enable: 0x%04X\n", pRGPIO_BAR[RGPIO_ENB]);
printf("RGPIO Data: 0x%04X\n", pRGPIO_BAR[RGPIO_DAT]);

Learning Objectives

This example demonstrates:

  • High-speed GPIO techniques - Achieving maximum toggle rates
  • Assembly language integration - Inline assembly with C/C++
  • Memory-mapped register access - Direct hardware manipulation
  • Performance optimization - Different implementation approaches
  • Critical section usage - Interrupt-free timing-critical code
  • Hardware-specific features - Platform-unique capabilities

Related Examples

For additional GPIO learning, see:

  • Basic GPIO examples for standard pin control
  • Timer examples for precise timing generation
  • Interrupt examples for GPIO event handling
  • PWM examples for controlled waveform generation