External IRQ 7 (Non-Maskable Interrupt) Example

Overview

This example demonstrates how to configure and use External IRQ 7 as a non-maskable interrupt on NetBurner MCF5441X platforms. The application shows both C/C++ and assembly language interrupt service routine (ISR) implementations, providing a complete example of level 7 interrupt handling.

Supported Platforms

MOD5441X - MOD54415 development module
NANO54415 - Nano54415 development module

Both platforms use the MCF54415 processor with identical interrupt functionality.

Hardware Requirements

Physical Connection Required

This example requires a jumper wire connection between a GPIO pin and the IRQ 7 input pin to trigger the interrupt:

MOD5441X Platform

GPIO Signal Pin: J2.33 ----[JUMPER]---- IRQ 7 Input: J2.48

NANO54415 Platform (Dev Board Rev 1.3)

GPIO Signal: Pin 12 (P2.12) ----[JUMPER]---- IRQ 7: Pin 9 (P1.9)

Pin Configuration Summary

Platform	GPIO Signal Pin	IRQ 7 Input Pin
MOD5441X	J2.33	J2.48
NANO54415	Pin 12 (P2.12)	Pin 9 (P1.9)

Features

Interrupt Service Routine (ISR) Implementation

Mixed C/C++ and Assembly - Demonstrates both programming approaches
Register preservation - Complete context saving and restoration
Interrupt flag clearing - Proper interrupt acknowledgment
Counter mechanism - Tracks number of interrupts received

GPIO Control

Signal generation - Uses GPIO pin to trigger interrupts
Edge detection - Configurable for falling, rising, or both edges
Manual triggering - Interactive testing via serial console

Web Interface

Built-in web server - Provides web-based interface
Status display - Shows interrupt counter and system information

Code Architecture

Main Components

UserMain() - Application entry point and main loop
ConfigureIrq7() - IRQ 7 configuration function
NMI_ASM_Part() - Assembly language ISR entry point
NMI_C_Part() - C/C++ interrupt handler
Function_Holder() - Assembly code container function

Interrupt Flow

Hardware IRQ 7 Signal
         |
         v
NMI_ASM_Part() (Assembly)
    - Save processor state
    - Mask interrupts (SR = 0x2700)
    - Save all registers (D0-D7, A0-A6)
         |
         v
NMI_C_Part() (C/C++)
    - Clear interrupt flag (EPFR)
    - Reset GPIO trigger pin
    - Increment counter
         |
         v
NMI_ASM_Part() (Assembly continued)
    - Restore all registers
    - Restore processor state
    - Return from exception (RTE)

Register Usage

Assembly Code Register Operations

move.w #0x2700,%sr              ; Set interrupt mask to level 7
lea -60(%a7),%a7                ; Allocate 60 bytes on stack
movem.l %d0-%d7/%a0-%a6,(%a7)   ; Save all general registers
jsr NMI_C_Part                  ; Call C handler
movem.l (%a7),%d0-%d7/%a0-%a6   ; Restore all registers
lea 60(%a7),%a7                 ; Restore stack pointer
rte                             ; Return from exception

Usage Instructions

Setup Process

Build the application
Deploy to device
Install jumper wire
- Connect GPIO signal pin to IRQ 7 input pin according to platform specifications above
Connect serial terminal
- Use MTTTY, PuTTY, or similar terminal program
- Configure for 115200 baud, 8-N-1

Interactive Operation

Start the application - Device will display initialization messages
Press any key - Triggers a falling edge interrupt on IRQ 7
View results - Interrupt counter increments and displays current count
Repeat testing - Continue pressing keys to generate more interrupts

Example Console Output

MOD5441x IRQ 7 application started
Configuring J2-33 as GPIO
Configuring J2-48 as IRQ7
Hit any key to generate an IRQ
[User presses key]
Irq Count: 1
Hit any key to generate an IRQ
[User presses key]
Irq Count: 2
Hit any key to generate an IRQ

Web Interface

Access the web interface at http://<device_ip>/ to view:

Welcome page with NetBurner branding
System status information
Interrupt counter display

Technical Details

Interrupt Configuration

EPORT (External Port) Registers

EPPAR - Pin assignment register (edge/level configuration)
EPDDR - Data direction register (input/output configuration)
EPIER - Interrupt enable register
EPFR - Flag register (interrupt status)

Edge Detection Settings (EPPAR Register)

Level-sensitive (not used in this example)
Rising edge triggered
Falling edge triggered (used in this example)
Both edges triggered

Interrupt Controller Configuration

Vector: 7 (IRQ 7 source)
Level: 7 (highest priority, non-maskable)
Controller: 0 (primary interrupt controller)

Memory Layout

Stack Frame During Interrupt

Stack Layout (60 bytes total):
+--------+--------+--------+--------+
|   D0   |   D1   |   D2   |   D3   |  Bytes 0-15
+--------+--------+--------+--------+
|   D4   |   D5   |   D6   |   D7   |  Bytes 16-31
+--------+--------+--------+--------+
|   A0   |   A1   |   A2   |   A3   |  Bytes 32-47
+--------+--------+--------+--------+
|   A4   |   A5   |   A6   |  ---   |  Bytes 48-59
+--------+--------+--------+--------+

Important Considerations

IRQ 7 Characteristics

Non-maskable - Cannot be disabled by interrupt mask bits
Highest priority - Preempts all other interrupts
Critical timing - Must be handled quickly to avoid system issues

Development Notes

Register preservation is critical in assembly ISR
Stack management must be precise (60-byte allocation)
Interrupt flag clearing prevents continuous triggering
GPIO reset ensures clean signal transitions

Troubleshooting

Common Issues

No interrupts - Check jumper wire connection
Continuous interrupts - Verify interrupt flag clearing in EPFR
System instability - Check assembly code register preservation
Build errors - Ensure SUPPORTED_PLATFORMS matches your hardware

Debug Steps

Verify jumper wire connections match platform specifications
Check serial console output for configuration messages
Confirm GPIO pin functions are set correctly
Test with multimeter to verify signal transitions

Learning Objectives

This example teaches:

Mixed-language programming - C/C++ with assembly integration
Interrupt handling - Non-maskable interrupt service routines
Hardware interface - GPIO and external interrupt configuration
Register programming - Direct MCF54415 register manipulation
Real-time concepts - Critical timing and context preservation

Build Configuration

Makefile Settings

Platforms: NANO54415, MOD5441X
Web content: Auto-generated from html/ directory
Compile: Standard NetBurner C++ compilation

Dependencies

NetBurner NNDK (Network Development Kit)
Compatible hardware platform
Serial terminal program for interaction

License and Support

This example is provided under NetBurner's standard licensing terms. For technical support:

Review the hardware platform documentation
Consult the MCF54415 processor reference manual
Contact NetBurner technical support for specific issues

Related Examples

For additional interrupt and GPIO examples, see:

Basic GPIO examples for pin control
Timer interrupt examples for periodic processing
External interrupt examples for maskable interrupts (IRQ 1-6)