Developer/html/etm_8h_source.html

#define ETM_TRCPRGCTLR_EN_Pos 0U

#define ETM_TRCPRGCTLR_EN_Msk (0x1UL << ETM_TRCPRGCTLR_EN_Pos)

#define ETM_TRCPRGCTLR_EN(_mrval) ((_mrval << ETM_TRCPRGCTLR_EN_Pos) & ETM_TRCPRGCTLR_EN_Msk)


#define ETM_TRCPROCSELR_PROCSEL_Pos 0U

#define ETM_TRCPROCSELR_PROCSEL_Msk (0x3UL << ETM_TRCPROCSELR_PROCSEL_Pos)

#define ETM_TRCPROCSELR_PROCSEL(_mrval) ((_mrval << ETM_TRCPROCSELR_PROCSEL_Pos) & ETM_TRCPROCSELR_PROCSEL_Msk)


#define ETM_TRCSTATR_IDLE_Pos 0U

#define ETM_TRCSTATR_IDLE_Msk (0x1UL << ETM_TRCSTATR_IDLE_Pos)

#define ETM_TRCSTATR_IDLE(_mrval) ((_mrval << ETM_TRCSTATR_IDLE_Pos) & ETM_TRCSTATR_IDLE_Msk)


#define ETM_TRCSTATR_PMSTABLE_Pos 1U

#define ETM_TRCSTATR_PMSTABLE_Msk (0x1UL << ETM_TRCSTATR_PMSTABLE_Pos)

#define ETM_TRCSTATR_PMSTABLE(_mrval) ((_mrval << ETM_TRCSTATR_PMSTABLE_Pos) & ETM_TRCSTATR_PMSTABLE_Msk)


#define ETM_TRCCONFIGR_INSTP0_Pos 1U

#define ETM_TRCCONFIGR_INSTP0_Msk (0x3UL << ETM_TRCCONFIGR_INSTP0_Pos)

#define ETM_TRCCONFIGR_INSTP0(_mrval) ((_mrval << ETM_TRCCONFIGR_INSTP0_Pos) & ETM_TRCCONFIGR_INSTP0_Msk)

#define ETM_TRCCONFIGR_INSTP0_ONLY_BRANCH (0x0UL << ETM_TRCCONFIGR_INSTP0_Pos)

#define ETM_TRCCONFIGR_INSTP0_LOAD_BRANCH (0x1UL << ETM_TRCCONFIGR_INSTP0_Pos)

#define ETM_TRCCONFIGR_INSTP0_STORE_BRANCH (0x2UL << ETM_TRCCONFIGR_INSTP0_Pos)

#define ETM_TRCCONFIGR_INSTP0_LOAD_STORE_BRANCH (0x3UL << ETM_TRCCONFIGR_INSTP0_Pos)


#define ETM_TRCCONFIGR_BB_Pos 3U

#define ETM_TRCCONFIGR_BB_Msk (0x1UL << ETM_TRCCONFIGR_BB_Pos)

#define ETM_TRCCONFIGR_BB(_mrval) ((_mrval << ETM_TRCCONFIGR_BB_Pos) & ETM_TRCCONFIGR_BB_Msk)

#define ETM_TRCCONFIGR_BB_DISABLED (0x0UL << ETM_TRCCONFIGR_BB_Pos)

#define ETM_TRCCONFIGR_BB_ENABLED (0x1UL << ETM_TRCCONFIGR_BB_Pos)


#define ETM_TRCCONFIGR_CCI_Pos 4U

#define ETM_TRCCONFIGR_CCI_Msk (0x1UL << ETM_TRCCONFIGR_CCI_Pos)

#define ETM_TRCCONFIGR_CCI(_mrval) ((_mrval << ETM_TRCCONFIGR_CCI_Pos) & ETM_TRCCONFIGR_CCI_Msk)

#define ETM_TRCCONFIGR_CCI_DISABLED (0x0UL << ETM_TRCCONFIGR_CCI_Pos)

#define ETM_TRCCONFIGR_CCI_ENABLED (0x1UL << ETM_TRCCONFIGR_CCI_Pos)


#define ETM_TRCCONFIGR_CID_Pos 6U

#define ETM_TRCCONFIGR_CID_Msk (0x1UL << ETM_TRCCONFIGR_CID_Pos)

#define ETM_TRCCONFIGR_CID(_mrval) ((_mrval << ETM_TRCCONFIGR_CID_Pos) & ETM_TRCCONFIGR_CID_Msk)


#define ETM_TRCCONFIGR_VMID_Pos 7U

#define ETM_TRCCONFIGR_VMID_Msk (0x1UL << ETM_TRCCONFIGR_VMID_Pos)

#define ETM_TRCCONFIGR_VMID(_mrval) ((_mrval << ETM_TRCCONFIGR_VMID_Pos) & ETM_TRCCONFIGR_VMID_Msk)


#define ETM_TRCCONFIGR_COND_Pos 8U

#define ETM_TRCCONFIGR_COND_Msk (0x7UL << ETM_TRCCONFIGR_COND_Pos)

#define ETM_TRCCONFIGR_COND(_mrval) ((_mrval << ETM_TRCCONFIGR_COND_Pos) & ETM_TRCCONFIGR_COND_Msk)

#define ETM_TRCCONFIGR_COND_DISABLED (0x0UL << ETM_TRCCONFIGR_COND_Pos)

#define ETM_TRCCONFIGR_COND_LOAD (0x1UL << ETM_TRCCONFIGR_COND_Pos)

#define ETM_TRCCONFIGR_COND_STORE (0x2UL << ETM_TRCCONFIGR_COND_Pos)

#define ETM_TRCCONFIGR_COND_LOAD_STORE (0x3UL << ETM_TRCCONFIGR_COND_Pos)

#define ETM_TRCCONFIGR_COND_ALL (0x7UL << ETM_TRCCONFIGR_COND_Pos)


#define ETM_TRCCONFIGR_TS_Pos 11U

#define ETM_TRCCONFIGR_TS_Msk (0x1UL << ETM_TRCCONFIGR_TS_Pos)

#define ETM_TRCCONFIGR_TS(_mrval) ((_mrval << ETM_TRCCONFIGR_TS_Pos) & ETM_TRCCONFIGR_TS_Msk)

#define ETM_TRCCONFIGR_TS_DISABLED (0x0UL << ETM_TRCCONFIGR_TS_Pos)

#define ETM_TRCCONFIGR_TS_ENABLED (0x1UL << ETM_TRCCONFIGR_TS_Pos)


#define ETM_TRCCONFIGR_RS_Pos 12U

#define ETM_TRCCONFIGR_RS_Msk (0x1UL << ETM_TRCCONFIGR_RS_Pos)

#define ETM_TRCCONFIGR_RS(_mrval) ((_mrval << ETM_TRCCONFIGR_RS_Pos) & ETM_TRCCONFIGR_RS_Msk)

#define ETM_TRCCONFIGR_RS_DISABLED (0x0UL << ETM_TRCCONFIGR_RS_Pos)

#define ETM_TRCCONFIGR_RS_ENABLED (0x1UL << ETM_TRCCONFIGR_RS_Pos)


#define ETM_TRCCONFIGR_DA_Pos 16U

#define ETM_TRCCONFIGR_DA_Msk (0x1UL << ETM_TRCCONFIGR_DA_Pos)

#define ETM_TRCCONFIGR_DA(_mrval) ((_mrval << ETM_TRCCONFIGR_DA_Pos) & ETM_TRCCONFIGR_DA_Msk)

#define ETM_TRCCONFIGR_DA_DISABLED (0x0UL << ETM_TRCCONFIGR_DA_Pos)

#define ETM_TRCCONFIGR_DA_ENABLED (0x1UL << ETM_TRCCONFIGR_DA_Pos)


#define ETM_TRCCONFIGR_DV_Pos 17U

#define ETM_TRCCONFIGR_DV_Msk (0x1UL << ETM_TRCCONFIGR_DV_Pos)

#define ETM_TRCCONFIGR_DV(_mrval) ((_mrval << ETM_TRCCONFIGR_DV_Pos) & ETM_TRCCONFIGR_DV_Msk)

#define ETM_TRCCONFIGR_DV_DISABLED (0x0UL << ETM_TRCCONFIGR_DV_Pos)

#define ETM_TRCCONFIGR_DV_ENABLED (0x1UL << ETM_TRCCONFIGR_DV_Pos)


#define ETM_TRCEVENTCTL0R_SEL0_Pos 0U

#define ETM_TRCEVENTCTL0R_SEL0_Msk (0xfUL << ETM_TRCEVENTCTL0R_SEL0_Pos)

#define ETM_TRCEVENTCTL0R_SEL0(_mrval) ((_mrval << ETM_TRCEVENTCTL0R_SEL0_Pos) & ETM_TRCEVENTCTL0R_SEL0_Msk)


#define ETM_TRCEVENTCTL0R_TYPE0_Pos 7U

#define ETM_TRCEVENTCTL0R_TYPE0_Msk (0x1UL << ETM_TRCEVENTCTL0R_TYPE0_Pos)

#define ETM_TRCEVENTCTL0R_TYPE0(_mrval) ((_mrval << ETM_TRCEVENTCTL0R_TYPE0_Pos) & ETM_TRCEVENTCTL0R_TYPE0_Msk)

#define ETM_TRCEVENTCTL0R_TYPE0_SINGLE (0x0UL << ETM_TRCEVENTCTL0R_TYPE0_Pos)

#define ETM_TRCEVENTCTL0R_TYPE0_PAIR (0x1UL << ETM_TRCEVENTCTL0R_TYPE0_Pos)


#define ETM_TRCEVENTCTL0R_SEL1_Pos 8U

#define ETM_TRCEVENTCTL0R_SEL1_Msk (0xfUL << ETM_TRCEVENTCTL0R_SEL1_Pos)

#define ETM_TRCEVENTCTL0R_SEL1(_mrval) ((_mrval << ETM_TRCEVENTCTL0R_SEL1_Pos) & ETM_TRCEVENTCTL0R_SEL1_Msk)


#define ETM_TRCEVENTCTL0R_TYPE1_Pos 15U

#define ETM_TRCEVENTCTL0R_TYPE1_Msk (0x1UL << ETM_TRCEVENTCTL0R_TYPE1_Pos)

#define ETM_TRCEVENTCTL0R_TYPE1(_mrval) ((_mrval << ETM_TRCEVENTCTL0R_TYPE1_Pos) & ETM_TRCEVENTCTL0R_TYPE1_Msk)

#define ETM_TRCEVENTCTL0R_TYPE1_SINGLE (0x0UL << ETM_TRCEVENTCTL0R_TYPE1_Pos)

#define ETM_TRCEVENTCTL0R_TYPE1_PAIR (0x1UL << ETM_TRCEVENTCTL0R_TYPE1_Pos)


#define ETM_TRCEVENTCTL0R_SEL2_Pos 16U

#define ETM_TRCEVENTCTL0R_SEL2_Msk (0xfUL << ETM_TRCEVENTCTL0R_SEL2_Pos)

#define ETM_TRCEVENTCTL0R_SEL2(_mrval) ((_mrval << ETM_TRCEVENTCTL0R_SEL2_Pos) & ETM_TRCEVENTCTL0R_SEL2_Msk)


#define ETM_TRCEVENTCTL0R_TYPE2_Pos 23U

#define ETM_TRCEVENTCTL0R_TYPE2_Msk (0x1UL << ETM_TRCEVENTCTL0R_TYPE2_Pos)

#define ETM_TRCEVENTCTL0R_TYPE2(_mrval) ((_mrval << ETM_TRCEVENTCTL0R_TYPE2_Pos) & ETM_TRCEVENTCTL0R_TYPE2_Msk)

#define ETM_TRCEVENTCTL0R_TYPE2_SINGLE (0x0UL << ETM_TRCEVENTCTL0R_TYPE2_Pos)

#define ETM_TRCEVENTCTL0R_TYPE2_PAIR (0x1UL << ETM_TRCEVENTCTL0R_TYPE2_Pos)


#define ETM_TRCEVENTCTL0R_SEL3_Pos 24U

#define ETM_TRCEVENTCTL0R_SEL3_Msk (0xfUL << ETM_TRCEVENTCTL0R_SEL3_Pos)

#define ETM_TRCEVENTCTL0R_SEL3(_mrval) ((_mrval << ETM_TRCEVENTCTL0R_SEL3_Pos) & ETM_TRCEVENTCTL0R_SEL3_Msk)


#define ETM_TRCEVENTCTL0R_TYPE3_Pos 31U

#define ETM_TRCEVENTCTL0R_TYPE3_Msk (0x1UL << ETM_TRCEVENTCTL0R_TYPE3_Pos)

#define ETM_TRCEVENTCTL0R_TYPE3(_mrval) ((_mrval << ETM_TRCEVENTCTL0R_TYPE3_Pos) & ETM_TRCEVENTCTL0R_TYPE3_Msk)

#define ETM_TRCEVENTCTL0R_TYPE3_SINGLE (0x0UL << ETM_TRCEVENTCTL0R_TYPE3_Pos)

#define ETM_TRCEVENTCTL0R_TYPE3_PAIR (0x1UL << ETM_TRCEVENTCTL0R_TYPE3_Pos)


#define ETM_TRCEVENTCTL1R_INSTEN_Pos 0U

#define ETM_TRCEVENTCTL1R_INSTEN_Msk (0xfUL << ETM_TRCEVENTCTL1R_INSTEN_Pos)

#define ETM_TRCEVENTCTL1R_INSTEN(_mrval) ((_mrval << ETM_TRCEVENTCTL1R_INSTEN_Pos) & ETM_TRCEVENTCTL1R_INSTEN_Msk)


#define ETM_TRCEVENTCTL1R_DATAEN_Pos 4U

#define ETM_TRCEVENTCTL1R_DATAEN_Msk (0x1UL << ETM_TRCEVENTCTL1R_DATAEN_Pos)

#define ETM_TRCEVENTCTL1R_DATAEN(_mrval) ((_mrval << ETM_TRCEVENTCTL1R_DATAEN_Pos) & ETM_TRCEVENTCTL1R_DATAEN_Msk)

#define ETM_TRCEVENTCTL1R_DATAEN_DISABLED (0x0UL << ETM_TRCEVENTCTL1R_DATAEN_Pos)

#define ETM_TRCEVENTCTL1R_DATAEN_ENABLED (0x1UL << ETM_TRCEVENTCTL1R_DATAEN_Pos)


#define ETM_TRCEVENTCTL1R_ATB_Pos 11U

#define ETM_TRCEVENTCTL1R_ATB_Msk (0x1UL << ETM_TRCEVENTCTL1R_ATB_Pos)

#define ETM_TRCEVENTCTL1R_ATB(_mrval) ((_mrval << ETM_TRCEVENTCTL1R_ATB_Pos) & ETM_TRCEVENTCTL1R_ATB_Msk)

#define ETM_TRCEVENTCTL1R_ATB_DISABLED (0x0UL << ETM_TRCEVENTCTL1R_ATB_Pos)

#define ETM_TRCEVENTCTL1R_ATB_ENABLED (0x1UL << ETM_TRCEVENTCTL1R_ATB_Pos)


#define ETM_TRCEVENTCTL1R_LPOVERRIDE_Pos 12U

#define ETM_TRCEVENTCTL1R_LPOVERRIDE_Msk (0x1UL << ETM_TRCEVENTCTL1R_LPOVERRIDE_Pos)

#define ETM_TRCEVENTCTL1R_LPOVERRIDE(_mrval) ((_mrval << ETM_TRCEVENTCTL1R_LPOVERRIDE_Pos) & ETM_TRCEVENTCTL1R_LPOVERRIDE_Msk)

#define ETM_TRCEVENTCTL1R_LPOVERRIDE_DISABLED (0x0UL << ETM_TRCEVENTCTL1R_LPOVERRIDE_Pos)

#define ETM_TRCEVENTCTL1R_LPOVERRIDE_ENABLED (0x1UL << ETM_TRCEVENTCTL1R_LPOVERRIDE_Pos)


#define ETM_TRCSTALLCTLR_LEVEL_Pos 2U

#define ETM_TRCSTALLCTLR_LEVEL_Msk (0x3UL << ETM_TRCSTALLCTLR_LEVEL_Pos)

#define ETM_TRCSTALLCTLR_LEVEL(_mrval) ((_mrval << ETM_TRCSTALLCTLR_LEVEL_Pos) & ETM_TRCSTALLCTLR_LEVEL_Msk)


#define ETM_TRCSTALLCTLR_ISTALL_Pos 8U

#define ETM_TRCSTALLCTLR_ISTALL_Msk (0x1UL << ETM_TRCSTALLCTLR_ISTALL_Pos)

#define ETM_TRCSTALLCTLR_ISTALL(_mrval) ((_mrval << ETM_TRCSTALLCTLR_ISTALL_Pos) & ETM_TRCSTALLCTLR_ISTALL_Msk)

#define ETM_TRCSTALLCTLR_ISTALL_DISABLED (0x0UL << ETM_TRCSTALLCTLR_ISTALL_Pos)

#define ETM_TRCSTALLCTLR_ISTALL_ENABLED (0x1UL << ETM_TRCSTALLCTLR_ISTALL_Pos)


#define ETM_TRCSTALLCTLR_DSTALL_Pos 9U

#define ETM_TRCSTALLCTLR_DSTALL_Msk (0x1UL << ETM_TRCSTALLCTLR_DSTALL_Pos)

#define ETM_TRCSTALLCTLR_DSTALL(_mrval) ((_mrval << ETM_TRCSTALLCTLR_DSTALL_Pos) & ETM_TRCSTALLCTLR_DSTALL_Msk)

#define ETM_TRCSTALLCTLR_DSTALL_DISABLED (0x0UL << ETM_TRCSTALLCTLR_DSTALL_Pos)

#define ETM_TRCSTALLCTLR_DSTALL_ENABLED (0x1UL << ETM_TRCSTALLCTLR_DSTALL_Pos)


#define ETM_TRCSTALLCTLR_INSTPRIORITY_Pos 10U

#define ETM_TRCSTALLCTLR_INSTPRIORITY_Msk (0x1UL << ETM_TRCSTALLCTLR_INSTPRIORITY_Pos)

#define ETM_TRCSTALLCTLR_INSTPRIORITY(_mrval) ((_mrval << ETM_TRCSTALLCTLR_INSTPRIORITY_Pos) & ETM_TRCSTALLCTLR_INSTPRIORITY_Msk)

#define ETM_TRCSTALLCTLR_INSTPRIORITY_DISABLED (0x0UL << ETM_TRCSTALLCTLR_INSTPRIORITY_Pos)

#define ETM_TRCSTALLCTLR_INSTPRIORITY_ENABLED (0x1UL << ETM_TRCSTALLCTLR_INSTPRIORITY_Pos)


#define ETM_TRCSTALLCTLR_DATADISCARD_Pos 11U

#define ETM_TRCSTALLCTLR_DATADISCARD_Msk (0x3UL << ETM_TRCSTALLCTLR_DATADISCARD_Pos)

#define ETM_TRCSTALLCTLR_DATADISCARD(_mrval) ((_mrval << ETM_TRCSTALLCTLR_DATADISCARD_Pos) & ETM_TRCSTALLCTLR_DATADISCARD_Msk)

#define ETM_TRCSTALLCTLR_DATADISCARD_NONE (0x0UL << ETM_TRCSTALLCTLR_DATADISCARD_Pos)

#define ETM_TRCSTALLCTLR_DATADISCARD_LOAD (0x1UL << ETM_TRCSTALLCTLR_DATADISCARD_Pos)

#define ETM_TRCSTALLCTLR_DATADISCARD_STORE (0x2UL << ETM_TRCSTALLCTLR_DATADISCARD_Pos)

#define ETM_TRCSTALLCTLR_DATADISCARD_LOAD_STORE (0x3UL << ETM_TRCSTALLCTLR_DATADISCARD_Pos)


#define ETM_TRCTSCTLR_SEL_Pos 0U

#define ETM_TRCTSCTLR_SEL_Msk (0xfUL << ETM_TRCTSCTLR_SEL_Pos)

#define ETM_TRCTSCTLR_SEL(_mrval) ((_mrval << ETM_TRCTSCTLR_SEL_Pos) & ETM_TRCTSCTLR_SEL_Msk)


#define ETM_TRCTSCTLR_TYPE_Pos 7U

#define ETM_TRCTSCTLR_TYPE_Msk (0x1UL << ETM_TRCTSCTLR_TYPE_Pos)

#define ETM_TRCTSCTLR_TYPE(_mrval) ((_mrval << ETM_TRCTSCTLR_TYPE_Pos) & ETM_TRCTSCTLR_TYPE_Msk)

#define ETM_TRCTSCTLR_TYPE_SINGLE (0x0UL << ETM_TRCTSCTLR_TYPE_Pos)

#define ETM_TRCTSCTLR_TYPE_PAIR (0x1UL << ETM_TRCTSCTLR_TYPE_Pos)


#define ETM_TRCSYNCPR_PERIOD_Pos 0U

#define ETM_TRCSYNCPR_PERIOD_Msk (0x1fUL << ETM_TRCSYNCPR_PERIOD_Pos)

#define ETM_TRCSYNCPR_PERIOD(_mrval) ((_mrval << ETM_TRCSYNCPR_PERIOD_Pos) & ETM_TRCSYNCPR_PERIOD_Msk)


#define ETM_TRCCCCCTLR_THRESHOLD_Pos 0U

#define ETM_TRCCCCCTLR_THRESHOLD_Msk (0xfffUL << ETM_TRCCCCCTLR_THRESHOLD_Pos)

#define ETM_TRCCCCCTLR_THRESHOLD(_mrval) ((_mrval << ETM_TRCCCCCTLR_THRESHOLD_Pos) & ETM_TRCCCCCTLR_THRESHOLD_Msk)


#define ETM_TRCBBCTLR_RANGE_Pos 0U

#define ETM_TRCBBCTLR_RANGE_Msk (0xfUL << ETM_TRCBBCTLR_RANGE_Pos)

#define ETM_TRCBBCTLR_RANGE(_mrval) ((_mrval << ETM_TRCBBCTLR_RANGE_Pos) & ETM_TRCBBCTLR_RANGE_Msk)


#define ETM_TRCBBCTLR_MODE_Pos 8U

#define ETM_TRCBBCTLR_MODE_Msk (0x1UL << ETM_TRCBBCTLR_MODE_Pos)

#define ETM_TRCBBCTLR_MODE(_mrval) ((_mrval << ETM_TRCBBCTLR_MODE_Pos) & ETM_TRCBBCTLR_MODE_Msk)

#define ETM_TRCBBCTLR_MODE_EXCLUDE (0x0UL << ETM_TRCBBCTLR_MODE_Pos)

#define ETM_TRCBBCTLR_MODE_INCLUDE (0x1UL << ETM_TRCBBCTLR_MODE_Pos)


#define ETM_TRCTRACEIDR_TRACEID_Pos 0U

#define ETM_TRCTRACEIDR_TRACEID_Msk (0x7fUL << ETM_TRCTRACEIDR_TRACEID_Pos)

#define ETM_TRCTRACEIDR_TRACEID(_mrval) ((_mrval << ETM_TRCTRACEIDR_TRACEID_Pos) & ETM_TRCTRACEIDR_TRACEID_Msk)


#define ETM_TRCVICTLR_SEL_Pos 0U

#define ETM_TRCVICTLR_SEL_Msk (0xfUL << ETM_TRCVICTLR_SEL_Pos)

#define ETM_TRCVICTLR_SEL(_mrval) ((_mrval << ETM_TRCVICTLR_SEL_Pos) & ETM_TRCVICTLR_SEL_Msk)


#define ETM_TRCVICTLR_TYPE_Pos 7U

#define ETM_TRCVICTLR_TYPE_Msk (0x1UL << ETM_TRCVICTLR_TYPE_Pos)

#define ETM_TRCVICTLR_TYPE(_mrval) ((_mrval << ETM_TRCVICTLR_TYPE_Pos) & ETM_TRCVICTLR_TYPE_Msk)

#define ETM_TRCVICTLR_TYPE_SINGLE (0x0UL << ETM_TRCVICTLR_TYPE_Pos)

#define ETM_TRCVICTLR_TYPE_PAIR (0x1UL << ETM_TRCVICTLR_TYPE_Pos)


#define ETM_TRCVICTLR_SSSTATUS_Pos 9U

#define ETM_TRCVICTLR_SSSTATUS_Msk (0x1UL << ETM_TRCVICTLR_SSSTATUS_Pos)

#define ETM_TRCVICTLR_SSSTATUS(_mrval) ((_mrval << ETM_TRCVICTLR_SSSTATUS_Pos) & ETM_TRCVICTLR_SSSTATUS_Msk)

#define ETM_TRCVICTLR_SSSTATUS_STOPPED (0x0UL << ETM_TRCVICTLR_SSSTATUS_Pos)

#define ETM_TRCVICTLR_SSSTATUS_STARTED (0x1UL << ETM_TRCVICTLR_SSSTATUS_Pos)


#define ETM_TRCVICTLR_TRCRESET_Pos 10U

#define ETM_TRCVICTLR_TRCRESET_Msk (0x1UL << ETM_TRCVICTLR_TRCRESET_Pos)

#define ETM_TRCVICTLR_TRCRESET(_mrval) ((_mrval << ETM_TRCVICTLR_TRCRESET_Pos) & ETM_TRCVICTLR_TRCRESET_Msk)

#define ETM_TRCVICTLR_TRCRESET_IFF_PRIOR (0x0UL << ETM_TRCVICTLR_TRCRESET_Pos)

#define ETM_TRCVICTLR_TRCRESET_ALWAYS (0x1UL << ETM_TRCVICTLR_TRCRESET_Pos)


#define ETM_TRCVICTLR_TRCERR_Pos 11U

#define ETM_TRCVICTLR_TRCERR_Msk (0x1UL << ETM_TRCVICTLR_TRCERR_Pos)

#define ETM_TRCVICTLR_TRCERR(_mrval) ((_mrval << ETM_TRCVICTLR_TRCERR_Pos) & ETM_TRCVICTLR_TRCERR_Msk)

#define ETM_TRCVICTLR_TRCERR_IFF_PRIOR (0x0UL << ETM_TRCVICTLR_TRCERR_Pos)

#define ETM_TRCVICTLR_TRCERR_ALWAYS (0x1UL << ETM_TRCVICTLR_TRCERR_Pos)


#define ETM_TRCVICTLR_EXLEVEL_S0_Pos 16U

#define ETM_TRCVICTLR_EXLEVEL_S0_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL_S0_Pos)

#define ETM_TRCVICTLR_EXLEVEL_S0(_mrval) ((_mrval << ETM_TRCVICTLR_EXLEVEL_S0_Pos) & ETM_TRCVICTLR_EXLEVEL_S0_Msk)

#define ETM_TRCVICTLR_EXLEVEL_S0_DISABLED (0x0UL << ETM_TRCVICTLR_EXLEVEL_S0_Pos)

#define ETM_TRCVICTLR_EXLEVEL_S0_ENABLED (0x1UL << ETM_TRCVICTLR_EXLEVEL_S0_Pos)


#define ETM_TRCVICTLR_EXLEVEL_S3_Pos 19U

#define ETM_TRCVICTLR_EXLEVEL_S3_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL_S3_Pos)

#define ETM_TRCVICTLR_EXLEVEL_S3(_mrval) ((_mrval << ETM_TRCVICTLR_EXLEVEL_S3_Pos) & ETM_TRCVICTLR_EXLEVEL_S3_Msk)

#define ETM_TRCVICTLR_EXLEVEL_S3_DISABLED (0x0UL << ETM_TRCVICTLR_EXLEVEL_S3_Pos)

#define ETM_TRCVICTLR_EXLEVEL_S3_ENABLED (0x1UL << ETM_TRCVICTLR_EXLEVEL_S3_Pos)


#define ETM_TRCVIIECTLR_INCLUDE_Pos 0U

#define ETM_TRCVIIECTLR_INCLUDE_Msk (0xfUL << ETM_TRCVIIECTLR_INCLUDE_Pos)

#define ETM_TRCVIIECTLR_INCLUDE(_mrval) ((_mrval << ETM_TRCVIIECTLR_INCLUDE_Pos) & ETM_TRCVIIECTLR_INCLUDE_Msk)


#define ETM_TRCVIIECTLR_EXCLUDE_Pos 16U

#define ETM_TRCVIIECTLR_EXCLUDE_Msk (0xfUL << ETM_TRCVIIECTLR_EXCLUDE_Pos)

#define ETM_TRCVIIECTLR_EXCLUDE(_mrval) ((_mrval << ETM_TRCVIIECTLR_EXCLUDE_Pos) & ETM_TRCVIIECTLR_EXCLUDE_Msk)


#define ETM_TRCVISSCTLR_START_Pos 0U

#define ETM_TRCVISSCTLR_START_Msk (0xfUL << ETM_TRCVISSCTLR_START_Pos)

#define ETM_TRCVISSCTLR_START(_mrval) ((_mrval << ETM_TRCVISSCTLR_START_Pos) & ETM_TRCVISSCTLR_START_Msk)


#define ETM_TRCVISSCTLR_STOP_Pos 16U

#define ETM_TRCVISSCTLR_STOP_Msk (0xfUL << ETM_TRCVISSCTLR_STOP_Pos)

#define ETM_TRCVISSCTLR_STOP(_mrval) ((_mrval << ETM_TRCVISSCTLR_STOP_Pos) & ETM_TRCVISSCTLR_STOP_Msk)


#define ETM_TRCVDCTLR_SEL_Pos 0U

#define ETM_TRCVDCTLR_SEL_Msk (0xfUL << ETM_TRCVDCTLR_SEL_Pos)

#define ETM_TRCVDCTLR_SEL(_mrval) ((_mrval << ETM_TRCVDCTLR_SEL_Pos) & ETM_TRCVDCTLR_SEL_Msk)


#define ETM_TRCVDCTLR_TYPE_Pos 7U

#define ETM_TRCVDCTLR_TYPE_Msk (0x1UL << ETM_TRCVDCTLR_TYPE_Pos)

#define ETM_TRCVDCTLR_TYPE(_mrval) ((_mrval << ETM_TRCVDCTLR_TYPE_Pos) & ETM_TRCVDCTLR_TYPE_Msk)

#define ETM_TRCVDCTLR_TYPE_SINGLE (0x0UL << ETM_TRCVDCTLR_TYPE_Pos)

#define ETM_TRCVDCTLR_TYPE_PAIR (0x1UL << ETM_TRCVDCTLR_TYPE_Pos)


#define ETM_TRCVDCTLR_SPREL_Pos 8U

#define ETM_TRCVDCTLR_SPREL_Msk (0x3UL << ETM_TRCVDCTLR_SPREL_Pos)

#define ETM_TRCVDCTLR_SPREL(_mrval) ((_mrval << ETM_TRCVDCTLR_SPREL_Pos) & ETM_TRCVDCTLR_SPREL_Msk)

#define ETM_TRCVDCTLR_SPREL_ALL (0x0UL << ETM_TRCVDCTLR_SPREL_Pos)

#define ETM_TRCVDCTLR_SPREL_NO_ADDR (0x2UL << ETM_TRCVDCTLR_SPREL_Pos)

#define ETM_TRCVDCTLR_SPREL_NONE (0x3UL << ETM_TRCVDCTLR_SPREL_Pos)


#define ETM_TRCVDCTLR_PCREL_Pos 10U

#define ETM_TRCVDCTLR_PCREL_Msk (0x1UL << ETM_TRCVDCTLR_PCREL_Pos)

#define ETM_TRCVDCTLR_PCREL(_mrval) ((_mrval << ETM_TRCVDCTLR_PCREL_Pos) & ETM_TRCVDCTLR_PCREL_Msk)

#define ETM_TRCVDCTLR_PCREL_ALL (0x0UL << ETM_TRCVDCTLR_PCREL_Pos)

#define ETM_TRCVDCTLR_PCREL_NONE (0x1UL << ETM_TRCVDCTLR_PCREL_Pos)


#define ETM_TRCVDCTLR_TRCEXDATA_Pos 12U

#define ETM_TRCVDCTLR_TRCEXDATA_Msk (0x1UL << ETM_TRCVDCTLR_TRCEXDATA_Pos)

#define ETM_TRCVDCTLR_TRCEXDATA(_mrval) ((_mrval << ETM_TRCVDCTLR_TRCEXDATA_Pos) & ETM_TRCVDCTLR_TRCEXDATA_Msk)

#define ETM_TRCVDCTLR_TRCEXDATA_DISABLED (0x0UL << ETM_TRCVDCTLR_TRCEXDATA_Pos)

#define ETM_TRCVDCTLR_TRCEXDATA_ENABLED (0x1UL << ETM_TRCVDCTLR_TRCEXDATA_Pos)


#define ETM_TRCVDSACCTLR_INCLUDE_Pos 0U

#define ETM_TRCVDSACCTLR_INCLUDE_Msk (0xffUL << ETM_TRCVDSACCTLR_INCLUDE_Pos)

#define ETM_TRCVDSACCTLR_INCLUDE(_mrval) ((_mrval << ETM_TRCVDSACCTLR_INCLUDE_Pos) & ETM_TRCVDSACCTLR_INCLUDE_Msk)


#define ETM_TRCVDSACCTLR_EXCLUDE_Pos 16U

#define ETM_TRCVDSACCTLR_EXCLUDE_Msk (0xffUL << ETM_TRCVDSACCTLR_EXCLUDE_Pos)

#define ETM_TRCVDSACCTLR_EXCLUDE(_mrval) ((_mrval << ETM_TRCVDSACCTLR_EXCLUDE_Pos) & ETM_TRCVDSACCTLR_EXCLUDE_Msk)


#define ETM_TRCVDARCCTLR_INCLUDE_Pos 0U

#define ETM_TRCVDARCCTLR_INCLUDE_Msk (0xffUL << ETM_TRCVDARCCTLR_INCLUDE_Pos)

#define ETM_TRCVDARCCTLR_INCLUDE(_mrval) ((_mrval << ETM_TRCVDARCCTLR_INCLUDE_Pos) & ETM_TRCVDARCCTLR_INCLUDE_Msk)


#define ETM_TRCVDARCCTLR_EXCLUDE_Pos 16U

#define ETM_TRCVDARCCTLR_EXCLUDE_Msk (0xffUL << ETM_TRCVDARCCTLR_EXCLUDE_Pos)

#define ETM_TRCVDARCCTLR_EXCLUDE(_mrval) ((_mrval << ETM_TRCVDARCCTLR_EXCLUDE_Pos) & ETM_TRCVDARCCTLR_EXCLUDE_Msk)


#define ETM_TRCSEQEVR_FSEL_Pos 0U

#define ETM_TRCSEQEVR_FSEL_Msk (0xfUL << ETM_TRCSEQEVR_FSEL_Pos)

#define ETM_TRCSEQEVR_FSEL(_mrval) ((_mrval << ETM_TRCSEQEVR_FSEL_Pos) & ETM_TRCSEQEVR_FSEL_Msk)


#define ETM_TRCSEQEVR_FTYPE_Pos 7U

#define ETM_TRCSEQEVR_FTYPE_Msk (0x1UL << ETM_TRCSEQEVR_FTYPE_Pos)

#define ETM_TRCSEQEVR_FTYPE(_mrval) ((_mrval << ETM_TRCSEQEVR_FTYPE_Pos) & ETM_TRCSEQEVR_FTYPE_Msk)

#define ETM_TRCSEQEVR_FTYPE_SINGLE (0x0UL << ETM_TRCSEQEVR_FTYPE_Pos)

#define ETM_TRCSEQEVR_FTYPE_PAIR (0x1UL << ETM_TRCSEQEVR_FTYPE_Pos)


#define ETM_TRCSEQEVR_BSEL_Pos 8U

#define ETM_TRCSEQEVR_BSEL_Msk (0xfUL << ETM_TRCSEQEVR_BSEL_Pos)

#define ETM_TRCSEQEVR_BSEL(_mrval) ((_mrval << ETM_TRCSEQEVR_BSEL_Pos) & ETM_TRCSEQEVR_BSEL_Msk)


#define ETM_TRCSEQEVR_BTYPE_Pos 15U

#define ETM_TRCSEQEVR_BTYPE_Msk (0x1UL << ETM_TRCSEQEVR_BTYPE_Pos)

#define ETM_TRCSEQEVR_BTYPE(_mrval) ((_mrval << ETM_TRCSEQEVR_BTYPE_Pos) & ETM_TRCSEQEVR_BTYPE_Msk)

#define ETM_TRCSEQEVR_BTYPE_SINGLE (0x0UL << ETM_TRCSEQEVR_BTYPE_Pos)

#define ETM_TRCSEQEVR_BTYPE_PAIR (0x1UL << ETM_TRCSEQEVR_BTYPE_Pos)


#define ETM_TRCSEQRSTEVR_RESETSEL_Pos 0U

#define ETM_TRCSEQRSTEVR_RESETSEL_Msk (0xfUL << ETM_TRCSEQRSTEVR_RESETSEL_Pos)

#define ETM_TRCSEQRSTEVR_RESETSEL(_mrval) ((_mrval << ETM_TRCSEQRSTEVR_RESETSEL_Pos) & ETM_TRCSEQRSTEVR_RESETSEL_Msk)


#define ETM_TRCSEQRSTEVR_TYPE_Pos 7U

#define ETM_TRCSEQRSTEVR_TYPE_Msk (0x1UL << ETM_TRCSEQRSTEVR_TYPE_Pos)

#define ETM_TRCSEQRSTEVR_TYPE(_mrval) ((_mrval << ETM_TRCSEQRSTEVR_TYPE_Pos) & ETM_TRCSEQRSTEVR_TYPE_Msk)

#define ETM_TRCSEQRSTEVR_TYPE_SINGLE (0x0UL << ETM_TRCSEQRSTEVR_TYPE_Pos)

#define ETM_TRCSEQRSTEVR_TYPE_PAIR (0x1UL << ETM_TRCSEQRSTEVR_TYPE_Pos)


#define ETM_TRCSEQSTR_STATE_Pos 0U

#define ETM_TRCSEQSTR_STATE_Msk (0x3UL << ETM_TRCSEQSTR_STATE_Pos)

#define ETM_TRCSEQSTR_STATE(_mrval) ((_mrval << ETM_TRCSEQSTR_STATE_Pos) & ETM_TRCSEQSTR_STATE_Msk)


#define ETM_TRCCNTRLDVR_VALUE_Pos 0U

#define ETM_TRCCNTRLDVR_VALUE_Msk (0xffffUL << ETM_TRCCNTRLDVR_VALUE_Pos)

#define ETM_TRCCNTRLDVR_VALUE(_mrval) ((_mrval << ETM_TRCCNTRLDVR_VALUE_Pos) & ETM_TRCCNTRLDVR_VALUE_Msk)


#define ETM_TRCCNTCTLR_CNTSEL_Pos 0U

#define ETM_TRCCNTCTLR_CNTSEL_Msk (0xfUL << ETM_TRCCNTCTLR_CNTSEL_Pos)

#define ETM_TRCCNTCTLR_CNTSEL(_mrval) ((_mrval << ETM_TRCCNTCTLR_CNTSEL_Pos) & ETM_TRCCNTCTLR_CNTSEL_Msk)


#define ETM_TRCCNTCTLR_CNTTYPE_Pos 7U

#define ETM_TRCCNTCTLR_CNTTYPE_Msk (0x1UL << ETM_TRCCNTCTLR_CNTTYPE_Pos)

#define ETM_TRCCNTCTLR_CNTTYPE(_mrval) ((_mrval << ETM_TRCCNTCTLR_CNTTYPE_Pos) & ETM_TRCCNTCTLR_CNTTYPE_Msk)

#define ETM_TRCCNTCTLR_CNTTYPE_SINGLE (0x0UL << ETM_TRCCNTCTLR_CNTTYPE_Pos)

#define ETM_TRCCNTCTLR_CNTTYPE_PAIR (0x1UL << ETM_TRCCNTCTLR_CNTTYPE_Pos)


#define ETM_TRCCNTCTLR_RLDSEL_Pos 8U

#define ETM_TRCCNTCTLR_RLDSEL_Msk (0xfUL << ETM_TRCCNTCTLR_RLDSEL_Pos)

#define ETM_TRCCNTCTLR_RLDSEL(_mrval) ((_mrval << ETM_TRCCNTCTLR_RLDSEL_Pos) & ETM_TRCCNTCTLR_RLDSEL_Msk)


#define ETM_TRCCNTCTLR_RLDTYPE_Pos 15U

#define ETM_TRCCNTCTLR_RLDTYPE_Msk (0x1UL << ETM_TRCCNTCTLR_RLDTYPE_Pos)

#define ETM_TRCCNTCTLR_RLDTYPE(_mrval) ((_mrval << ETM_TRCCNTCTLR_RLDTYPE_Pos) & ETM_TRCCNTCTLR_RLDTYPE_Msk)

#define ETM_TRCCNTCTLR_RLDTYPE_SINGLE (0x0UL << ETM_TRCCNTCTLR_RLDTYPE_Pos)

#define ETM_TRCCNTCTLR_RLDTYPE_PAIR (0x1UL << ETM_TRCCNTCTLR_RLDTYPE_Pos)


#define ETM_TRCCNTCTLR_RLDSELF_Pos 16U

#define ETM_TRCCNTCTLR_RLDSELF_Msk (0x1UL << ETM_TRCCNTCTLR_RLDSELF_Pos)

#define ETM_TRCCNTCTLR_RLDSELF(_mrval) ((_mrval << ETM_TRCCNTCTLR_RLDSELF_Pos) & ETM_TRCCNTCTLR_RLDSELF_Msk)

#define ETM_TRCCNTCTLR_RLDSELF_DISABLED (0x0UL << ETM_TRCCNTCTLR_RLDSELF_Pos)

#define ETM_TRCCNTCTLR_RLDSELF_ENABLED (0x1UL << ETM_TRCCNTCTLR_RLDSELF_Pos)


#define ETM_TRCCNTCTLR_CNTCHAIN_Pos 17U

#define ETM_TRCCNTCTLR_CNTCHAIN_Msk (0x1UL << ETM_TRCCNTCTLR_CNTCHAIN_Pos)

#define ETM_TRCCNTCTLR_CNTCHAIN(_mrval) ((_mrval << ETM_TRCCNTCTLR_CNTCHAIN_Pos) & ETM_TRCCNTCTLR_CNTCHAIN_Msk)

#define ETM_TRCCNTCTLR_CNTCHAIN_DISABLED (0x0UL << ETM_TRCCNTCTLR_CNTCHAIN_Pos)

#define ETM_TRCCNTCTLR_CNTCHAIN_ENABLED (0x1UL << ETM_TRCCNTCTLR_CNTCHAIN_Pos)


#define ETM_TRCCNTVR_VALUE_Pos 0U

#define ETM_TRCCNTVR_VALUE_Msk (0xffffUL << ETM_TRCCNTVR_VALUE_Pos)

#define ETM_TRCCNTVR_VALUE(_mrval) ((_mrval << ETM_TRCCNTVR_VALUE_Pos) & ETM_TRCCNTVR_VALUE_Msk)


#define ETM_TRCID8_MAXSPEC_Pos 0U

#define ETM_TRCID8_MAXSPEC_Msk (0xffffffffUL << ETM_TRCID8_MAXSPEC_Pos)

#define ETM_TRCID8_MAXSPEC(_mrval) ((_mrval << ETM_TRCID8_MAXSPEC_Pos) & ETM_TRCID8_MAXSPEC_Msk)


#define ETM_TRCID9_NUMP0KEY_Pos 0U

#define ETM_TRCID9_NUMP0KEY_Msk (0xffffffffUL << ETM_TRCID9_NUMP0KEY_Pos)

#define ETM_TRCID9_NUMP0KEY(_mrval) ((_mrval << ETM_TRCID9_NUMP0KEY_Pos) & ETM_TRCID9_NUMP0KEY_Msk)


#define ETM_TRCID10_NUMP1KEY_Pos 0U

#define ETM_TRCID10_NUMP1KEY_Msk (0xffffffffUL << ETM_TRCID10_NUMP1KEY_Pos)

#define ETM_TRCID10_NUMP1KEY(_mrval) ((_mrval << ETM_TRCID10_NUMP1KEY_Pos) & ETM_TRCID10_NUMP1KEY_Msk)


#define ETM_TRCID11_NUMP1SPC_Pos 0U

#define ETM_TRCID11_NUMP1SPC_Msk (0xffffffffUL << ETM_TRCID11_NUMP1SPC_Pos)

#define ETM_TRCID11_NUMP1SPC(_mrval) ((_mrval << ETM_TRCID11_NUMP1SPC_Pos) & ETM_TRCID11_NUMP1SPC_Msk)


#define ETM_TRCID12_NUMCONDKEY_Pos 0U

#define ETM_TRCID12_NUMCONDKEY_Msk (0xffffffffUL << ETM_TRCID12_NUMCONDKEY_Pos)

#define ETM_TRCID12_NUMCONDKEY(_mrval) ((_mrval << ETM_TRCID12_NUMCONDKEY_Pos) & ETM_TRCID12_NUMCONDKEY_Msk)


#define ETM_TRCID13_NUMCONDSPC_Pos 0U

#define ETM_TRCID13_NUMCONDSPC_Msk (0xffffffffUL << ETM_TRCID13_NUMCONDSPC_Pos)

#define ETM_TRCID13_NUMCONDSPC(_mrval) ((_mrval << ETM_TRCID13_NUMCONDSPC_Pos) & ETM_TRCID13_NUMCONDSPC_Msk)


#define ETM_TRCID0_INSTP0_Pos 1U

#define ETM_TRCID0_INSTP0_Msk (0x3UL << ETM_TRCID0_INSTP0_Pos)

#define ETM_TRCID0_INSTP0(_mrval) ((_mrval << ETM_TRCID0_INSTP0_Pos) & ETM_TRCID0_INSTP0_Msk)

#define ETM_TRCID0_INSTP0_SUPPORTED (0x3UL << ETM_TRCID0_INSTP0_Pos)


#define ETM_TRCID0_TRCDATA_Pos 3U

#define ETM_TRCID0_TRCDATA_Msk (0x3UL << ETM_TRCID0_TRCDATA_Pos)

#define ETM_TRCID0_TRCDATA(_mrval) ((_mrval << ETM_TRCID0_TRCDATA_Pos) & ETM_TRCID0_TRCDATA_Msk)

#define ETM_TRCID0_TRCDATA_SUPPORTED (0x3UL << ETM_TRCID0_TRCDATA_Pos)


#define ETM_TRCID0_TRCBB_Pos 5U

#define ETM_TRCID0_TRCBB_Msk (0x1UL << ETM_TRCID0_TRCBB_Pos)

#define ETM_TRCID0_TRCBB(_mrval) ((_mrval << ETM_TRCID0_TRCBB_Pos) & ETM_TRCID0_TRCBB_Msk)

#define ETM_TRCID0_TRCBB_NOT_IMPLEMENTED (0x0UL << ETM_TRCID0_TRCBB_Pos)

#define ETM_TRCID0_TRCBB_IMPLEMENTED (0x1UL << ETM_TRCID0_TRCBB_Pos)


#define ETM_TRCID0_TRCCOND_Pos 6U

#define ETM_TRCID0_TRCCOND_Msk (0x1UL << ETM_TRCID0_TRCCOND_Pos)

#define ETM_TRCID0_TRCCOND(_mrval) ((_mrval << ETM_TRCID0_TRCCOND_Pos) & ETM_TRCID0_TRCCOND_Msk)

#define ETM_TRCID0_TRCCOND_NOT_IMPLEMENTED (0x0UL << ETM_TRCID0_TRCCOND_Pos)

#define ETM_TRCID0_TRCCOND_IMPLEMENTED (0x1UL << ETM_TRCID0_TRCCOND_Pos)


#define ETM_TRCID0_TRCCCI_Pos 7U

#define ETM_TRCID0_TRCCCI_Msk (0x1UL << ETM_TRCID0_TRCCCI_Pos)

#define ETM_TRCID0_TRCCCI(_mrval) ((_mrval << ETM_TRCID0_TRCCCI_Pos) & ETM_TRCID0_TRCCCI_Msk)

#define ETM_TRCID0_TRCCCI_NOT_IMPLEMENTED (0x0UL << ETM_TRCID0_TRCCCI_Pos)

#define ETM_TRCID0_TRCCCI_IMPLEMENTED (0x1UL << ETM_TRCID0_TRCCCI_Pos)


#define ETM_TRCID0_RETSTACK_Pos 9U

#define ETM_TRCID0_RETSTACK_Msk (0x1UL << ETM_TRCID0_RETSTACK_Pos)

#define ETM_TRCID0_RETSTACK(_mrval) ((_mrval << ETM_TRCID0_RETSTACK_Pos) & ETM_TRCID0_RETSTACK_Msk)

#define ETM_TRCID0_RETSTACK_NOT_IMPLEMENTED (0x0UL << ETM_TRCID0_RETSTACK_Pos)

#define ETM_TRCID0_RETSTACK_IMPLEMENTED (0x1UL << ETM_TRCID0_RETSTACK_Pos)


#define ETM_TRCID0_NUMEVENT_Pos 10U

#define ETM_TRCID0_NUMEVENT_Msk (0x3UL << ETM_TRCID0_NUMEVENT_Pos)

#define ETM_TRCID0_NUMEVENT(_mrval) ((_mrval << ETM_TRCID0_NUMEVENT_Pos) & ETM_TRCID0_NUMEVENT_Msk)

#define ETM_TRCID0_NUMEVENT_4_EVENT_ID (0x3UL << ETM_TRCID0_NUMEVENT_Pos)

#define ETM_TRCID0_NUMEVENT_2_EVENT_INST_ONLY (0x1UL << ETM_TRCID0_NUMEVENT_Pos)


#define ETM_TRCID0_COND_Pos 12U

#define ETM_TRCID0_COND_Msk (0x3UL << ETM_TRCID0_COND_Pos)

#define ETM_TRCID0_COND(_mrval) ((_mrval << ETM_TRCID0_COND_Pos) & ETM_TRCID0_COND_Msk)


#define ETM_TRCID0_QFILT_Pos 14U

#define ETM_TRCID0_QFILT_Msk (0x1UL << ETM_TRCID0_QFILT_Pos)

#define ETM_TRCID0_QFILT(_mrval) ((_mrval << ETM_TRCID0_QFILT_Pos) & ETM_TRCID0_QFILT_Msk)


#define ETM_TRCID0_QSUPP_Pos 15U

#define ETM_TRCID0_QSUPP_Msk (0x3UL << ETM_TRCID0_QSUPP_Pos)

#define ETM_TRCID0_QSUPP(_mrval) ((_mrval << ETM_TRCID0_QSUPP_Pos) & ETM_TRCID0_QSUPP_Msk)


#define ETM_TRCID0_TRCEXDATA_Pos 17U

#define ETM_TRCID0_TRCEXDATA_Msk (0x1UL << ETM_TRCID0_TRCEXDATA_Pos)

#define ETM_TRCID0_TRCEXDATA(_mrval) ((_mrval << ETM_TRCID0_TRCEXDATA_Pos) & ETM_TRCID0_TRCEXDATA_Msk)

#define ETM_TRCID0_TRCEXDATA_NOT_IMPLEMENTED (0x0UL << ETM_TRCID0_TRCEXDATA_Pos)

#define ETM_TRCID0_TRCEXDATA_IMPLEMENTED (0x1UL << ETM_TRCID0_TRCEXDATA_Pos)


#define ETM_TRCID0_TSSIZE_Pos 24U

#define ETM_TRCID0_TSSIZE_Msk (0x1fUL << ETM_TRCID0_TSSIZE_Pos)

#define ETM_TRCID0_TSSIZE(_mrval) ((_mrval << ETM_TRCID0_TSSIZE_Pos) & ETM_TRCID0_TSSIZE_Msk)


#define ETM_TRCID0_COMMOPT_Pos 29U

#define ETM_TRCID0_COMMOPT_Msk (0x1UL << ETM_TRCID0_COMMOPT_Pos)

#define ETM_TRCID0_COMMOPT(_mrval) ((_mrval << ETM_TRCID0_COMMOPT_Pos) & ETM_TRCID0_COMMOPT_Msk)


#define ETM_TRCID1_REVISION_Pos 0U

#define ETM_TRCID1_REVISION_Msk (0xfUL << ETM_TRCID1_REVISION_Pos)

#define ETM_TRCID1_REVISION(_mrval) ((_mrval << ETM_TRCID1_REVISION_Pos) & ETM_TRCID1_REVISION_Msk)


#define ETM_TRCID1_TRCARCHMIN_Pos 4U

#define ETM_TRCID1_TRCARCHMIN_Msk (0xfUL << ETM_TRCID1_TRCARCHMIN_Pos)

#define ETM_TRCID1_TRCARCHMIN(_mrval) ((_mrval << ETM_TRCID1_TRCARCHMIN_Pos) & ETM_TRCID1_TRCARCHMIN_Msk)


#define ETM_TRCID1_TRCARCHMAJ_Pos 8U

#define ETM_TRCID1_TRCARCHMAJ_Msk (0xfUL << ETM_TRCID1_TRCARCHMAJ_Pos)

#define ETM_TRCID1_TRCARCHMAJ(_mrval) ((_mrval << ETM_TRCID1_TRCARCHMAJ_Pos) & ETM_TRCID1_TRCARCHMAJ_Msk)


#define ETM_TRCID1_DESIGNER_Pos 24U

#define ETM_TRCID1_DESIGNER_Msk (0xffUL << ETM_TRCID1_DESIGNER_Pos)

#define ETM_TRCID1_DESIGNER(_mrval) ((_mrval << ETM_TRCID1_DESIGNER_Pos) & ETM_TRCID1_DESIGNER_Msk)


#define ETM_TRCID2_IASIZE_Pos 0U

#define ETM_TRCID2_IASIZE_Msk (0x1fUL << ETM_TRCID2_IASIZE_Pos)

#define ETM_TRCID2_IASIZE(_mrval) ((_mrval << ETM_TRCID2_IASIZE_Pos) & ETM_TRCID2_IASIZE_Msk)


#define ETM_TRCID2_CIDSIZE_Pos 5U

#define ETM_TRCID2_CIDSIZE_Msk (0x1fUL << ETM_TRCID2_CIDSIZE_Pos)

#define ETM_TRCID2_CIDSIZE(_mrval) ((_mrval << ETM_TRCID2_CIDSIZE_Pos) & ETM_TRCID2_CIDSIZE_Msk)


#define ETM_TRCID2_VMIDSIZE_Pos 10U

#define ETM_TRCID2_VMIDSIZE_Msk (0x1fUL << ETM_TRCID2_VMIDSIZE_Pos)

#define ETM_TRCID2_VMIDSIZE(_mrval) ((_mrval << ETM_TRCID2_VMIDSIZE_Pos) & ETM_TRCID2_VMIDSIZE_Msk)


#define ETM_TRCID2_DASIZE_Pos 15U

#define ETM_TRCID2_DASIZE_Msk (0x1fUL << ETM_TRCID2_DASIZE_Pos)

#define ETM_TRCID2_DASIZE(_mrval) ((_mrval << ETM_TRCID2_DASIZE_Pos) & ETM_TRCID2_DASIZE_Msk)


#define ETM_TRCID2_DVSIZE_Pos 20U

#define ETM_TRCID2_DVSIZE_Msk (0x1fUL << ETM_TRCID2_DVSIZE_Pos)

#define ETM_TRCID2_DVSIZE(_mrval) ((_mrval << ETM_TRCID2_DVSIZE_Pos) & ETM_TRCID2_DVSIZE_Msk)


#define ETM_TRCID2_CCSIZE_Pos 25U

#define ETM_TRCID2_CCSIZE_Msk (0xfUL << ETM_TRCID2_CCSIZE_Pos)

#define ETM_TRCID2_CCSIZE(_mrval) ((_mrval << ETM_TRCID2_CCSIZE_Pos) & ETM_TRCID2_CCSIZE_Msk)


#define ETM_TRCID3_CCITMIN_Pos 0U

#define ETM_TRCID3_CCITMIN_Msk (0xfffUL << ETM_TRCID3_CCITMIN_Pos)

#define ETM_TRCID3_CCITMIN(_mrval) ((_mrval << ETM_TRCID3_CCITMIN_Pos) & ETM_TRCID3_CCITMIN_Msk)


#define ETM_TRCID3_EXLEVEL_S_Pos 16U

#define ETM_TRCID3_EXLEVEL_S_Msk (0xfUL << ETM_TRCID3_EXLEVEL_S_Pos)

#define ETM_TRCID3_EXLEVEL_S(_mrval) ((_mrval << ETM_TRCID3_EXLEVEL_S_Pos) & ETM_TRCID3_EXLEVEL_S_Msk)


#define ETM_TRCID3_EXLEVEL_NS_Pos 20U

#define ETM_TRCID3_EXLEVEL_NS_Msk (0xfUL << ETM_TRCID3_EXLEVEL_NS_Pos)

#define ETM_TRCID3_EXLEVEL_NS(_mrval) ((_mrval << ETM_TRCID3_EXLEVEL_NS_Pos) & ETM_TRCID3_EXLEVEL_NS_Msk)


#define ETM_TRCID3_TRCERR_Pos 24U

#define ETM_TRCID3_TRCERR_Msk (0x1UL << ETM_TRCID3_TRCERR_Pos)

#define ETM_TRCID3_TRCERR(_mrval) ((_mrval << ETM_TRCID3_TRCERR_Pos) & ETM_TRCID3_TRCERR_Msk)

#define ETM_TRCID3_TRCERR_NOT_IMPLEMENTED (0x0UL << ETM_TRCID3_TRCERR_Pos)

#define ETM_TRCID3_TRCERR_IMPLEMENTED (0x1UL << ETM_TRCID3_TRCERR_Pos)


#define ETM_TRCID3_SYNCPR_Pos 25U

#define ETM_TRCID3_SYNCPR_Msk (0x1UL << ETM_TRCID3_SYNCPR_Pos)

#define ETM_TRCID3_SYNCPR(_mrval) ((_mrval << ETM_TRCID3_SYNCPR_Pos) & ETM_TRCID3_SYNCPR_Msk)

#define ETM_TRCID3_SYNCPR_WRITABLE (0x0UL << ETM_TRCID3_SYNCPR_Pos)

#define ETM_TRCID3_SYNCPR_READ_ONLY (0x1UL << ETM_TRCID3_SYNCPR_Pos)


#define ETM_TRCID3_STALLCTL_Pos 26U

#define ETM_TRCID3_STALLCTL_Msk (0x1UL << ETM_TRCID3_STALLCTL_Pos)

#define ETM_TRCID3_STALLCTL(_mrval) ((_mrval << ETM_TRCID3_STALLCTL_Pos) & ETM_TRCID3_STALLCTL_Msk)

#define ETM_TRCID3_STALLCTL_NOT_IMPLEMENTED (0x0UL << ETM_TRCID3_STALLCTL_Pos)

#define ETM_TRCID3_STALLCTL_IMPLEMENTED (0x1UL << ETM_TRCID3_STALLCTL_Pos)


#define ETM_TRCID3_SYSSTALL_Pos 27U

#define ETM_TRCID3_SYSSTALL_Msk (0x1UL << ETM_TRCID3_SYSSTALL_Pos)

#define ETM_TRCID3_SYSSTALL(_mrval) ((_mrval << ETM_TRCID3_SYSSTALL_Pos) & ETM_TRCID3_SYSSTALL_Msk)

#define ETM_TRCID3_SYSSTALL_NOT_SUPPORTED (0x0UL << ETM_TRCID3_SYSSTALL_Pos)

#define ETM_TRCID3_SYSSTALL_SUPPORTED (0x1UL << ETM_TRCID3_SYSSTALL_Pos)


#define ETM_TRCID3_NUMPROC_Pos 28U

#define ETM_TRCID3_NUMPROC_Msk (0x7UL << ETM_TRCID3_NUMPROC_Pos)

#define ETM_TRCID3_NUMPROC(_mrval) ((_mrval << ETM_TRCID3_NUMPROC_Pos) & ETM_TRCID3_NUMPROC_Msk)


#define ETM_TRCID3_NOOVERFLOW_Pos 31U

#define ETM_TRCID3_NOOVERFLOW_Msk (0x1UL << ETM_TRCID3_NOOVERFLOW_Pos)

#define ETM_TRCID3_NOOVERFLOW(_mrval) ((_mrval << ETM_TRCID3_NOOVERFLOW_Pos) & ETM_TRCID3_NOOVERFLOW_Msk)

#define ETM_TRCID3_NOOVERFLOW_NOT_IMPLEMENTED (0x0UL << ETM_TRCID3_NOOVERFLOW_Pos)

#define ETM_TRCID3_NOOVERFLOW_IMPLEMENTED (0x1UL << ETM_TRCID3_NOOVERFLOW_Pos)


#define ETM_TRCIDR4_NUMACPAIRS_Pos 0U

#define ETM_TRCIDR4_NUMACPAIRS_Msk (0xfUL << ETM_TRCIDR4_NUMACPAIRS_Pos)

#define ETM_TRCIDR4_NUMACPAIRS(_mrval) ((_mrval << ETM_TRCIDR4_NUMACPAIRS_Pos) & ETM_TRCIDR4_NUMACPAIRS_Msk)


#define ETM_TRCIDR4_NUMDVC_Pos 4U

#define ETM_TRCIDR4_NUMDVC_Msk (0xfUL << ETM_TRCIDR4_NUMDVC_Pos)

#define ETM_TRCIDR4_NUMDVC(_mrval) ((_mrval << ETM_TRCIDR4_NUMDVC_Pos) & ETM_TRCIDR4_NUMDVC_Msk)


#define ETM_TRCIDR4_SUPPDAC_Pos 8U

#define ETM_TRCIDR4_SUPPDAC_Msk (0x1UL << ETM_TRCIDR4_SUPPDAC_Pos)

#define ETM_TRCIDR4_SUPPDAC(_mrval) ((_mrval << ETM_TRCIDR4_SUPPDAC_Pos) & ETM_TRCIDR4_SUPPDAC_Msk)

#define ETM_TRCIDR4_SUPPDAC_NOT_IMPLEMENTED (0x0UL << ETM_TRCIDR4_SUPPDAC_Pos)

#define ETM_TRCIDR4_SUPPDAC_IMPLEMENTED (0x1UL << ETM_TRCIDR4_SUPPDAC_Pos)


#define ETM_TRCIDR4_NUMPC_Pos 12U

#define ETM_TRCIDR4_NUMPC_Msk (0xfUL << ETM_TRCIDR4_NUMPC_Pos)

#define ETM_TRCIDR4_NUMPC(_mrval) ((_mrval << ETM_TRCIDR4_NUMPC_Pos) & ETM_TRCIDR4_NUMPC_Msk)


#define ETM_TRCIDR4_NUMRSPAIR_Pos 16U

#define ETM_TRCIDR4_NUMRSPAIR_Msk (0xfUL << ETM_TRCIDR4_NUMRSPAIR_Pos)

#define ETM_TRCIDR4_NUMRSPAIR(_mrval) ((_mrval << ETM_TRCIDR4_NUMRSPAIR_Pos) & ETM_TRCIDR4_NUMRSPAIR_Msk)


#define ETM_TRCIDR4_NUMSSCC_Pos 20U

#define ETM_TRCIDR4_NUMSSCC_Msk (0xfUL << ETM_TRCIDR4_NUMSSCC_Pos)

#define ETM_TRCIDR4_NUMSSCC(_mrval) ((_mrval << ETM_TRCIDR4_NUMSSCC_Pos) & ETM_TRCIDR4_NUMSSCC_Msk)


#define ETM_TRCIDR4_NUMCIDC_Pos 24U

#define ETM_TRCIDR4_NUMCIDC_Msk (0xfUL << ETM_TRCIDR4_NUMCIDC_Pos)

#define ETM_TRCIDR4_NUMCIDC(_mrval) ((_mrval << ETM_TRCIDR4_NUMCIDC_Pos) & ETM_TRCIDR4_NUMCIDC_Msk)


#define ETM_TRCIDR4_NUMVMIDC_Pos 28U

#define ETM_TRCIDR4_NUMVMIDC_Msk (0xfUL << ETM_TRCIDR4_NUMVMIDC_Pos)

#define ETM_TRCIDR4_NUMVMIDC(_mrval) ((_mrval << ETM_TRCIDR4_NUMVMIDC_Pos) & ETM_TRCIDR4_NUMVMIDC_Msk)


#define ETM_TRCIDR5_NUMEXTIN_Pos 0U

#define ETM_TRCIDR5_NUMEXTIN_Msk (0x1ffUL << ETM_TRCIDR5_NUMEXTIN_Pos)

#define ETM_TRCIDR5_NUMEXTIN(_mrval) ((_mrval << ETM_TRCIDR5_NUMEXTIN_Pos) & ETM_TRCIDR5_NUMEXTIN_Msk)


#define ETM_TRCIDR5_NUMEXTINSEL_Pos 9U

#define ETM_TRCIDR5_NUMEXTINSEL_Msk (0x7UL << ETM_TRCIDR5_NUMEXTINSEL_Pos)

#define ETM_TRCIDR5_NUMEXTINSEL(_mrval) ((_mrval << ETM_TRCIDR5_NUMEXTINSEL_Pos) & ETM_TRCIDR5_NUMEXTINSEL_Msk)


#define ETM_TRCIDR5_TRACEIDSIZE_Pos 16U

#define ETM_TRCIDR5_TRACEIDSIZE_Msk (0x3fUL << ETM_TRCIDR5_TRACEIDSIZE_Pos)

#define ETM_TRCIDR5_TRACEIDSIZE(_mrval) ((_mrval << ETM_TRCIDR5_TRACEIDSIZE_Pos) & ETM_TRCIDR5_TRACEIDSIZE_Msk)


#define ETM_TRCIDR5_ATBTRIG_Pos 22U

#define ETM_TRCIDR5_ATBTRIG_Msk (0x1UL << ETM_TRCIDR5_ATBTRIG_Pos)

#define ETM_TRCIDR5_ATBTRIG(_mrval) ((_mrval << ETM_TRCIDR5_ATBTRIG_Pos) & ETM_TRCIDR5_ATBTRIG_Msk)

#define ETM_TRCIDR5_ATBTRIG_NOT_IMPLEMENTED (0x0UL << ETM_TRCIDR5_ATBTRIG_Pos)

#define ETM_TRCIDR5_ATBTRIG_IMPLEMENTED (0x1UL << ETM_TRCIDR5_ATBTRIG_Pos)


#define ETM_TRCIDR5_LPOVERRIDE_Pos 23U

#define ETM_TRCIDR5_LPOVERRIDE_Msk (0x1UL << ETM_TRCIDR5_LPOVERRIDE_Pos)

#define ETM_TRCIDR5_LPOVERRIDE(_mrval) ((_mrval << ETM_TRCIDR5_LPOVERRIDE_Pos) & ETM_TRCIDR5_LPOVERRIDE_Msk)

#define ETM_TRCIDR5_LPOVERRIDE_NOT_IMPLEMENTED (0x0UL << ETM_TRCIDR5_LPOVERRIDE_Pos)

#define ETM_TRCIDR5_LPOVERRIDE_IMPLEMENTED (0x1UL << ETM_TRCIDR5_LPOVERRIDE_Pos)


#define ETM_TRCIDR5_NUMSEQSTATE_Pos 25U

#define ETM_TRCIDR5_NUMSEQSTATE_Msk (0x7UL << ETM_TRCIDR5_NUMSEQSTATE_Pos)

#define ETM_TRCIDR5_NUMSEQSTATE(_mrval) ((_mrval << ETM_TRCIDR5_NUMSEQSTATE_Pos) & ETM_TRCIDR5_NUMSEQSTATE_Msk)


#define ETM_TRCIDR5_NUMCNTR_Pos 28U

#define ETM_TRCIDR5_NUMCNTR_Msk (0x7UL << ETM_TRCIDR5_NUMCNTR_Pos)

#define ETM_TRCIDR5_NUMCNTR(_mrval) ((_mrval << ETM_TRCIDR5_NUMCNTR_Pos) & ETM_TRCIDR5_NUMCNTR_Msk)


#define ETM_TRCIDR5_REDFUNCNTR_Pos 31U

#define ETM_TRCIDR5_REDFUNCNTR_Msk (0x1UL << ETM_TRCIDR5_REDFUNCNTR_Pos)

#define ETM_TRCIDR5_REDFUNCNTR(_mrval) ((_mrval << ETM_TRCIDR5_REDFUNCNTR_Pos) & ETM_TRCIDR5_REDFUNCNTR_Msk)

#define ETM_TRCIDR5_REDFUNCNTR_NOT_IMPLEMENTED (0x0UL << ETM_TRCIDR5_REDFUNCNTR_Pos)

#define ETM_TRCIDR5_REDFUNCNTR_INST_ONLY (0x1UL << ETM_TRCIDR5_REDFUNCNTR_Pos)


#define ETM_TRCRSCTLR_SELECT_Pos 0U

#define ETM_TRCRSCTLR_SELECT_Msk (0xffUL << ETM_TRCRSCTLR_SELECT_Pos)

#define ETM_TRCRSCTLR_SELECT(_mrval) ((_mrval << ETM_TRCRSCTLR_SELECT_Pos) & ETM_TRCRSCTLR_SELECT_Msk)


#define ETM_TRCRSCTLR_GROUP_Pos 16U

#define ETM_TRCRSCTLR_GROUP_Msk (0x7UL << ETM_TRCRSCTLR_GROUP_Pos)

#define ETM_TRCRSCTLR_GROUP(_mrval) ((_mrval << ETM_TRCRSCTLR_GROUP_Pos) & ETM_TRCRSCTLR_GROUP_Msk)


#define ETM_TRCRSCTLR_INV_Pos 20U

#define ETM_TRCRSCTLR_INV_Msk (0x1UL << ETM_TRCRSCTLR_INV_Pos)

#define ETM_TRCRSCTLR_INV(_mrval) ((_mrval << ETM_TRCRSCTLR_INV_Pos) & ETM_TRCRSCTLR_INV_Msk)

#define ETM_TRCRSCTLR_INV_NOT_INVERTED (0x0UL << ETM_TRCRSCTLR_INV_Pos)

#define ETM_TRCRSCTLR_INV_INVERTED (0x1UL << ETM_TRCRSCTLR_INV_Pos)


#define ETM_TRCRSCTLR_PAIRINV_Pos 21U

#define ETM_TRCRSCTLR_PAIRINV_Msk (0x1UL << ETM_TRCRSCTLR_PAIRINV_Pos)

#define ETM_TRCRSCTLR_PAIRINV(_mrval) ((_mrval << ETM_TRCRSCTLR_PAIRINV_Pos) & ETM_TRCRSCTLR_PAIRINV_Msk)

#define ETM_TRCRSCTLR_PAIRINV_NOT_INVERTED (0x0UL << ETM_TRCRSCTLR_PAIRINV_Pos)

#define ETM_TRCRSCTLR_PAIRINV_INVERTED (0x1UL << ETM_TRCRSCTLR_PAIRINV_Pos)


#define ETM_TRCSSCCR0_SAC_Pos 0U

#define ETM_TRCSSCCR0_SAC_Msk (0xffUL << ETM_TRCSSCCR0_SAC_Pos)

#define ETM_TRCSSCCR0_SAC(_mrval) ((_mrval << ETM_TRCSSCCR0_SAC_Pos) & ETM_TRCSSCCR0_SAC_Msk)


#define ETM_TRCSSCCR0_ARC_Pos 16U

#define ETM_TRCSSCCR0_ARC_Msk (0x7UL << ETM_TRCSSCCR0_ARC_Pos)

#define ETM_TRCSSCCR0_ARC(_mrval) ((_mrval << ETM_TRCSSCCR0_ARC_Pos) & ETM_TRCSSCCR0_ARC_Msk)


#define ETM_TRCSSCCR0_RST_Pos 24U

#define ETM_TRCSSCCR0_RST_Msk (0x1UL << ETM_TRCSSCCR0_RST_Pos)

#define ETM_TRCSSCCR0_RST(_mrval) ((_mrval << ETM_TRCSSCCR0_RST_Pos) & ETM_TRCSSCCR0_RST_Msk)


#define ETM_TRCSSCSR0_INST_Pos 0U

#define ETM_TRCSSCSR0_INST_Msk (0x1UL << ETM_TRCSSCSR0_INST_Pos)

#define ETM_TRCSSCSR0_INST(_mrval) ((_mrval << ETM_TRCSSCSR0_INST_Pos) & ETM_TRCSSCSR0_INST_Msk)

#define ETM_TRCSSCSR0_INST_NOT_SUPPORTED (0x0UL << ETM_TRCSSCSR0_INST_Pos)

#define ETM_TRCSSCSR0_INST_SUPPORTED (0x1UL << ETM_TRCSSCSR0_INST_Pos)


#define ETM_TRCSSCSR0_DA_Pos 1U

#define ETM_TRCSSCSR0_DA_Msk (0x1UL << ETM_TRCSSCSR0_DA_Pos)

#define ETM_TRCSSCSR0_DA(_mrval) ((_mrval << ETM_TRCSSCSR0_DA_Pos) & ETM_TRCSSCSR0_DA_Msk)

#define ETM_TRCSSCSR0_DA_NOT_SUPPORTED (0x0UL << ETM_TRCSSCSR0_DA_Pos)

#define ETM_TRCSSCSR0_DA_SUPPORTED (0x1UL << ETM_TRCSSCSR0_DA_Pos)


#define ETM_TRCSSCSR0_DV_Pos 2U

#define ETM_TRCSSCSR0_DV_Msk (0x1UL << ETM_TRCSSCSR0_DV_Pos)

#define ETM_TRCSSCSR0_DV(_mrval) ((_mrval << ETM_TRCSSCSR0_DV_Pos) & ETM_TRCSSCSR0_DV_Msk)

#define ETM_TRCSSCSR0_DV_NOT_SUPPORTED (0x0UL << ETM_TRCSSCSR0_DV_Pos)

#define ETM_TRCSSCSR0_DV_SUPPORTED (0x1UL << ETM_TRCSSCSR0_DV_Pos)


#define ETM_TRCSSCSR0_PC_Pos 3U

#define ETM_TRCSSCSR0_PC_Msk (0x1UL << ETM_TRCSSCSR0_PC_Pos)

#define ETM_TRCSSCSR0_PC(_mrval) ((_mrval << ETM_TRCSSCSR0_PC_Pos) & ETM_TRCSSCSR0_PC_Msk)

#define ETM_TRCSSCSR0_PC_NOT_SUPPORTED (0x0UL << ETM_TRCSSCSR0_PC_Pos)

#define ETM_TRCSSCSR0_PC_SUPPORTED (0x1UL << ETM_TRCSSCSR0_PC_Pos)


#define ETM_TRCSSCSR0_STATUS_Pos 31U

#define ETM_TRCSSCSR0_STATUS_Msk (0x1UL << ETM_TRCSSCSR0_STATUS_Pos)

#define ETM_TRCSSCSR0_STATUS(_mrval) ((_mrval << ETM_TRCSSCSR0_STATUS_Pos) & ETM_TRCSSCSR0_STATUS_Msk)

#define ETM_TRCSSCSR0_STATUS_NO_MATCH (0x0UL << ETM_TRCSSCSR0_STATUS_Pos)

#define ETM_TRCSSCSR0_STATUS_MATCHED (0x1UL << ETM_TRCSSCSR0_STATUS_Pos)


#define ETM_TRCSSPCICR0_PC_Pos 0U

#define ETM_TRCSSPCICR0_PC_Msk (0xfUL << ETM_TRCSSPCICR0_PC_Pos)

#define ETM_TRCSSPCICR0_PC(_mrval) ((_mrval << ETM_TRCSSPCICR0_PC_Pos) & ETM_TRCSSPCICR0_PC_Msk)


#define ETM_TRCOSLSR_OSLM0_Pos 0U

#define ETM_TRCOSLSR_OSLM0_Msk (0x1UL << ETM_TRCOSLSR_OSLM0_Pos)

#define ETM_TRCOSLSR_OSLM0(_mrval) ((_mrval << ETM_TRCOSLSR_OSLM0_Pos) & ETM_TRCOSLSR_OSLM0_Msk)


#define ETM_TRCOSLSR_OSLK_Pos 1U

#define ETM_TRCOSLSR_OSLK_Msk (0x1UL << ETM_TRCOSLSR_OSLK_Pos)

#define ETM_TRCOSLSR_OSLK(_mrval) ((_mrval << ETM_TRCOSLSR_OSLK_Pos) & ETM_TRCOSLSR_OSLK_Msk)


#define ETM_TRCOSLSR_NTT_Pos 2U

#define ETM_TRCOSLSR_NTT_Msk (0x1UL << ETM_TRCOSLSR_NTT_Pos)

#define ETM_TRCOSLSR_NTT(_mrval) ((_mrval << ETM_TRCOSLSR_NTT_Pos) & ETM_TRCOSLSR_NTT_Msk)


#define ETM_TRCOSLSR_OSLM1_Pos 3U

#define ETM_TRCOSLSR_OSLM1_Msk (0x1UL << ETM_TRCOSLSR_OSLM1_Pos)

#define ETM_TRCOSLSR_OSLM1(_mrval) ((_mrval << ETM_TRCOSLSR_OSLM1_Pos) & ETM_TRCOSLSR_OSLM1_Msk)


#define ETM_TRCPDCR_PU_Pos 3U

#define ETM_TRCPDCR_PU_Msk (0x1UL << ETM_TRCPDCR_PU_Pos)

#define ETM_TRCPDCR_PU(_mrval) ((_mrval << ETM_TRCPDCR_PU_Pos) & ETM_TRCPDCR_PU_Msk)

#define ETM_TRCPDCR_PU_NOT_REQUESTED (0x0UL << ETM_TRCPDCR_PU_Pos)

#define ETM_TRCPDCR_PU_REQUESTED (0x1UL << ETM_TRCPDCR_PU_Pos)


#define ETM_TRCPDSR_POWER_Pos 0U

#define ETM_TRCPDSR_POWER_Msk (0x1UL << ETM_TRCPDSR_POWER_Pos)

#define ETM_TRCPDSR_POWER(_mrval) ((_mrval << ETM_TRCPDSR_POWER_Pos) & ETM_TRCPDSR_POWER_Msk)

#define ETM_TRCPDSR_POWER_OFF (0x0UL << ETM_TRCPDSR_POWER_Pos)

#define ETM_TRCPDSR_POWER_ON (0x1UL << ETM_TRCPDSR_POWER_Pos)


#define ETM_TRCPDSR_STICKYPD_Pos 1U

#define ETM_TRCPDSR_STICKYPD_Msk (0x1UL << ETM_TRCPDSR_STICKYPD_Pos)

#define ETM_TRCPDSR_STICKYPD(_mrval) ((_mrval << ETM_TRCPDSR_STICKYPD_Pos) & ETM_TRCPDSR_STICKYPD_Msk)

#define ETM_TRCPDSR_STICKYPD_UNCHANGED (0x0UL << ETM_TRCPDSR_STICKYPD_Pos)

#define ETM_TRCPDSR_STICKYPD_TURNED_OFF (0x1UL << ETM_TRCPDSR_STICKYPD_Pos)


#define ETM_TRCACVR_ADDRESS_Pos 0U

#define ETM_TRCACVR_ADDRESS_Msk (0xffffffffUL << ETM_TRCACVR_ADDRESS_Pos)

#define ETM_TRCACVR_ADDRESS(_mrval) ((_mrval << ETM_TRCACVR_ADDRESS_Pos) & ETM_TRCACVR_ADDRESS_Msk)


#define ETM_TRCACATR0_TYPE_Pos 0U

#define ETM_TRCACATR0_TYPE_Msk (0x3UL << ETM_TRCACATR0_TYPE_Pos)

#define ETM_TRCACATR0_TYPE(_mrval) ((_mrval << ETM_TRCACATR0_TYPE_Pos) & ETM_TRCACATR0_TYPE_Msk)

#define ETM_TRCACATR0_TYPE_INST (0x0UL << ETM_TRCACATR0_TYPE_Pos)

#define ETM_TRCACATR0_TYPE_LOAD (0x1UL << ETM_TRCACATR0_TYPE_Pos)

#define ETM_TRCACATR0_TYPE_STORE (0x2UL << ETM_TRCACATR0_TYPE_Pos)

#define ETM_TRCACATR0_TYPE_LOAD_STORE (0x3UL << ETM_TRCACATR0_TYPE_Pos)


#define ETM_TRCACATR0_CONTEXTTYPE_Pos 2U

#define ETM_TRCACATR0_CONTEXTTYPE_Msk (0x1UL << ETM_TRCACATR0_CONTEXTTYPE_Pos)

#define ETM_TRCACATR0_CONTEXTTYPE(_mrval) ((_mrval << ETM_TRCACATR0_CONTEXTTYPE_Pos) & ETM_TRCACATR0_CONTEXTTYPE_Msk)

#define ETM_TRCACATR0_CONTEXTTYPE_NOT_SUPPORTED (0x0UL << ETM_TRCACATR0_CONTEXTTYPE_Pos)

#define ETM_TRCACATR0_CONTEXTTYPE_SUPPORTED (0x1UL << ETM_TRCACATR0_CONTEXTTYPE_Pos)


#define ETM_TRCACATR0_EXLEVEL_S0_Pos 8U

#define ETM_TRCACATR0_EXLEVEL_S0_Msk (0x1UL << ETM_TRCACATR0_EXLEVEL_S0_Pos)

#define ETM_TRCACATR0_EXLEVEL_S0(_mrval) ((_mrval << ETM_TRCACATR0_EXLEVEL_S0_Pos) & ETM_TRCACATR0_EXLEVEL_S0_Msk)

#define ETM_TRCACATR0_EXLEVEL_S0_MATCH (0x0UL << ETM_TRCACATR0_EXLEVEL_S0_Pos)

#define ETM_TRCACATR0_EXLEVEL_S0_DONT_MATCH (0x1UL << ETM_TRCACATR0_EXLEVEL_S0_Pos)


#define ETM_TRCACATR0_EXLEVEL_S3_Pos 11U

#define ETM_TRCACATR0_EXLEVEL_S3_Msk (0x1UL << ETM_TRCACATR0_EXLEVEL_S3_Pos)

#define ETM_TRCACATR0_EXLEVEL_S3(_mrval) ((_mrval << ETM_TRCACATR0_EXLEVEL_S3_Pos) & ETM_TRCACATR0_EXLEVEL_S3_Msk)

#define ETM_TRCACATR0_EXLEVEL_S3_MATCH (0x0UL << ETM_TRCACATR0_EXLEVEL_S3_Pos)

#define ETM_TRCACATR0_EXLEVEL_S3_DONT_MATCH (0x1UL << ETM_TRCACATR0_EXLEVEL_S3_Pos)


#define ETM_TRCACATR0_DATAMATCH_Pos 16U

#define ETM_TRCACATR0_DATAMATCH_Msk (0x3UL << ETM_TRCACATR0_DATAMATCH_Pos)

#define ETM_TRCACATR0_DATAMATCH(_mrval) ((_mrval << ETM_TRCACATR0_DATAMATCH_Pos) & ETM_TRCACATR0_DATAMATCH_Msk)

#define ETM_TRCACATR0_DATAMATCH_VAL_MATCH (0x1UL << ETM_TRCACATR0_DATAMATCH_Pos)

#define ETM_TRCACATR0_DATAMATCH_VAL_NO_MATCH (0x3UL << ETM_TRCACATR0_DATAMATCH_Pos)


#define ETM_TRCACATR0_DATASIZE_Pos 18U

#define ETM_TRCACATR0_DATASIZE_Msk (0x3UL << ETM_TRCACATR0_DATASIZE_Pos)

#define ETM_TRCACATR0_DATASIZE(_mrval) ((_mrval << ETM_TRCACATR0_DATASIZE_Pos) & ETM_TRCACATR0_DATASIZE_Msk)

#define ETM_TRCACATR0_DATASIZE_BYTE (0x0UL << ETM_TRCACATR0_DATASIZE_Pos)

#define ETM_TRCACATR0_DATASIZE_HALF (0x1UL << ETM_TRCACATR0_DATASIZE_Pos)

#define ETM_TRCACATR0_DATASIZE_WORD (0x2UL << ETM_TRCACATR0_DATASIZE_Pos)

#define ETM_TRCACATR0_DATASIZE_DWORD (0x3UL << ETM_TRCACATR0_DATASIZE_Pos)


#define ETM_TRCACATR0_DATARANGE_Pos 20U

#define ETM_TRCACATR0_DATARANGE_Msk (0x1UL << ETM_TRCACATR0_DATARANGE_Pos)

#define ETM_TRCACATR0_DATARANGE(_mrval) ((_mrval << ETM_TRCACATR0_DATARANGE_Pos) & ETM_TRCACATR0_DATARANGE_Msk)

#define ETM_TRCACATR0_DATARANGE_SINGLE_ADDR (0x0UL << ETM_TRCACATR0_DATARANGE_Pos)

#define ETM_TRCACATR0_DATARANGE_ADDR_RANGE (0x1UL << ETM_TRCACATR0_DATARANGE_Pos)


#define ETM_TRCACATR1_TYPE_Pos 0U

#define ETM_TRCACATR1_TYPE_Msk (0x3UL << ETM_TRCACATR1_TYPE_Pos)

#define ETM_TRCACATR1_TYPE(_mrval) ((_mrval << ETM_TRCACATR1_TYPE_Pos) & ETM_TRCACATR1_TYPE_Msk)

#define ETM_TRCACATR1_TYPE_INST (0x0UL << ETM_TRCACATR1_TYPE_Pos)

#define ETM_TRCACATR1_TYPE_LOAD (0x1UL << ETM_TRCACATR1_TYPE_Pos)

#define ETM_TRCACATR1_TYPE_STORE (0x2UL << ETM_TRCACATR1_TYPE_Pos)

#define ETM_TRCACATR1_TYPE_LOAD_STORE (0x3UL << ETM_TRCACATR1_TYPE_Pos)


#define ETM_TRCACATR1_CONTEXTTYPE_Pos 2U

#define ETM_TRCACATR1_CONTEXTTYPE_Msk (0x1UL << ETM_TRCACATR1_CONTEXTTYPE_Pos)

#define ETM_TRCACATR1_CONTEXTTYPE(_mrval) ((_mrval << ETM_TRCACATR1_CONTEXTTYPE_Pos) & ETM_TRCACATR1_CONTEXTTYPE_Msk)

#define ETM_TRCACATR1_CONTEXTTYPE_NOT_SUPPORTED (0x0UL << ETM_TRCACATR1_CONTEXTTYPE_Pos)

#define ETM_TRCACATR1_CONTEXTTYPE_SUPPORTED (0x1UL << ETM_TRCACATR1_CONTEXTTYPE_Pos)


#define ETM_TRCACATR1_EXLEVEL_S0_Pos 8U

#define ETM_TRCACATR1_EXLEVEL_S0_Msk (0x1UL << ETM_TRCACATR1_EXLEVEL_S0_Pos)

#define ETM_TRCACATR1_EXLEVEL_S0(_mrval) ((_mrval << ETM_TRCACATR1_EXLEVEL_S0_Pos) & ETM_TRCACATR1_EXLEVEL_S0_Msk)

#define ETM_TRCACATR1_EXLEVEL_S0_MATCH (0x0UL << ETM_TRCACATR1_EXLEVEL_S0_Pos)

#define ETM_TRCACATR1_EXLEVEL_S0_DONT_MATCH (0x1UL << ETM_TRCACATR1_EXLEVEL_S0_Pos)


#define ETM_TRCACATR1_EXLEVEL_S3_Pos 11U

#define ETM_TRCACATR1_EXLEVEL_S3_Msk (0x1UL << ETM_TRCACATR1_EXLEVEL_S3_Pos)

#define ETM_TRCACATR1_EXLEVEL_S3(_mrval) ((_mrval << ETM_TRCACATR1_EXLEVEL_S3_Pos) & ETM_TRCACATR1_EXLEVEL_S3_Msk)

#define ETM_TRCACATR1_EXLEVEL_S3_MATCH (0x0UL << ETM_TRCACATR1_EXLEVEL_S3_Pos)

#define ETM_TRCACATR1_EXLEVEL_S3_DONT_MATCH (0x1UL << ETM_TRCACATR1_EXLEVEL_S3_Pos)


#define ETM_TRCDVCVR_VALUE_Pos 0U

#define ETM_TRCDVCVR_VALUE_Msk (0xffffffffUL << ETM_TRCDVCVR_VALUE_Pos)

#define ETM_TRCDVCVR_VALUE(_mrval) ((_mrval << ETM_TRCDVCVR_VALUE_Pos) & ETM_TRCDVCVR_VALUE_Msk)


#define ETM_TRCDVCMR_MASK_Pos 0U

#define ETM_TRCDVCMR_MASK_Msk (0xffffffffUL << ETM_TRCDVCMR_MASK_Pos)

#define ETM_TRCDVCMR_MASK(_mrval) ((_mrval << ETM_TRCDVCMR_MASK_Pos) & ETM_TRCDVCMR_MASK_Msk)


#define ETM_TRCCLAIMSET_SET_Pos 0U

#define ETM_TRCCLAIMSET_SET_Msk (0xfUL << ETM_TRCCLAIMSET_SET_Pos)

#define ETM_TRCCLAIMSET_SET(_mrval) ((_mrval << ETM_TRCCLAIMSET_SET_Pos) & ETM_TRCCLAIMSET_SET_Msk)


#define ETM_TRCCLAIMCLR_CLR_Pos 0U

#define ETM_TRCCLAIMCLR_CLR_Msk (0xfUL << ETM_TRCCLAIMCLR_CLR_Pos)

#define ETM_TRCCLAIMCLR_CLR(_mrval) ((_mrval << ETM_TRCCLAIMCLR_CLR_Pos) & ETM_TRCCLAIMCLR_CLR_Msk)


#define ETM_TRCLAR_KEY_Pos 0U

#define ETM_TRCLAR_KEY_Msk (0xffffffffUL << ETM_TRCLAR_KEY_Pos)

#define ETM_TRCLAR_KEY(_mrval) ((_mrval << ETM_TRCLAR_KEY_Pos) & ETM_TRCLAR_KEY_Msk)

#define ETM_TRCLAR_KEY_UNLOCK (0xc5acce55UL << ETM_TRCLAR_KEY_Pos)


#define ETM_TRCLSR_SLI_Pos 0U

#define ETM_TRCLSR_SLI_Msk (0x1UL << ETM_TRCLSR_SLI_Pos)

#define ETM_TRCLSR_SLI(_mrval) ((_mrval << ETM_TRCLSR_SLI_Pos) & ETM_TRCLSR_SLI_Msk)


#define ETM_TRCLSR_SLK_Pos 1U

#define ETM_TRCLSR_SLK_Msk (0x1UL << ETM_TRCLSR_SLK_Pos)

#define ETM_TRCLSR_SLK(_mrval) ((_mrval << ETM_TRCLSR_SLK_Pos) & ETM_TRCLSR_SLK_Msk)

#define ETM_TRCLSR_SLK_IS_CLEAR (0x0UL << ETM_TRCLSR_SLK_Pos)

#define ETM_TRCLSR_SLK_IS_SET (0x1UL << ETM_TRCLSR_SLK_Pos)


#define ETM_TRCLSR_NTT_Pos 2U

#define ETM_TRCLSR_NTT_Msk (0x1UL << ETM_TRCLSR_NTT_Pos)

#define ETM_TRCLSR_NTT(_mrval) ((_mrval << ETM_TRCLSR_NTT_Pos) & ETM_TRCLSR_NTT_Msk)


#define ETM_TRCAUTHSTATUS_NSID_Pos 0U

#define ETM_TRCAUTHSTATUS_NSID_Msk (0x3UL << ETM_TRCAUTHSTATUS_NSID_Pos)

#define ETM_TRCAUTHSTATUS_NSID(_mrval) ((_mrval << ETM_TRCAUTHSTATUS_NSID_Pos) & ETM_TRCAUTHSTATUS_NSID_Msk)


#define ETM_TRCAUTHSTATUS_NSNID_Pos 2U

#define ETM_TRCAUTHSTATUS_NSNID_Msk (0x3UL << ETM_TRCAUTHSTATUS_NSNID_Pos)

#define ETM_TRCAUTHSTATUS_NSNID(_mrval) ((_mrval << ETM_TRCAUTHSTATUS_NSNID_Pos) & ETM_TRCAUTHSTATUS_NSNID_Msk)


#define ETM_TRCAUTHSTATUS_SID_Pos 4U

#define ETM_TRCAUTHSTATUS_SID_Msk (0x3UL << ETM_TRCAUTHSTATUS_SID_Pos)

#define ETM_TRCAUTHSTATUS_SID(_mrval) ((_mrval << ETM_TRCAUTHSTATUS_SID_Pos) & ETM_TRCAUTHSTATUS_SID_Msk)


#define ETM_TRCAUTHSTATUS_SNID_Pos 6U

#define ETM_TRCAUTHSTATUS_SNID_Msk (0x3UL << ETM_TRCAUTHSTATUS_SNID_Pos)

#define ETM_TRCAUTHSTATUS_SNID(_mrval) ((_mrval << ETM_TRCAUTHSTATUS_SNID_Pos) & ETM_TRCAUTHSTATUS_SNID_Msk)


#define ETM_TRCDEVARCH_ARCHID_Pos 0U

#define ETM_TRCDEVARCH_ARCHID_Msk (0xffffUL << ETM_TRCDEVARCH_ARCHID_Pos)

#define ETM_TRCDEVARCH_ARCHID(_mrval) ((_mrval << ETM_TRCDEVARCH_ARCHID_Pos) & ETM_TRCDEVARCH_ARCHID_Msk)

#define ETM_TRCDEVARCH_ARCHID_ETMv4 (0x4a13UL << ETM_TRCDEVARCH_ARCHID_Pos)


#define ETM_TRCDEVARCH_REVISION_Pos 16U

#define ETM_TRCDEVARCH_REVISION_Msk (0xfUL << ETM_TRCDEVARCH_REVISION_Pos)

#define ETM_TRCDEVARCH_REVISION(_mrval) ((_mrval << ETM_TRCDEVARCH_REVISION_Pos) & ETM_TRCDEVARCH_REVISION_Msk)


#define ETM_TRCDEVARCH_PRESENT_Pos 20U

#define ETM_TRCDEVARCH_PRESENT_Msk (0x1UL << ETM_TRCDEVARCH_PRESENT_Pos)

#define ETM_TRCDEVARCH_PRESENT(_mrval) ((_mrval << ETM_TRCDEVARCH_PRESENT_Pos) & ETM_TRCDEVARCH_PRESENT_Msk)

#define ETM_TRCDEVARCH_PRESENT_NOT_PRESENT (0x0UL << ETM_TRCDEVARCH_PRESENT_Pos)

#define ETM_TRCDEVARCH_PRESENT_IS_PRESENT (0x1UL << ETM_TRCDEVARCH_PRESENT_Pos)


#define ETM_TRCDEVARCH_ARCHITECT_Pos 21U

#define ETM_TRCDEVARCH_ARCHITECT_Msk (0x7ffUL << ETM_TRCDEVARCH_ARCHITECT_Pos)

#define ETM_TRCDEVARCH_ARCHITECT(_mrval) ((_mrval << ETM_TRCDEVARCH_ARCHITECT_Pos) & ETM_TRCDEVARCH_ARCHITECT_Msk)

#define ETM_TRCDEVARCH_ARCHITECT_ARM (0x23bUL << ETM_TRCDEVARCH_ARCHITECT_Pos)


#define ETM_TRCDEVTYPE_MAJOR_Pos 0U

#define ETM_TRCDEVTYPE_MAJOR_Msk (0xfUL << ETM_TRCDEVTYPE_MAJOR_Pos)

#define ETM_TRCDEVTYPE_MAJOR(_mrval) ((_mrval << ETM_TRCDEVTYPE_MAJOR_Pos) & ETM_TRCDEVTYPE_MAJOR_Msk)

#define ETM_TRCDEVTYPE_MAJOR_TRACE_SOURCE (0x3UL << ETM_TRCDEVTYPE_MAJOR_Pos)


#define ETM_TRCDEVTYPE_SUB_Pos 4U

#define ETM_TRCDEVTYPE_SUB_Msk (0xfUL << ETM_TRCDEVTYPE_SUB_Pos)

#define ETM_TRCDEVTYPE_SUB(_mrval) ((_mrval << ETM_TRCDEVTYPE_SUB_Pos) & ETM_TRCDEVTYPE_SUB_Msk)

#define ETM_TRCDEVTYPE_SUB_PROCESSOR_TRACE (0x1UL << ETM_TRCDEVTYPE_SUB_Pos)