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ether_phy_ksz9893_regs.h
1#define KSZ98XX_MAX_PORTS 8
2
3struct global_control_t {
4 uint8_t CHIP_ID0; /* Address: 0x00-0x00 */
5 uint8_t CHIP_ID1; /* Address: 0x01-0x01 */
6 uint8_t CHIP_ID2; /* Address: 0x02-0x02 */
7 uint8_t CHIP_ID3; /* Address: 0x03-0x03 */
8 uint8_t RESERVED0[0x02]; /* Address: 0x04-0x05 */
9 uint8_t PME_CTRL; /* Address: 0x06-0x06 */
10 uint8_t RESERVED1[0x08]; /* Address: 0x07-0x0E */
11 uint8_t GLOBAL_OPTIONS; /* Address: 0x0F-0x0F */
12 beuint32_t GLOBAL_INT_STATUS; /* Address: 0x10-0x13 */
13 beuint32_t GLOBAL_INT_MASK; /* Address: 0x14-0x17 */
14 beuint32_t PORT_INT_STATUS; /* Address: 0x18-0x1B */
15 beuint32_t PORT_INT_MASK; /* Address: 0x1C-0x1F */
16 beuint32_t PHY_INT_STATUS; /* Address: 0x20-0x23 */
17 beuint32_t PHY_INT_MASK; /* Address: 0x24-0x27 */
18 uint8_t RESERVED2[0xD8]; /* Address: 0x28-0xFF */
19
20} __attribute__((packed));
21
22struct global_io_control_t {
23 uint8_t SERIAL_IO_CTRL; /* Address: 0x100-0x100 */
24 uint8_t RESERVED0[0x02]; /* Address: 0x101-0x102 */
25 uint8_t OUTPUT_CLOCK_CTRL; /* Address: 0x103-0x103 */
26 beuint32_t IBA_CTRL; /* Address: 0x104-0x107 */
27 beuint32_t APB_TIMEOUT; /* Address: 0x108-0x10B */
28 uint8_t IBA_SYNC; /* Address: 0x10C-0x10C */
29 uint8_t IO_DRIVE_STRENGTH; /* Address: 0x10D-0x10D */
30 uint8_t RESERVED1[0x02]; /* Address: 0x10E-0x10F */
31 beuint32_t IBA_STATUS; /* Address: 0x110-0x113 */
32 beuint32_t IBA_STATES; /* Address: 0x114-0x117 */
33 beuint32_t IBA_RESULT; /* Address: 0x118-0x11B */
34 uint8_t RESERVED2[0x04]; /* Address: 0x11C-0x11F */
35 beuint32_t LED_OVERRIDE; /* Address: 0x120-0x123 */
36 beuint32_t LED_OUTPUT; /* Address: 0x124-0x127 */
37 uint8_t RESERVED3[0xD8]; /* Address: 0x128-0x1FF */
38
39} __attribute__((packed));
40
41struct global_phy_control_t {
42 uint8_t RESERVED0[0x01]; /* Address: 0x200-0x200 */
43 uint8_t POWER_MANAGEMENT_CTRL; /* Address: 0x201-0x201 */
44 uint8_t RESERVED1[0x0E]; /* Address: 0x202-0x20F */
45 beuint32_t LED_STRAP; /* Address: 0x210-0x213 */
46 uint8_t RESERVED2[0xEC]; /* Address: 0x214-0x2FF */
47
48} __attribute__((packed));
49
50struct global_switch_control_t {
51 uint8_t SW_OPERATION; /* Address: 0x300-0x300 */
52 uint8_t RESERVED0[0x01]; /* Address: 0x301-0x301 */
53 uint8_t SW_MAC_ADDR_0; /* Address: 0x302-0x302 */
54 uint8_t SW_MAC_ADDR_1; /* Address: 0x303-0x303 */
55 uint8_t SW_MAC_ADDR_2; /* Address: 0x304-0x304 */
56 uint8_t SW_MAC_ADDR_3; /* Address: 0x305-0x305 */
57 uint8_t SW_MAC_ADDR_4; /* Address: 0x306-0x306 */
58 uint8_t SW_MAC_ADDR_5; /* Address: 0x307-0x307 */
59 beuint16_t SW_MTU; /* Address: 0x308-0x309 */
60 beuint16_t SW_ISP_TPID; /* Address: 0x30A-0x30B */
61 beuint16_t SW_HSR_TPID; /* Address: 0x30C-0x30D */
62 beuint16_t SW_AVB_STRATEGY; /* Address: 0x30E-0x30F */
63 beuint32_t SW_LUE_CTRL; /* Address: 0x310-0x313 */
64 uint8_t SW_LUE_INT_STATUS; /* Address: 0x314-0x314 */
65 uint8_t SW_LUE_INT_MASK; /* Address: 0x315-0x315 */
66 beuint16_t SW_LUE_INDEX_WRITE; /* Address: 0x316-0x317 */
67 beuint16_t SW_LUE_INDEX_LEARN; /* Address: 0x318-0x319 */
68 beuint16_t SW_LUE_INDEX_CPU; /* Address: 0x31A-0x31B */
69 uint8_t RESERVED1[0x04]; /* Address: 0x31C-0x31F */
70 beuint32_t SW_UNK_UCAST_CTRL; /* Address: 0x320-0x323 */
71 beuint32_t SW_UNK_MCAST_CTRL; /* Address: 0x324-0x327 */
72 beuint32_t SW_UNK_VID_CTRL; /* Address: 0x328-0x32B */
73 uint8_t RESERVED2[0x04]; /* Address: 0x32C-0x32F */
74 beuint32_t SW_MAC_CTRL; /* Address: 0x330-0x333 */
75 beuint32_t SW_MAC_CTRL2; /* Address: 0x334-0x337 */
76 beuint32_t SW_MAC_802_1P_MAP; /* Address: 0x338-0x33B */
77 uint8_t RESERVED3[0x02]; /* Address: 0x33C-0x33D */
78 uint8_t SW_MAC_TOS_CTRL; /* Address: 0x33E-0x33E */
79 uint8_t RESERVED4[0x01]; /* Address: 0x33F-0x33F */
80 uint8_t SW_MAC_TOS_PRIO_0; /* Address: 0x340-0x340 */
81 uint8_t SW_MAC_TOS_PRIO_1; /* Address: 0x341-0x341 */
82 uint8_t SW_MAC_TOS_PRIO_2; /* Address: 0x342-0x342 */
83 uint8_t SW_MAC_TOS_PRIO_3; /* Address: 0x343-0x343 */
84 uint8_t SW_MAC_TOS_PRIO_4; /* Address: 0x344-0x344 */
85 uint8_t SW_MAC_TOS_PRIO_5; /* Address: 0x345-0x345 */
86 uint8_t SW_MAC_TOS_PRIO_6; /* Address: 0x346-0x346 */
87 uint8_t SW_MAC_TOS_PRIO_7; /* Address: 0x347-0x347 */
88 uint8_t SW_MAC_TOS_PRIO_8; /* Address: 0x348-0x348 */
89 uint8_t SW_MAC_TOS_PRIO_9; /* Address: 0x349-0x349 */
90 uint8_t SW_MAC_TOS_PRIO_10; /* Address: 0x34A-0x34A */
91 uint8_t SW_MAC_TOS_PRIO_11; /* Address: 0x34B-0x34B */
92 uint8_t SW_MAC_TOS_PRIO_12; /* Address: 0x34C-0x34C */
93 uint8_t SW_MAC_TOS_PRIO_13; /* Address: 0x34D-0x34D */
94 uint8_t SW_MAC_TOS_PRIO_14; /* Address: 0x34E-0x34E */
95 uint8_t SW_MAC_TOS_PRIO_15; /* Address: 0x34F-0x34F */
96 uint8_t SW_MAC_TOS_PRIO_16; /* Address: 0x350-0x350 */
97 uint8_t SW_MAC_TOS_PRIO_17; /* Address: 0x351-0x351 */
98 uint8_t SW_MAC_TOS_PRIO_18; /* Address: 0x352-0x352 */
99 uint8_t SW_MAC_TOS_PRIO_19; /* Address: 0x353-0x353 */
100 uint8_t SW_MAC_TOS_PRIO_20; /* Address: 0x354-0x354 */
101 uint8_t SW_MAC_TOS_PRIO_21; /* Address: 0x355-0x355 */
102 uint8_t SW_MAC_TOS_PRIO_22; /* Address: 0x356-0x356 */
103 uint8_t SW_MAC_TOS_PRIO_23; /* Address: 0x357-0x357 */
104 uint8_t SW_MAC_TOS_PRIO_24; /* Address: 0x358-0x358 */
105 uint8_t SW_MAC_TOS_PRIO_25; /* Address: 0x359-0x359 */
106 uint8_t SW_MAC_TOS_PRIO_26; /* Address: 0x35A-0x35A */
107 uint8_t SW_MAC_TOS_PRIO_27; /* Address: 0x35B-0x35B */
108 uint8_t SW_MAC_TOS_PRIO_28; /* Address: 0x35C-0x35C */
109 uint8_t SW_MAC_TOS_PRIO_29; /* Address: 0x35D-0x35D */
110 uint8_t SW_MAC_TOS_PRIO_30; /* Address: 0x35E-0x35E */
111 uint8_t SW_MAC_TOS_PRIO_31; /* Address: 0x35F-0x35F */
112 uint8_t RESERVED5[0x10]; /* Address: 0x360-0x36F */
113 uint8_t SW_MRI_CTRL; /* Address: 0x370-0x370 */
114 uint8_t RESERVED6[0x07]; /* Address: 0x371-0x377 */
115 uint8_t SW_WRED_DSCP_COLOR; /* Address: 0x378-0x378 */
116 uint8_t RESERVED7[0x17]; /* Address: 0x379-0x38F */
117 beuint32_t SW_QM_CTRL; /* Address: 0x390-0x393 */
118 uint8_t RESERVED8[0x2E]; /* Address: 0x394-0x3C1 */
119 beuint16_t SW_EEE_TXQ_WAIT_TIME; /* Address: 0x3C2-0x3C3 */
120 uint8_t RESERVED9[0x3C]; /* Address: 0x3C4-0x3FF */
121
122} __attribute__((packed));
123
124struct global_lue_control_t {
125 beuint32_t VLAN_ENTRY; /* Address: 0x400-0x403 */
126 beuint32_t VLAN_UNTAG; /* Address: 0x404-0x407 */
127 beuint32_t VLAN_FORWARD; /* Address: 0x408-0x40B */
128 beuint16_t VLAN_INDEX; /* Address: 0x40C-0x40D */
129 uint8_t VLAN_CTRL; /* Address: 0x40E-0x40E */
130 uint8_t RESERVED0[0x1]; /* Address: 0x40F-0x40F */
131 beuint32_t ALU_INDEX; /* Address: 0x410-0x413 */
132 beuint32_t ALU_INDEX2; /* Address: 0x414-0x417 */
133 beuint32_t ALU_CTRL; /* Address: 0x418-0x41B */
134 beuint32_t ALU_STAT_CTRL; /* Address: 0x41C-0x41F */
135 beuint32_t ALU_VAL_A; /* Address: 0x420-0x423 */
136 beuint32_t ALU_VAL_B; /* Address: 0x424-0x427 */
137 beuint32_t ALU_VAL_C; /* Address: 0x428-0x42B */
138 beuint32_t ALU_VAL_D; /* Address: 0x42C-0x42F */
139 uint8_t RESERVED1[0xD0]; /* Address: 0x430-0x4FF */
140
141} __attribute__((packed));
142
143struct global_ptp_control_t {
144 beuint16_t PTP_CLK_CTRL; /* Address: 0x500-0x501 */
145 beuint16_t PTP_RTC_PHASE; /* Address: 0x502-0x503 */
146 beuint32_t PTP_RTC_NANO; /* Address: 0x504-0x507 */
147 beuint32_t PTP_RTC_SEC; /* Address: 0x508-0x50B */
148 beuint32_t PTP_RTC_SUBNANO; /* Address: 0x50C-0x50F */
149 beuint32_t PTP_RTC_TMP_ADJ; /* Address: 0x510-0x513 */
150 beuint32_t PTP_MSG_CONFIG; /* Address: 0x514-0x517 */
151 beuint16_t PTP_DOMAIN_VERSION; /* Address: 0x518-0x519 */
152 uint8_t RESERVED0[0x06]; /* Address: 0x51A-0x51F */
153 beuint32_t PTP_UNIT_INDEX; /* Address: 0x520-0x523 */
154 beuint32_t PTP_TRIG_STATUS; /* Address: 0x524-0x527 */
155 beuint32_t PTP_INT_STATUS; /* Address: 0x528-0x52B */
156 beuint32_t PTP_TS_CTRL; /* Address: 0x52C-0x52F */
157 beuint32_t PTP_TRIG_TARGET_NANO; /* Address: 0x530-0x533 */
158 beuint32_t PTP_TRIG_TARGET_SEC; /* Address: 0x534-0x537 */
159 beuint32_t PTP_TRIG_CTRL; /* Address: 0x538-0x53B */
160 beuint32_t PTP_TRIG_CYC_WIDTH; /* Address: 0x53C-0x53F */
161 beuint32_t PTP_TRIG_CYC_CNT; /* Address: 0x540-0x543 */
162 beuint32_t PTP_TRIG_ITER_TIME; /* Address: 0x544-0x547 */
163 beuint32_t PTP_TRIG_PULSE; /* Address: 0x548-0x54B */
164 uint8_t RESERVED1[0x04]; /* Address: 0x54C-0x54F */
165 beuint32_t PTP_TS_STAT_CTRL; /* Address: 0x550-0x553 */
166 beuint32_t PTP_TS_EVT_0_NANO; /* Address: 0x554-0x557 */
167 beuint32_t PTP_TS_EVT_0_SEC; /* Address: 0x558-0x55B */
168 beuint32_t PTP_TS_EVT_0_PHASE; /* Address: 0x55C-0x55F */
169 beuint32_t PTP_TS_EVT_1_NANO; /* Address: 0x560-0x563 */
170 beuint32_t PTP_TS_EVT_1_SEC; /* Address: 0x564-0x567 */
171 beuint32_t PTP_TS_EVT_1_PHASE; /* Address: 0x568-0x56B */
172 beuint32_t PTP_TS_EVT_2_NANO; /* Address: 0x56C-0x56F */
173 beuint32_t PTP_TS_EVT_2_SEC; /* Address: 0x570-0x573 */
174 beuint32_t PTP_TS_EVT_2_PHASE; /* Address: 0x574-0x577 */
175 beuint32_t PTP_TS_EVT_3_NANO; /* Address: 0x578-0x57B */
176 beuint32_t PTP_TS_EVT_3_SEC; /* Address: 0x57C-0x57F */
177 beuint32_t PTP_TS_EVT_3_PHASE; /* Address: 0x580-0x583 */
178 beuint32_t PTP_TS_EVT_4_NANO; /* Address: 0x584-0x587 */
179 beuint32_t PTP_TS_EVT_4_SEC; /* Address: 0x588-0x58B */
180 beuint32_t PTP_TS_EVT_4_PHASE; /* Address: 0x58C-0x58F */
181 beuint32_t PTP_TS_EVT_5_NANO; /* Address: 0x590-0x593 */
182 beuint32_t PTP_TS_EVT_5_SEC; /* Address: 0x594-0x597 */
183 beuint32_t PTP_TS_EVT_5_PHASE; /* Address: 0x598-0x59B */
184 beuint32_t PTP_TS_EVT_6_NANO; /* Address: 0x59C-0x59F */
185 beuint32_t PTP_TS_EVT_6_SEC; /* Address: 0x5A0-0x5A3 */
186 beuint32_t PTP_TS_EVT_6_PHASE; /* Address: 0x5A4-0x5A7 */
187 beuint32_t PTP_TS_EVT_7_NANO; /* Address: 0x5A8-0x5AB */
188 beuint32_t PTP_TS_EVT_7_SEC; /* Address: 0x5AC-0x5AF */
189 beuint32_t PTP_TS_EVT_7_PHASE; /* Address: 0x5B0-0x5B3 */
190 uint8_t RESERVED2[0x4C]; /* Address: 0x5B4-0x5FF */
191
192} __attribute__((packed));
193
194struct port_control_t {
195 beuint16_t PORT_DEFAULT_VID; /* Address: 0x00-0x01 */
196 beuint16_t PORT_CUSTOM_VID; /* Address: 0x02-0x03 */
197 beuint16_t PORT_AVB_SR_1_VID; /* Address: 0x04-0x05 */
198 beuint16_t PORT_AVB_SR_2_VID; /* Address: 0x06-0x07 */
199 beuint16_t PORT_AVB_SR_1_TYPE; /* Address: 0x08-0x09 */
200 beuint16_t PORT_AVB_SR_2_TYPE; /* Address: 0x0A-0x0B */
201 uint8_t RESERVED0[0x07]; /* Address: 0x0C-0x12 */
202 uint8_t PORT_WOL_STATUS; /* Address: 0x13-0x13 */
203 uint8_t RESERVED1[0x03]; /* Address: 0x14-0x16 */
204 uint8_t PORT_WOL_MASK; /* Address: 0x17-0x17 */
205 uint8_t RESERVED2[0x03]; /* Address: 0x18-0x1A */
206 uint8_t PORT_INT_STATUS; /* Address: 0x1B-0x1B */
207 uint8_t RESERVED3[0x03]; /* Address: 0x1C-0x1E */
208 uint8_t PORT_INT_MASK; /* Address: 0x1F-0x1F */
209 beuint32_t PORT_CTRL; /* Address: 0x20-0x23 */
210 uint8_t RESERVED4[0x0C]; /* Address: 0x24-0x2F */
211 beuint32_t PORT_STATUS; /* Address: 0x30-0x33 */
212 uint8_t RESERVED5[0xCC]; /* Address: 0x34-0xFF */
213
214} __attribute__((packed));
215
216struct port_phy_control_t {
217 beuint16_t PHY_BASIC_CTL; /* Address: 0x100-0x101 */
218 beuint16_t PHY_BASIC_ST; /* Address: 0x102-0x103 */
219 beuint16_t PHY_ID_1; /* Address: 0x104-0x105 */
220 beuint16_t PHY_ID_2; /* Address: 0x106-0x107 */
221 beuint16_t PHY_A_NEG_ADVERT; /* Address: 0x108-0x109 */
222 beuint16_t PHY_A_NEG_LPA; /* Address: 0x10A-0x10B */
223 beuint16_t PHY_A_NEG_EXP; /* Address: 0x10C-0x10D */
224 beuint16_t PHY_A_NEG_NEXT_PG; /* Address: 0x10E-0x10F */
225 beuint16_t PHY_LP_NEXT_PG_ABIL; /* Address: 0x110-0x111 */
226 beuint16_t PHY_GBCR; /* Address: 0x112-0x113 */
227 beuint16_t PHY_GBSR; /* Address: 0x114-0x115 */
228 uint8_t RESERVED0[0x04]; /* Address: 0x116-0x119 */
229 beuint16_t PHY_MMD_SETUP; /* Address: 0x11A-0x11B */
230 beuint16_t PHY_MMD_DATA; /* Address: 0x11C-0x11D */
231 beuint16_t PHY_EXT_STATUS; /* Address: 0x11E-0x11F */
232 uint8_t RESERVED1[0x02]; /* Address: 0x120-0x121 */
233 beuint16_t PHY_REMOTE_LOOPBACK; /* Address: 0x122-0x123 */
234 beuint16_t PHY_LINK_MD; /* Address: 0x124-0x125 */
235 beuint16_t PHY_PMA_STATUS; /* Address: 0x126-0x127 */
236 uint8_t RESERVED2[0x02]; /* Address: 0x128-0x129 */
237 beuint16_t PHY_RXER_CNT; /* Address: 0x12A-0x12B */
238 uint8_t RESERVED3[0x0a]; /* Address: 0x12C-0x133 */
239 beuint16_t PHY_INT; /* Address: 0x136-0x137 */
240 beuint16_t PHY_AUTO_MDIX; /* Address: 0x138-0x139 */
241 uint8_t RESERVED4[0x04]; /* Address: 0x13A-0x13D */
242 beuint16_t PHY_CTL_2; /* Address: 0x13E-0x13F */
243 uint8_t RESERVED5[0xC0]; /* Address: 0x140-0x1FF */
244
245} __attribute__((packed));
246
247struct port_mii_control_t {
248 beuint32_t PORT_XMII_CTRL; /* Address: 0x300-0x303 */
249 uint8_t RESERVED0[0xFC]; /* Address: 0x304-0x3FF */
250
251} __attribute__((packed));
252
253struct port_mac_control_t {
254 beuint32_t PORT_MAC_CTRL; /* Address: 0x400-0x403 */
255 uint8_t RESERVED0[0x0C]; /* Address: 0x404-0x40F */
256 uint8_t PORT_IN_RATE_0; /* Address: 0x410-0x410 */
257 uint8_t PORT_IN_RATE_1; /* Address: 0x411-0x411 */
258 uint8_t PORT_IN_RATE_2; /* Address: 0x412-0x412 */
259 uint8_t PORT_IN_RATE_3; /* Address: 0x413-0x413 */
260 uint8_t PORT_IN_RATE_4; /* Address: 0x414-0x414 */
261 uint8_t PORT_IN_RATE_5; /* Address: 0x415-0x415 */
262 uint8_t PORT_IN_RATE_6; /* Address: 0x416-0x416 */
263 uint8_t PORT_IN_RATE_7; /* Address: 0x417-0x417 */
264 uint8_t RESERVED1[0x08]; /* Address: 0x418-0x41F */
265 uint8_t PORT_OUT_RATE_0; /* Address: 0x420-0x420 */
266 uint8_t PORT_OUT_RATE_1; /* Address: 0x421-0x421 */
267 uint8_t PORT_OUT_RATE_2; /* Address: 0x422-0x422 */
268 uint8_t PORT_OUT_RATE_3; /* Address: 0x423-0x423 */
269 uint8_t RESERVED2[0xDC]; /* Address: 0x424-0x4FF */
270
271} __attribute__((packed));
272
273struct port_mib_control_t {
274 beuint32_t PORT_MIB_CTRL_STAT; /* Address: 0x500-0x503 */
275 beuint32_t PORT_MIB_DATA; /* Address: 0x504-0x507 */
276 uint8_t RESERVED0[0xF8]; /* Address: 0x508-0x5FF */
277
278} __attribute__((packed));
279
280struct port_acl_control_t {
281 beuint32_t PORT_ACL_ACCESS; /* Address: 0x600-0x603 */
282 beuint32_t PORT_ACL_ACCESS2; /* Address: 0x604-0x607 */
283 beuint32_t PORT_ACL_ACCESS3; /* Address: 0x608-0x60B */
284 beuint32_t PORT_ACL_ACCESS4; /* Address: 0x60C-0x60F */
285 beuint32_t PORT_ACL_EN_CTRL; /* Address: 0x610-0x613 */
286 uint8_t RESERVED0[0xEC]; /* Address: 0x614-0x6FF */
287
288} __attribute__((packed));
289
290struct port_sw_ingress_control_t {
291 uint8_t PORT_MIRROR_CTRL; /* Address: 0x800-0x800 */
292 uint8_t PORT_PRIO_CTRL; /* Address: 0x801-0x801 */
293 uint8_t PORT_IN_MAC_CTRL; /* Address: 0x802-0x802 */
294 uint8_t PORT_AUTH_CTRL; /* Address: 0x803-0x803 */
295 beuint32_t PORT_POINTER; /* Address: 0x804-0x807 */
296 beuint32_t PORT_PRIO_QUEUE_MAP; /* Address: 0x808-0x80B */
297 beuint32_t PORT_POLICE_CTRL; /* Address: 0x80C-0x80F */
298 uint8_t RESERVED0[0xF0]; /* Address: 0x810-0x8FF */
299
300} __attribute__((packed));
301
302struct port_sw_egress_control_t {
303 beuint32_t PORT_TX_QUEUE_IDX; /* Address: 0x900-0x903 */
304 beuint32_t PORT_TX_QUEUE_PVID; /* Address: 0x904-0x907 */
305 uint8_t RESERVED0[0x0C]; /* Address: 0x908-0x913 */
306 beuint16_t PORT_TX_QUEUE_CTRL; /* Address: 0x914-0x915 */
307 uint8_t RESERVED1[0xEA]; /* Address: 0x916-0x9FF */
308
309} __attribute__((packed));
310
311struct port_sw_queue_management_control_t {
312 uint8_t RESERVED0[0x04]; /* Address: 0xA00-0xA03 */
313 beuint32_t PORT_VLAN_MEMBERS; /* Address: 0xA04-0xA07 */
314 uint8_t RESERVED1[0xF8]; /* Address: 0xA08-0xAFF */
315
316} __attribute__((packed));
317
318struct port_sw_addr_lue_control_t {
319 uint8_t PORT_LUE_CTRL; /* Address: 0xB00-0xB00 */
320 uint8_t PORT_MSTP_POINTER; /* Address: 0xB01-0xB01 */
321 uint8_t RESERVED0[0x02]; /* Address: 0xB02-0xB03 */
322 uint8_t PORT_MSTP_STATE; /* Address: 0xB04-0xB04 */
323 uint8_t RESERVED1[0xFB]; /* Address: 0xB05-0xBFF */
324
325} __attribute__((packed));
326
327struct global_regs_t {
328 global_control_t ctl; /* Address: 0x0000-0x00FF */
329 global_io_control_t io; /* Address: 0x0100-0x01FF */
330 global_phy_control_t phy; /* Address: 0x0200-0x02FF */
331 global_switch_control_t sw; /* Address: 0x0300-0x03FF */
332 global_lue_control_t lue; /* Address: 0x0400-0x04FF */
333 global_ptp_control_t ptp; /* Address: 0x0500-0x05FF */
334} __attribute__((packed));
335
336struct port_regs_t {
337 port_control_t ctl; /* Address: 0xN000-0xN0FF */
338 port_phy_control_t phy; /* Address: 0xN100-0xN1FF */
339 uint8_t RESERVED0[0x100]; /* Address: 0x200-0x2FF */
340 port_mii_control_t mii; /* Address: 0xN300-0xN3FF */
341 port_mac_control_t mac; /* Address: 0xN400-0xN4FF */
342 port_mib_control_t mib; /* Address: 0xN500-0xN5FF */
343 port_acl_control_t acl; /* Address: 0xN600-0xN6FF */
344 uint8_t RESERVED1[0x100]; /* Address: 0x700-0x7FF */
345 port_sw_ingress_control_t in; /* Address: 0xN800-0xN8FF */
346 port_sw_egress_control_t out; /* Address: 0xN900-0xN9FF */
347 port_sw_queue_management_control_t qmanage; /* Address: 0xNA00-0xNAFF */
348 port_sw_addr_lue_control_t lue; /* Address: 0xNB00-0xNBFF */
349 uint8_t RESERVED2[0x400]; /* Address: 0xC00-0xFFF */
350} __attribute__((packed));
351
352struct ksz_98xx_regs_t {
353 global_regs_t g; /* Address: 0x0000-0x05FF */
354 uint8_t RESERVED0[0xA00]; /* Address: 0x600-0xFFF */
355 port_regs_t p[KSZ98XX_MAX_PORTS]; /* Address: 0xN000-0xNBFF */
356} __attribute__((packed));
357
358#ifdef __cplusplus
359namespace CHIP_ID1 {
360 enum {
361 FAMILY_ID = 0x95,
362 FAMILY_ID_94 = 0x94,
363 FAMILY_ID_95 = 0x95,
364 FAMILY_ID_85 = 0x85,
365 FAMILY_ID_98 = 0x98,
366 FAMILY_ID_88 = 0x88,
367 };
368
369}
370namespace CHIP_ID2 {
371 enum {
372 CHIP_ID_63 = 0x63,
373 CHIP_ID_66 = 0x66,
374 CHIP_ID_67 = 0x67,
375 CHIP_ID_77 = 0x77,
376 CHIP_ID_93 = 0x93,
377 CHIP_ID_96 = 0x96,
378 CHIP_ID_97 = 0x97,
379 };
380
381}
382namespace CHIP_ID3 {
383 enum {
384 SW_REV_Pos = 4,
385 SW_REV_Msk = ( 0xF << SW_REV_Pos),
386 };
387
388}
389namespace PME_CTRL {
390 enum {
391 PME_ENABLE_Pos = 0,
392 PME_ENABLE_Msk = (0x1 << PME_ENABLE_Pos),
393 PME_ENABLE_ENABLED = (1 << PME_ENABLE_Pos),
394 PME_ENABLE_DISABLED = (0 << PME_ENABLE_Pos),
395 PME_POLARITY_Pos = 1,
396 PME_POLARITY_Msk = (0x1 << PME_POLARITY_Pos),
397 PME_POLARITY_HIGH = (1 << PME_POLARITY_Pos),
398 PME_POLARITY_LOW = (0 << PME_POLARITY_Pos),
399 };
400
401 inline uint32_t PME_ENABLE(uint32_t _x)
402 { return ((_x) << PME_ENABLE_Pos); }
403 inline uint32_t PME_POLARITY(uint32_t _x)
404 { return ((_x) << PME_POLARITY_Pos); }
405
406}
407namespace GLOBAL_INT_STATUS {
408 enum {
409 LUE_INT_Pos = 31,
410 LUE_INT_Msk = (0x1 << LUE_INT_Pos),
411 TRIG_TS_INT_Pos = 30,
412 TRIG_TS_INT_Msk = (0x1 << TRIG_TS_INT_Pos),
413 ABP_TIMEOUT_INT_Pos = 29,
414 ABP_TIMEOUT_INT_Msk = (0x1 << ABP_TIMEOUT_INT_Pos),
415 };
416
417}
418namespace GLOBAL_INT_MASK {
419 enum {
420 LUE_INT_Pos = 31,
421 LUE_INT_Msk = (0x1 << LUE_INT_Pos),
422 TRIG_TS_INT_Pos = 30,
423 TRIG_TS_INT_Msk = (0x1 << TRIG_TS_INT_Pos),
424 ABP_TIMEOUT_INT_Pos = 29,
425 ABP_TIMEOUT_INT_Msk = (0x1 << ABP_TIMEOUT_INT_Pos),
426 };
427
428}
429namespace PORT_INT_STATUS {
430 enum {
431 };
432
433 inline uint32_t PORT(uint32_t _x)
434 { return (0x1 << (_x)); }
435
436}
437namespace PORT_INT_MASK {
438 enum {
439 };
440
441 inline uint32_t PORT(uint32_t _x)
442 { return (0x1 << (_x)); }
443
444}
445namespace PHY_INT_STATUS {
446 enum {
447 };
448
449 inline uint32_t PHY(uint32_t _x)
450 { return (0x1 << (_x)); }
451
452}
453namespace PHY_INT_MASK {
454 enum {
455 };
456
457 inline uint32_t PHY(uint32_t _x)
458 { return (0x1 << (_x)); }
459
460}
461
462namespace SERIAL_IO_CTRL {
463 enum {
464 SPI_CLOCK_OUT_RISING_EDGE_Pos = 0,
465 SPI_CLOCK_OUT_RISING_EDGE_Msk = (0x1 << SPI_CLOCK_OUT_RISING_EDGE_Pos),
466 SPI_CLOCK_OUT_RISING_EDGE_TRUE = (0x1 << SPI_CLOCK_OUT_RISING_EDGE_Pos),
467 SPI_CLOCK_OUT_RISING_EDGE_FALSE = (0x1 << SPI_CLOCK_OUT_RISING_EDGE_Pos),
468 SPI_AUTO_EDGE_DETECTION_Pos = 1,
469 SPI_AUTO_EDGE_DETECTION_Msk = (0x1 << SPI_AUTO_EDGE_DETECTION_Pos),
470 SPI_AUTO_EDGE_DETECTION_ENABLED = (0x1 << SPI_AUTO_EDGE_DETECTION_Pos),
471 SPI_AUTO_EDGE_DETECTION_DISABLED = (0x0 << SPI_AUTO_EDGE_DETECTION_Pos),
472 MIIM_PREAMBLE_SUPPRESSION_Pos = 2,
473 MIIM_PREAMBLE_SUPPRESSION_Msk = (0x1 << MIIM_PREAMBLE_SUPPRESSION_Pos),
474 MIIM_PREAMBLE_SUPPRESSION_ENABLED = (0x1 << MIIM_PREAMBLE_SUPPRESSION_Pos),
475 MIIM_PREAMBLE_SUPPRESSION_DISABLED = (0x0 << MIIM_PREAMBLE_SUPPRESSION_Pos),
476 };
477
478 inline uint32_t SPI_CLOCK_OUT_RISING_EDGE(uint32_t _x)
479 { return (((_x) << SPI_CLOCK_OUT_RISING_EDGE_Pos) & SPI_CLOCK_OUT_RISING_EDGE_Msk); }
480 inline uint32_t SPI_AUTO_EDGE_DETECTION(uint32_t _x)
481 { return ((_x) << SPI_AUTO_EDGE_DETECTION_Pos); }
482 inline uint32_t MIIM_PREAMBLE_SUPPRESSION(uint32_t _x)
483 { return ((_x) << MIIM_PREAMBLE_SUPPRESSION_Pos); }
484
485}
486namespace OUTPUT_CLOCK_CTRL {
487 enum {
488 REFCLKO_IS_125MHZ_Pos = 0,
489 REFCLKO_IS_125MHZ_Msk = (0x1 << REFCLKO_IS_125MHZ_Pos),
490 REFCLKO_IS_125MHZ_TRUE = (0x1 << REFCLKO_IS_125MHZ_Pos),
491 REFCLKO_IS_125MHZ_FALSE = (0x0 << REFCLKO_IS_125MHZ_Pos),
492 REFCLKO_Pos = 1,
493 REFCLKO_Msk = (0x1 << REFCLKO_Pos),
494 REFCLKO_ENABLED = (0x1 << REFCLKO_Pos),
495 REFCLKO_DISABLED = (0x0 << REFCLKO_Pos),
496 };
497
498 inline uint32_t REFCLKO_IS_125MHZ(uint32_t _x)
499 { return ((_x) << REFCLKO_IS_125MHZ_Pos); }
500 inline uint32_t REFCLKO(uint32_t _x)
501 { return ((_x) << REFCLKO_Pos); }
502
503}
504namespace IBA_CTRL {
505 enum {
506 IBA_FRAME_TPID_Pos = 0,
507 IBA_FRAME_TPID_Msk = (0xFFFF << IBA_FRAME_TPID_Pos),
508 IBA_PORT_Pos = 16,
509 IBA_PORT_Msk = (0x7 << IBA_PORT_Pos),
510 IBA_RESP_PRIO_Pos = 22,
511 IBA_RESP_PRIO_Msk = (0x3 << IBA_RESP_PRIO_Pos),
512 IBA_RESET_Pos = 29,
513 IBA_RESET_Msk = (0x1 << IBA_RESET_Pos),
514 IBA_DA_MATCH_Pos = 30,
515 IBA_DA_MATCH_Msk = (0x1 << IBA_DA_MATCH_Pos),
516 IBA_DA_MATCH_ENABLED = (0x1 << IBA_DA_MATCH_Pos),
517 IBA_DA_MATCH_DISABLED = (0x0 << IBA_DA_MATCH_Pos),
518 IBA_ENABLE_Pos = 31,
519 IBA_ENABLE_Msk = (0x1 << IBA_ENABLE_Pos),
520 IBA_ENABLE_ENABLED = (0x1 << IBA_ENABLE_Pos),
521 IBA_ENABLE_DISABLED = (0x0 << IBA_ENABLE_Pos),
522 };
523
524 inline uint32_t IBA_FRAME_TPID(uint32_t _x)
525 { return ((_x) << IBA_FRAME_TPID_Pos); }
526 inline uint32_t IBA_PORT(uint32_t _x)
527 { return ((_x) << IBA_PORT_Pos); }
528 inline uint32_t IBA_RESP_PRIO(uint32_t _x)
529 { return ((_x) << IBA_RESP_PRIO_Pos); }
530 inline uint32_t IBA_RESET(uint32_t _x)
531 { return ((_x) << IBA_RESET_Pos); }
532 inline uint32_t IBA_DA_MATCH(uint32_t _x)
533 { return (((_x) << IBA_DA_MATCH_Pos) & IBA_DA_MATCH_Msk); }
534 inline uint32_t IBA_ENABLE(uint32_t _x)
535 { return (((_x) << IBA_ENABLE_Pos) & IBA_ENABLE_Msk); }
536
537}
538namespace APB_TIMEOUT {
539 enum {
540 APB_TIMEOUT_ACK_Pos = 31,
541 APB_TIMEOUT_ACK_Msk = (0x1 << APB_TIMEOUT_ACK_Pos),
542 };
543
544}
545namespace IO_DRIVE_STRENGTH {
546 enum {
547 LO_SPEED_DRIVE_STRENGTH_Pos = 0,
548 LO_SPEED_DRIVE_STRENGTH_Msk = (0x7 << LO_SPEED_DRIVE_STRENGTH_Pos),
549 HI_SPEED_DRIVE_STRENGTH_Pos = 4,
550 HI_SPEED_DRIVE_STRENGTH_Msk = (0x7 << HI_SPEED_DRIVE_STRENGTH_Pos),
551 };
552
553 inline uint32_t LO_SPEED_DRIVE_STRENGTH(uint32_t _x)
554 { return (((_x) << LO_SPEED_DRIVE_STRENGTH_Pos) & LO_SPEED_DRIVE_STRENGTH_Msk); }
555 inline uint32_t HI_SPEED_DRIVE_STRENGTH(uint32_t _x)
556 { return (((_x) << HI_SPEED_DRIVE_STRENGTH_Pos) & HI_SPEED_DRIVE_STRENGTH_Msk); }
557
558}
559namespace IBA_STATUS {
560 enum {
561 IBA_CMD_LOC_Pos = 0,
562 IBA_CMD_LOC_Msk = (0x7F << IBA_CMD_LOC_Pos),
563 IBA_OVERSIZE_ERROR_Pos = 10,
564 IBA_OVERSIZE_ERROR_Msk = (0x1 << IBA_OVERSIZE_ERROR_Pos),
565 IBA_CMD_ERROR_Pos = 11,
566 IBA_CMD_ERROR_Msk = (0x1 << IBA_CMD_ERROR_Pos),
567 IBA_CODE_ERROR_Pos = 12,
568 IBA_CODE_ERROR_Msk = (0x1 << IBA_CMD_ERROR_Pos),
569 IBA_FMT_MISMATCH_Pos = 13,
570 IBA_FMT_MISMATCH_Msk = (0x1 << IBA_FMT_MISMATCH_Pos),
571 IBA_DA_MISMATCH_Pos = 14,
572 IBA_DA_MISMATCH_Msk = (0x1 << IBA_DA_MISMATCH_Pos),
573 IBA_EXEC_DONE_Pos = 29,
574 IBA_EXEC_DONE_Msk = (0x1 << IBA_EXEC_DONE_Pos),
575 IBA_RESP_Pos = 30,
576 IBA_RESP_Msk = (0x1 << IBA_RESP_Pos),
577 IBA_REQ_Pos = 31,
578 IBA_REQ_Msk = (0x1 << IBA_REQ_Pos),
579 };
580
581 inline uint32_t IBA_CMD_LOC(uint32_t _x)
582 { return (((_x) << IBA_CMD_LOC_Pos) & IBA_CMD_LOC_Msk); }
583
584}
585namespace IBA_STATES {
586 enum {
587 IBA_FMT_ID_Pos = 0,
588 IBA_FMT_ID_Msk = (0xFFFF << IBA_FMT_ID_Pos),
589 IBA_PACKET_SIZE_Pos = 16,
590 IBA_PACKET_SIZE_Msk = (0x7F << IBA_PACKET_SIZE_Pos),
591 IBA_RESP_STATE_Pos = 26,
592 IBA_RESP_STATE_Msk = (0x3 << IBA_RESP_STATE_Pos),
593 IBA_CMD_STATE_Pos = 28,
594 IBA_CMD_STATE_Msk = (0x3 << IBA_CMD_STATE_Pos),
595 IBA_BUF_STATE_Pos = 30,
596 IBA_BUF_STATE_Msk = (0x3 << IBA_BUF_STATE_Pos),
597 };
598
599}
600namespace IBA_RESULT {
601 enum {
602 IBA_RETRY_CNT_Pos = 0,
603 IBA_RETRY_CNT_Msk = (0x3F << IBA_RETRY_CNT_Pos),
604 IBA_SIZE_Pos = 24,
605 IBA_SIZE_Msk = (0xFF << IBA_SIZE_Pos),
606 };
607
608}
609namespace LED_OVERRIDE {
610 enum {
611 };
612
613 inline uint32_t LED_GPO(uint32_t _x)
614 { return (1 << (_x)); }
615
616}
617namespace LED_OUTPUT {
618 enum {
619 };
620
621 inline uint32_t HIGH(uint32_t _x)
622 { return (1 << (_x)); }
623
624}
625
626namespace POWER_MANAGEMENT_CTRL {
627 enum {
628 MODE_Pos = 3,
629 MODE_Msk = (0x3 << MODE_Pos),
630 MODE_NORMAL = (0x0 << MODE_Pos),
631 MODE_ENERGY_DETECT_POWER_DOWN = (0x1 << MODE_Pos),
632 MODE_SOFT_POWER_DOWN = (0x2 << MODE_Pos),
633 PLL_POWER_DOWN_Pos = 5,
634 PLL_POWER_DOWN_Msk = (0x1 << MODE_Pos),
635 PLL_POWER_DOWN_NORMAL = (0x0 << MODE_Pos),
636 PLL_POWER_DOWN_PLL_DISABLED = (0x1 << MODE_Pos),
637 };
638
639}
640
641namespace SW_OPERATION {
642 enum {
643 SW_START_Pos = 0,
644 SW_START_Msk = (0x1 << SW_START_Pos),
645 SW_START_ENABLED = (0x1 << SW_START_Pos),
646 SW_START_DISABLED = (0x1 << SW_START_Pos),
647 SW_RESET_Pos = 1,
648 SW_RESET_Msk = (0x1 << SW_RESET_Pos),
649 SW_RESET_RESET = (0x1 << SW_RESET_Pos),
650 SW_DOUBLE_TAG_Pos = 2,
651 SW_DOUBLE_TAG_Msk = (0x1 << SW_DOUBLE_TAG_Pos),
652 SW_DOUBLE_TAG_ENABLED = (0x1 << SW_DOUBLE_TAG_Pos),
653 SW_DOUBLE_TAG_DISABLED = (0x0 << SW_DOUBLE_TAG_Pos),
654 };
655
656}
657namespace SW_MTU {
658 enum {
659 MTU_Pos = 0,
660 MTU_Msk = (0x3FFF << MTU_Pos),
661 };
662
663 inline uint32_t MTU(uint32_t _x)
664 { return (((_x) << MTU_Pos) & MTU_Msk); }
665
666}
667namespace SW_ISP_TPID {
668 enum {
669 ISP_TPID_Pos = 0,
670 ISP_TPID_Msk = (0xFFFF << ISP_TPID_Pos),
671 };
672
673 inline uint32_t ISP_TPID(uint32_t _x)
674 { return (((_x) << ISP_TPID_Pos) & ISP_TPID_Msk); }
675
676}
677namespace SW_HSR_TPID {
678 enum {
679 HSR_TPID_Pos = 0,
680 HSR_TPID_Msk = (0xFFFF << HSR_TPID_Pos),
681 };
682
683 inline uint32_t ISP_TPID(uint32_t _x)
684 { return (((_x) << HSR_TPID_Pos) & HSR_TPID_Msk); }
685
686}
687namespace SW_AVB_STRATEGY {
688 enum {
689 POLICING_CREDIT_ACCT_Pos = 0,
690 POLICING_CREDIT_ACCT_Msk = (0x1 << POLICING_CREDIT_ACCT_Pos),
691 SHAPING_CREDIT_ACCT_Pos = 1,
692 SHAPING_CREDIT_ACCT_Msk = (0x1 << SHAPING_CREDIT_ACCT_Pos),
693 };
694
695}
696namespace SW_LUE_CTRL {
697 enum {
698 AGE_PERIOD_Pos = 0,
699 AGE_PERIOD_Msk = (0xFF << AGE_PERIOD_Pos),
700 PRIO_Pos = 8,
701 PRIO_Msk = (0x3 << PRIO_Pos),
702 PRIO_DST_ADDR = (0x0 << PRIO_Pos),
703 PRIO_SRC_ADDR = (0x1 << PRIO_Pos),
704 PRIO_HIGHEST_DA_SA = (0x2 << PRIO_Pos),
705 PRIO_LOWEST_DA_SA = (0x3 << PRIO_Pos),
706 FLUSH_OPTION_Pos = 10,
707 FLUSH_OPTION_Msk = (0x3 << FLUSH_OPTION_Pos),
708 FLUSH_OPTION_NONE = (0x0 << FLUSH_OPTION_Pos),
709 FLUSH_OPTION_DYN_MAC = (0x1 << FLUSH_OPTION_Pos),
710 FLUSH_OPTION_STA_MAC = (0x2 << FLUSH_OPTION_Pos),
711 FLUSH_OPTION_BOTH = (0x3 << FLUSH_OPTION_Pos),
712 EGRESS_VLAN_FILTER_STA_Pos = 12,
713 EGRESS_VLAN_FILTER_STA_Msk = (0x3 << EGRESS_VLAN_FILTER_STA_Pos),
714 EGRESS_VLAN_FILTER_STA_ENABLED = (0x1 << EGRESS_VLAN_FILTER_STA_Pos),
715 EGRESS_VLAN_FILTER_STA_DISABLED = (0x0 << EGRESS_VLAN_FILTER_STA_Pos),
716 EGRESS_VLAN_FILTER_DYN_Pos = 13,
717 EGRESS_VLAN_FILTER_DYN_Msk = (0x1 << EGRESS_VLAN_FILTER_DYN_Pos),
718 EGRESS_VLAN_FILTER_DYN_ENABLED = (0x1 << EGRESS_VLAN_FILTER_DYN_Pos),
719 EGRESS_VLAN_FILTER_DYN_DISABLED = (0x0 << EGRESS_VLAN_FILTER_DYN_Pos),
720 TRAP_DOUBLE_TAG_Pos = 14,
721 TRAP_DOUBLE_TAG_Msk = (0x1 << TRAP_DOUBLE_TAG_Pos),
722 TRAP_DOUBLE_TAG_ENABLED = (0x1 << TRAP_DOUBLE_TAG_Pos),
723 TRAP_DOUBLE_TAG_DISABLED = (0x0 << TRAP_DOUBLE_TAG_Pos),
724 LINK_DOWN_FLUSH_Pos = 16,
725 LINK_DOWN_FLUSH_Msk = (0x1 << LINK_DOWN_FLUSH_Pos),
726 LINK_DOWN_FLUSH_ENABLED = (0x1 << LINK_DOWN_FLUSH_Pos),
727 LINK_DOWN_FLUSH_DISABLED = (0x0 << LINK_DOWN_FLUSH_Pos),
728 FAST_AGING_Pos = 17,
729 FAST_AGING_Msk = (0x1 << FAST_AGING_Pos),
730 FAST_AGING_ENABLED = (0x1 << FAST_AGING_Pos),
731 FAST_AGING_DISABLED = (0x0 << FAST_AGING_Pos),
732 AGING_Pos = 18,
733 AGING_Msk = (0x1 << AGING_Pos),
734 AGING_ENABLED = (0x1 << AGING_Pos),
735 AGING_DISABLED = (0x0 << AGING_Pos),
736 FWD_MCAST_SRC_ADDR_Pos = 19,
737 FWD_MCAST_SRC_ADDR_Msk = (0x1 << FWD_MCAST_SRC_ADDR_Pos),
738 FWD_MCAST_SRC_ADDR_ENABLED = (0x1 << FWD_MCAST_SRC_ADDR_Pos),
739 FWD_MCAST_SRC_ADDR_DISABLED = (0x0 << FWD_MCAST_SRC_ADDR_Pos),
740 FLUSH_MSTP_TABLE_Pos = 20,
741 FLUSH_MSTP_TABLE_Msk = (0x1 << FLUSH_MSTP_TABLE_Pos),
742 FLUSH_MSTP_TABLE_ENABLED = (0x1 << FLUSH_MSTP_TABLE_Pos),
743 FLUSH_MSTP_TABLE_DISABLED = (0x0 << FLUSH_MSTP_TABLE_Pos),
744 FLUSH_STP_TABLE_Pos = 21,
745 FLUSH_STP_TABLE_Msk = (0x1 << FLUSH_STP_TABLE_Pos),
746 FLUSH_STP_TABLE_ENABLED = (0x1 << FLUSH_STP_TABLE_Pos),
747 FLUSH_STP_TABLE_DISABLED = (0x0 << FLUSH_STP_TABLE_Pos),
748 SRC_ADDR_FILTER_Pos = 22,
749 SRC_ADDR_FILTER_Msk = (0x1 << SRC_ADDR_FILTER_Pos),
750 SRC_ADDR_FILTER_ENABLED = (0x1 << SRC_ADDR_FILTER_Pos),
751 SRC_ADDR_FILTER_DISABLED = (0x0 << SRC_ADDR_FILTER_Pos),
752 UNICAST_LEARN_DISABLE_Pos = 23,
753 UNICAST_LEARN_DISABLE_Msk = (0x1 << UNICAST_LEARN_DISABLE_Pos),
754 UNICAST_LEARN_DISABLE_ENABLED = (0x1 << UNICAST_LEARN_DISABLE_Pos),
755 UNICAST_LEARN_DISABLE_DISABLED = (0x0 << UNICAST_LEARN_DISABLE_Pos),
756 HASH_OPTION_Pos = 24,
757 HASH_OPTION_Msk = (0x3 << HASH_OPTION_Pos),
758 HASH_OPTION_CRC = (0x1 << HASH_OPTION_Pos),
759 HASH_OPTION_XOR = (0x2 << HASH_OPTION_Pos),
760 HASH_OPTION_DIRECT = (0x3 << HASH_OPTION_Pos),
761 RESV_MCAST_Pos = 26,
762 RESV_MCAST_Msk = (0x1 << RESV_MCAST_Pos),
763 RESV_MCAST_ENABLED = (0x1 << RESV_MCAST_Pos),
764 RESV_MCAST_DISABLED = (0x0 << RESV_MCAST_Pos),
765 AGE_CNT_Pos = 27,
766 AGE_CNT_Msk = (0x7 << AGE_CNT_Pos),
767 DROP_INVALID_VID_Pos = 30,
768 DROP_INVALID_VID_Msk = (0x1 << DROP_INVALID_VID_Pos),
769 DROP_INVALID_VID_ENABLED = (0x1 << DROP_INVALID_VID_Pos),
770 DROP_INVALID_VID_DISABLED = (0x0 << DROP_INVALID_VID_Pos),
771 VLAN_ENABLE_Pos = 31,
772 VLAN_ENABLE_Msk = (0x1 << VLAN_ENABLE_Pos),
773 VLAN_ENABLE_ENABLED = (0x1 << VLAN_ENABLE_Pos),
774 VLAN_ENABLE_DISABLED = (0x0 << VLAN_ENABLE_Pos),
775 };
776
777 inline uint32_t AGE_PERIOD(uint32_t _x)
778 { return (((_x) << AGE_PERIOD_Pos) & AGE_PERIOD_Msk); }
779 inline uint32_t AGE_CNT(uint32_t _x)
780 { return (((_x) << AGE_CNT_Pos) & AGE_CNT_Msk); }
781
782}
783namespace SW_LUE_INT_STATUS {
784 enum {
785 WRITE_FAIL_Pos = 0,
786 WRITE_FAIL_Msk = (0x1 << WRITE_FAIL_Pos),
787 WRITE_FAIL_ENABLED = (0x1 << WRITE_FAIL_Pos),
788 WRITE_FAIL_DISABLED = (0x0 << WRITE_FAIL_Pos),
789 ALMOST_FULL_Pos = 1,
790 ALMOST_FULL_Msk = (0x1 << ALMOST_FULL_Pos),
791 ALMOST_FULL_ENABLED = (0x1 << ALMOST_FULL_Pos),
792 ALMOST_FULL_DISABLED = (0x0 << ALMOST_FULL_Pos),
793 LEARN_FAIL_Pos = 2,
794 LEARN_FAIL_Msk = (0x1 << LEARN_FAIL_Pos),
795 LEARN_FAIL_ENABLED = (0x1 << LEARN_FAIL_Pos),
796 LEARN_FAIL_DISABLED = (0x0 << LEARN_FAIL_Pos),
797 };
798
799}
800namespace SW_LUE_INT_MASK {
801 enum {
802 WRITE_FAIL_Pos = 0,
803 WRITE_FAIL_Msk = (0x1 << WRITE_FAIL_Pos),
804 WRITE_FAIL_ENABLED = (0x0 << WRITE_FAIL_Pos),
805 WRITE_FAIL_DISABLED = (0x1 << WRITE_FAIL_Pos),
806 ALMOST_FULL_Pos = 1,
807 ALMOST_FULL_Msk = (0x1 << ALMOST_FULL_Pos),
808 ALMOST_FULL_ENABLED = (0x0 << ALMOST_FULL_Pos),
809 ALMOST_FULL_DISABLED = (0x1 << ALMOST_FULL_Pos),
810 LEARN_FAIL_Pos = 2,
811 LEARN_FAIL_Msk = (0x1 << LEARN_FAIL_Pos),
812 LEARN_FAIL_ENABLED = (0x0 << LEARN_FAIL_Pos),
813 LEARN_FAIL_DISABLED = (0x1 << LEARN_FAIL_Pos),
814 };
815
816}
817namespace SW_LUE_INDEX_WRITE {
818 enum {
819 FAIL_WRITE_ALMOST_FULL_Pos = 0,
820 FAIL_WRITE_ALMOST_FULL_Msk = (0xFFF << FAIL_WRITE_ALMOST_FULL_Pos),
821 };
822
823}
824namespace SW_LUE_INDEX_LEARN {
825 enum {
826 FAIL_LEARN_Pos = 0,
827 FAIL_LEARN_Msk = (0x3FF << FAIL_LEARN_Pos),
828 };
829
830}
831namespace SW_LUE_INDEX_CPU {
832 enum {
833 CPU_ACCESS_Pos = 0,
834 CPU_ACCESS_Msk = (0x3FF << CPU_ACCESS_Pos),
835 };
836
837}
838namespace SW_UNK_UCAST_CTRL {
839 enum {
840 FWD_PORTS_Pos = 0,
841 FWD_PORTS_Msk = (0xFF << FWD_PORTS_Pos),
842 FWD_Pos = 31,
843 FWD_Msk = (0x1 << FWD_Pos),
844 FWD_ENABLED = (0x1 << FWD_Pos),
845 FWD_DISABLED = (0x0 << FWD_Pos),
846 };
847
848 inline uint32_t FWD_PORT(uint32_t _x)
849 { return (((_x) << FWD_PORTS_Pos) & FWD_PORTS_Msk); }
850
851}
852namespace SW_UNK_MCAST_CTRL {
853 enum {
854 FWD_PORTS_Pos = 0,
855 FWD_PORTS_Msk = (0xFF << FWD_PORTS_Pos),
856 FWD_Pos = 31,
857 FWD_Msk = (0x1 << FWD_Pos),
858 FWD_ENABLED = (0x1 << FWD_Pos),
859 FWD_DISABLED = (0x0 << FWD_Pos),
860 };
861
862 inline uint32_t FWD_PORT(uint32_t _x)
863 { return (((_x) << FWD_PORTS_Pos) & FWD_PORTS_Msk); }
864
865}
866namespace SW_UNK_VID_CTRL {
867 enum {
868 FWD_PORTS_Pos = 0,
869 FWD_PORTS_Msk = (0xFF << FWD_PORTS_Pos),
870 FWD_Pos = 31,
871 FWD_Msk = (0x1 << FWD_Pos),
872 FWD_ENABLED = (0x1 << FWD_Pos),
873 FWD_DISABLED = (0x0 << FWD_Pos),
874 };
875
876 inline uint32_t FWD_PORT(uint32_t _x)
877 { return (((_x) << FWD_PORTS_Pos) & FWD_PORTS_Msk); }
878
879}
880namespace SW_MAC_CTRL {
881 enum {
882 AGGR_BACKOFF_Pos = 24,
883 AGGR_BACKOFF_Msk = (0x1 << AGGR_BACKOFF_Pos),
884 AGGR_BACKOFF_ENABLED = (0x1 << AGGR_BACKOFF_Pos),
885 AGGR_BACKOFF_DISABLED = (0x0 << AGGR_BACKOFF_Pos),
886 PAUSE_UNH_MODE_Pos = 25,
887 PAUSE_UNH_MODE_Msk = (0x1 << PAUSE_UNH_MODE_Pos),
888 PAUSE_UNH_MODE_DROP_EITHER = (0x1 << PAUSE_UNH_MODE_Pos),
889 PAUSE_UNH_MODE_DROP_BOTH = (0x0 << PAUSE_UNH_MODE_Pos),
890 CHECK_LENGTH_Pos = 27,
891 CHECK_LENGTH_Msk = (0x1 << CHECK_LENGTH_Pos),
892 CHECK_LENGTH_ENABLED = (0x1 << CHECK_LENGTH_Pos),
893 CHECK_LENGTH_DISABLED = (0x0 << CHECK_LENGTH_Pos),
894 NEW_BACKOFF_Pos = 31,
895 NEW_BACKOFF_Msk = (0x1 << NEW_BACKOFF_Pos),
896 NEW_BACKOFF_ENABLED = (0x1 << NEW_BACKOFF_Pos),
897 NEW_BACKOFF_DISABLED = (0x0 << NEW_BACKOFF_Pos),
898 PASS_SHORT_FRAME_Pos = 16,
899 PASS_SHORT_FRAME_Msk = (0x1 << PASS_SHORT_FRAME_Pos),
900 PASS_SHORT_FRAME_ENABLED = (0x1 << PASS_SHORT_FRAME_Pos),
901 PASS_SHORT_FRAME_DISABLED = (0x0 << PASS_SHORT_FRAME_Pos),
902 LEGAL_PACKET_SIZE_CHECK_Pos = 17,
903 LEGAL_PACKET_SIZE_CHECK_Msk = (0x1 << LEGAL_PACKET_SIZE_CHECK_Pos),
904 LEGAL_PACKET_SIZE_CHECK_ENABLED = (0x0 << LEGAL_PACKET_SIZE_CHECK_Pos),
905 LEGAL_PACKET_SIZE_CHECK_DISABLED = (0x1 << LEGAL_PACKET_SIZE_CHECK_Pos),
906 JUMBO_PACKET_Pos = 18,
907 JUMBO_PACKET_Msk = (0x1 << JUMBO_PACKET_Pos),
908 JUMBO_PACKET_ENABLED = (0x1 << JUMBO_PACKET_Pos),
909 JUMBO_PACKET_DISABLED = (0x0 << JUMBO_PACKET_Pos),
910 NO_EXC_COLLISION_DROP_Pos = 19,
911 NO_EXC_COLLISION_DROP_Msk = (0x1 << NO_EXC_COLLISION_DROP_Pos),
912 NO_EXC_COLLISION_DROP_ENABLED = (0x1 << NO_EXC_COLLISION_DROP_Pos),
913 NO_EXC_COLLISION_DROP_DISABLED = (0x0 << NO_EXC_COLLISION_DROP_Pos),
914 FAIR_FLOW_CTRL_Pos = 20,
915 FAIR_FLOW_CTRL_Msk = (0x1 << FAIR_FLOW_CTRL_Pos),
916 FAIR_FLOW_CTRL_ENABLED = (0x1 << FAIR_FLOW_CTRL_Pos),
917 FAIR_FLOW_CTRL_DISABLED = (0x0 << FAIR_FLOW_CTRL_Pos),
918 BACK_PRESSURE_Pos = 21,
919 BACK_PRESSURE_Msk = (0x1 << BACK_PRESSURE_Pos),
920 BACK_PRESSURE_CARRIER_SENSE = (0x1 << BACK_PRESSURE_Pos),
921 BACK_PRESSURE_COLLISION = (0x0 << BACK_PRESSURE_Pos),
922 MCAST_STORM_PROT_Pos = 22,
923 MCAST_STORM_PROT_Msk = (0x1 << MCAST_STORM_PROT_Pos),
924 MCAST_STORM_PROT_ENABLED = (0x0 << MCAST_STORM_PROT_Pos),
925 MCAST_STORM_PROT_DISABLED = (0x1 << MCAST_STORM_PROT_Pos),
926 NULL_VID_REPLACE_Pos = 11,
927 NULL_VID_REPLACE_Msk = (0x1 << NULL_VID_REPLACE_Pos),
928 NULL_VID_REPLACE_ENABLED = (0x1 << NULL_VID_REPLACE_Pos),
929 NULL_VID_REPLACE_DISABLED = (0x0 << NULL_VID_REPLACE_Pos),
930 BCAST_STORM_RATE_Pos = 0,
931 BCAST_STORM_RATE_Msk = (0x7FF << BCAST_STORM_RATE_Pos),
932 BCAST_STORM_RATE_DISABLED = (0x0 << BCAST_STORM_RATE_Pos),
933 };
934
935 inline uint32_t BCAST_STORM_RATE(uint32_t _x)
936 { return (((_x) << BCAST_STORM_RATE_Pos & BCAST_STORM_RATE_Msk)); }
937
938}
939namespace SW_MAC_CTRL2 {
940 enum {
941 PASS_PAUSE_Pos = 24,
942 PASS_PAUSE_Msk = (0x1 << PASS_PAUSE_Pos),
943 PASS_PAUSE_ENABLED = (0x1 << PASS_PAUSE_Pos),
944 PASS_PAUSE_DISABLED = (0x0 << PASS_PAUSE_Pos),
945 INGRESS_RATE_LIMIT_PERIOD_Pos = 20,
946 INGRESS_RATE_LIMIT_PERIOD_Msk = (0x3 << INGRESS_RATE_LIMIT_PERIOD_Pos),
947 INGRESS_RATE_LIMIT_PERIOD_16MS = (0x0 << INGRESS_RATE_LIMIT_PERIOD_Pos),
948 INGRESS_RATE_LIMIT_PERIOD_64MS = (0x1 << INGRESS_RATE_LIMIT_PERIOD_Pos),
949 INGRESS_RATE_LIMIT_PERIOD_256MS = (0x2 << INGRESS_RATE_LIMIT_PERIOD_Pos),
950 EGRESS_RATE_LIMIT_BY_Pos = 19,
951 EGRESS_RATE_LIMIT_BY_Msk = (0x1 << EGRESS_RATE_LIMIT_BY_Pos),
952 EGRESS_RATE_LIMIT_BY_QUEUE = (0x1 << EGRESS_RATE_LIMIT_BY_Pos),
953 EGRESS_RATE_LIMIT_BY_PORT = (0x0 << EGRESS_RATE_LIMIT_BY_Pos),
954 MIB_COUNTER_FLUSH_Pos = 15,
955 MIB_COUNTER_FLUSH_Msk = (0x1 << MIB_COUNTER_FLUSH_Pos),
956 MIB_COUNTER_FLUSH_ENABLED = (0x1 << MIB_COUNTER_FLUSH_Pos),
957 MIB_COUNTER_FLUSH_DISABLED = (0x0 << MIB_COUNTER_FLUSH_Pos),
958 MIB_COUNTER_FREEZE_Pos = 14,
959 MIB_COUNTER_FREEZE_Msk = (0x1 << MIB_COUNTER_FREEZE_Pos),
960 MIB_COUNTER_FREEZE_ENABLED = (0x1 << MIB_COUNTER_FREEZE_Pos),
961 MIB_COUNTER_FREEZE_DISABLED = (0x0 << MIB_COUNTER_FREEZE_Pos),
962 };
963
964}
965namespace SW_MAC_802_1P_MAP {
966 enum {
967 };
968
969 inline uint32_t PCP_VAL_Pos(uint32_t _x)
970 { return (28-((!(_x&1))*4)-(((_x>>1)&0x3)*8)); }
971 inline uint32_t PCP_VAL_Msk(uint32_t _x)
972 { return (0xF << PCP_VAL_Pos(_x)); }
973 inline uint32_t PCP_VAL(uint32_t _x, uint32_t _val)
974 { return (((_val) << PCP_VAL_Pos(_x) & PCP_VAL_Msk(_x))); }
975
976}
977namespace SW_MAC_TOS_CTRL {
978 enum {
979 TOS_DCSP_REMAP_Pos = 0,
980 TOS_DCSP_REMAP_Msk = (0x1 << TOS_DCSP_REMAP_Pos),
981 TOS_DCSP_REMAP_ENABLED = (0x1 << TOS_DCSP_REMAP_Pos),
982 TOS_DCSP_REMAP_DISABLED = (0x0 << TOS_DCSP_REMAP_Pos),
983 TOS_DCSP_REMARK_Pos = 1,
984 TOS_DCSP_REMARK_Msk = (0x1 << TOS_DCSP_REMARK_Pos),
985 TOS_DCSP_REMARK_ENABLED = (0x1 << TOS_DCSP_REMARK_Pos),
986 TOS_DCSP_REMARK_DISABLED = (0x0 << TOS_DCSP_REMARK_Pos),
987 };
988
989}
990namespace SW_MAC_TOS_PRIO_31 {
991 enum {
992 };
993
994 inline uint32_t REG(uint32_t _x)
995 { return ((_x>>1)&0x1F); }
996 inline uint32_t DCSP_VAL_Pos(uint32_t _x)
997 { return (((_x&1))*4); }
998 inline uint32_t DCSP_VAL_Msk(uint32_t _x)
999 { return (0xF << DCSP_VAL_Pos(_x)); }
1000 inline uint32_t DCSP_VAL(uint32_t _x, uint32_t _val)
1001 { return (((_val) << DCSP_VAL_Pos(_x) & DCSP_VAL_Msk(_x))); }
1002
1003}
1004namespace SW_MRI_CTRL {
1005 enum {
1006 MIRROR_FILTER_Pos = 0,
1007 MIRROR_FILTER_Msk = (0x1 << MIRROR_FILTER_Pos),
1008 MIRROR_FILTER_AND = (0x1 << MIRROR_FILTER_Pos),
1009 MIRROR_FILTER_OR = (0x0 << MIRROR_FILTER_Pos),
1010 IPV6_MLD_SNOOP_Pos = 2,
1011 IPV6_MLD_SNOOP_Msk = (0x1 << IPV6_MLD_SNOOP_Pos),
1012 IPV6_MLD_SNOOP_ENABLED = (0x1 << IPV6_MLD_SNOOP_Pos),
1013 IPV6_MLD_SNOOP_DISABLED = (0x0 << IPV6_MLD_SNOOP_Pos),
1014 IPV6_MLD_OPTION_Pos = 3,
1015 IPV6_MLD_OPTION_Msk = (0x1 << IPV6_MLD_OPTION_Pos),
1016 IPV6_MLD_OPTION_ENABLED = (0x1 << IPV6_MLD_OPTION_Pos),
1017 IPV6_MLD_OPTION_DISABLED = (0x0 << IPV6_MLD_OPTION_Pos),
1018 IGMP_SNOOP_Pos = 6,
1019 IGMP_SNOOP_Msk = (0x1 << IGMP_SNOOP_Pos),
1020 IGMP_SNOOP_ENABLED = (0x1 << IGMP_SNOOP_Pos),
1021 IGMP_SNOOP_DISABLED = (0x0 << IGMP_SNOOP_Pos),
1022 };
1023
1024}
1025namespace SW_WRED_DSCP_COLOR {
1026 enum {
1027 GREEN_Pos = 0,
1028 GREEN_Msk = (0x3 << GREEN_Pos),
1029 YELLOW_Pos = 2,
1030 YELLOW_Msk = (0x3 << YELLOW_Pos),
1031 RED_Pos = 4,
1032 RED_Msk = (0x3 << RED_Pos),
1033 NO_COLOR_Pos = 6,
1034 NO_COLOR_Msk = (0x3 << NO_COLOR_Pos),
1035 };
1036
1037 inline uint32_t GREEN(uint32_t _x)
1038 { return (((_x) << GREEN_Pos) & GREEN_Msk); }
1039 inline uint32_t YELLOW(uint32_t _x)
1040 { return (((_x) << YELLOW_Pos) & YELLOW_Msk); }
1041 inline uint32_t RED(uint32_t _x)
1042 { return (((_x) << RED_Pos) & RED_Msk); }
1043 inline uint32_t NO_COLOR(uint32_t _x)
1044 { return (((_x) << NO_COLOR_Pos) & NO_COLOR_Msk); }
1045
1046}
1047namespace SW_QM_CTRL {
1048 enum {
1049 UNICAST_VLAN_BOUNDARY_Pos = 1,
1050 UNICAST_VLAN_BOUNDARY_Msk = (0x1 << UNICAST_VLAN_BOUNDARY_Pos),
1051 UNICAST_VLAN_BOUNDARY_ENABLED = (0x1 << UNICAST_VLAN_BOUNDARY_Pos),
1052 UNICAST_VLAN_BOUNDARY_DISABLED = (0x0 << UNICAST_VLAN_BOUNDARY_Pos),
1053 PRIO_SCHEME_SELECT_Pos = 6,
1054 PRIO_SCHEME_SELECT_Msk = (0x1 << PRIO_SCHEME_SELECT_Pos),
1055 PRIO_SCHEME_SELECT_MAP_3_HI = (0x0 << PRIO_SCHEME_SELECT_Pos),
1056 PRIO_SCHEME_SELECT_MAP_2_HI = (0x2 << PRIO_SCHEME_SELECT_Pos),
1057 PRIO_SCHEME_SELECT_MAP_0_LO = (0x3 << PRIO_SCHEME_SELECT_Pos),
1058 };
1059
1060}
1061
1062namespace VLAN_ENTRY {
1063 enum {
1064 FID_Pos = 0,
1065 FID_Msk = (0x7F << FID_Pos),
1066 MSTP_INDEX_Pos = 12,
1067 MSTP_INDEX_Msk = (0x7 << MSTP_INDEX_Pos),
1068 PRIORITY_Pos = 24,
1069 PRIORITY_Msk = (0x3 << PRIORITY_Pos),
1070 FORWARD_OPTION_Pos = 27,
1071 FORWARD_OPTION_Msk = (0x1 << FORWARD_OPTION_Pos),
1072 FORWARD_OPTION_OTHER = (0x0 << FORWARD_OPTION_Pos),
1073 FORWARD_OPTION_VLAN_MAP = (0x1 << FORWARD_OPTION_Pos),
1074 VALID_Pos = 31,
1075 VALID_Msk = (0x1 << VALID_Pos),
1076 VALID_FALSE = (0x0 << VALID_Pos),
1077 VALID_TRUE = (0x1 << VALID_Pos),
1078 };
1079
1080 inline uint32_t FID(uint32_t _x)
1081 { return (((_x) << FID_Pos) & FID_Msk); }
1082 inline uint32_t MSTP_INDEX(uint32_t _x)
1083 { return (((_x) << MSTP_INDEX_Pos) & MSTP_INDEX_Msk); }
1084 inline uint32_t PRIORITY(uint32_t _x)
1085 { return (((_x) << PRIORITY_Pos) & PRIORITY_Msk); }
1086
1087}
1088namespace VLAN_UNTAG {
1089 enum {
1090 };
1091
1092 inline uint32_t PORT(uint32_t _x)
1093 { return (( 0x1 << (((_x)-1) & 0x1F))); }
1094
1095}
1096namespace VLAN_FORWARD {
1097 enum {
1098 };
1099
1100 inline uint32_t PORT(uint32_t _x)
1101 { return (( 0x1 << (((_x)-1) & 0x1F))); }
1102
1103}
1104namespace VLAN_INDEX {
1105 enum {
1106 INDEX_Pos = 0,
1107 INDEX_Msk = (0xFFF << INDEX_Pos),
1108 };
1109
1110 inline uint32_t INDEX(uint32_t _x)
1111 { return (((_x) << INDEX_Pos) & INDEX_Msk); }
1112
1113}
1114namespace VLAN_CTRL {
1115 enum {
1116 ACTION_Pos = 0,
1117 ACTION_Msk = (0x3 << ACTION_Pos),
1118 ACTION_NOP = (0x0 << ACTION_Pos),
1119 ACTION_WRITE = (0x1 << ACTION_Pos),
1120 ACTION_READ = (0x2 << ACTION_Pos),
1121 ACTION_CLEAR = (0x3 << ACTION_Pos),
1122 START_ACTION_Pos = 7,
1123 START_ACTION_Msk = (0x1 << START_ACTION_Pos),
1124 START_ACTION_START = (0x1 << START_ACTION_Pos),
1125 START_ACTION_COMPLETE = (0x1 << START_ACTION_Pos),
1126 };
1127
1128}
1129namespace ALU_INDEX {
1130 enum {
1131 MAC_ADDR_HI_Pos = 0,
1132 MAC_ADDR_HI_Msk = (0xFFFF << MAC_ADDR_HI_Pos),
1133 FID_INDEX_Pos = 16,
1134 FID_INDEX_Msk = (0x7F << FID_INDEX_Pos),
1135 };
1136
1137 inline uint32_t MAC_ADDR_HI(uint32_t _x)
1138 { return (((_x) << MAC_ADDR_HI_Pos) & MAC_ADDR_HI_Msk); }
1139 inline uint32_t FID_INDEX(uint32_t _x)
1140 { return (((_x) << FID_INDEX_Pos) & FID_INDEX_Msk); }
1141
1142}
1143namespace ALU_INDEX2 {
1144 enum {
1145 MAC_ADDR_LO_Pos = 0,
1146 MAC_ADDR_LO_Msk = (0xFFFFFFFF << MAC_ADDR_LO_Pos),
1147 ALU_DIRECT_INDEX_Pos = 0,
1148 ALU_DIRECT_INDEX_Msk = (0xFFF << ALU_DIRECT_INDEX_Pos),
1149 };
1150
1151 inline uint32_t MAC_ADDR_LO(uint32_t _x)
1152 { return (((_x) << MAC_ADDR_LO_Pos) & MAC_ADDR_LO_Msk); }
1153 inline uint32_t ALU_DIRECT_INDEX(uint32_t _x)
1154 { return (((_x) << ALU_DIRECT_INDEX_Pos) & ALU_DIRECT_INDEX_Msk); }
1155
1156}
1157namespace ALU_CTRL {
1158 enum {
1159 ACTION_Pos = 0,
1160 ACTION_Msk = (0x3 << ACTION_Pos),
1161 ACTION_NOP = (0x0 << ACTION_Pos),
1162 ACTION_WRITE = (0x1 << ACTION_Pos),
1163 ACTION_READ = (0x2 << ACTION_Pos),
1164 ACTION_SEARCH = (0x3 << ACTION_Pos),
1165 DIRECT_Pos = 2,
1166 DIRECT_Msk = (0x1 << DIRECT_Pos),
1167 DIRECT_DIRECT = (0x1 << DIRECT_Pos),
1168 DIRECT_HASHED = (0x0 << DIRECT_Pos),
1169 VALID_OR_STOP_Pos = 5,
1170 VALID_OR_STOP_Msk = (0x1 << VALID_OR_STOP_Pos),
1171 VALID_OR_STOP_TRUE = (0x1 << VALID_OR_STOP_Pos),
1172 VALID_OR_STOP_FALSE = (0x0 << VALID_OR_STOP_Pos),
1173 VALID_Pos = 6,
1174 VALID_Msk = (0x1 << VALID_Pos),
1175 VALID_TRUE = (0x1 << VALID_Pos),
1176 VALID_FALSE = (0x0 << VALID_Pos),
1177 START_Pos = 7,
1178 START_Msk = (0x1 << START_Pos),
1179 START_START = (0x1 << START_Pos),
1180 START_COMPLETE = (0x0 << START_Pos),
1181 VALID_CNT_Pos = 0,
1182 VALID_CNT_Msk = (0x3FFF << VALID_CNT_Pos),
1183 };
1184
1185}
1186namespace ALU_STAT_CTRL {
1187 enum {
1188 ACTION_Pos = 0,
1189 ACTION_Msk = (0x1 << ACTION_Pos),
1190 ACTION_WRITE = (0x0 << ACTION_Pos),
1191 ACTION_READ = (0x1 << ACTION_Pos),
1192 TABLE_Pos = 1,
1193 TABLE_Msk = (0x1 << TABLE_Pos),
1194 TABLE_STATIC_ADDR = (0x0 << TABLE_Pos),
1195 TABLE_STATIC_RESV_MCAST = (0x1 << TABLE_Pos),
1196 START_Pos = 7,
1197 START_Msk = (0x1 << START_Pos),
1198 START_NOP = (0x0 << START_Pos),
1199 START_START = (0x1 << START_Pos),
1200 START_COMPLETE = (0x0 << START_Pos),
1201 TABLE_INDEX_Pos = 16,
1202 TABLE_INDEX_Msk = (0x3F << TABLE_INDEX_Pos),
1203 };
1204
1205 inline uint32_t TABLE_INDEX(uint32_t _x)
1206 { return (((_x) << TABLE_INDEX_Pos) & TABLE_INDEX_Msk); }
1207
1208}
1209namespace ALU_VAL_A {
1210 enum {
1211 MSTP_Pos = 0,
1212 MSTP_Msk = (0x7 << MSTP_Pos),
1213 PRIO_AGE_Pos = 26,
1214 PRIO_AGE_Msk = (0x3 << PRIO_AGE_Pos),
1215 DST_FILTER_Pos = 29,
1216 DST_FILTER_Msk = (0x1 << DST_FILTER_Pos),
1217 DST_FILTER_ENABLED = (0x1 << DST_FILTER_Pos),
1218 DST_FILTER_DISABLED = (0x0 << DST_FILTER_Pos),
1219 SRC_FILTER_Pos = 30,
1220 SRC_FILTER_Msk = (0x1 << SRC_FILTER_Pos),
1221 SRC_FILTER_ENABLED = (0x1 << SRC_FILTER_Pos),
1222 SRC_FILTER_DISABLED = (0x0 << SRC_FILTER_Pos),
1223 ALU_STATIC_Pos = 31,
1224 ALU_STATIC_Msk = (0x1 << ALU_STATIC_Pos),
1225 ALU_STATIC_STATIC = (0x1 << ALU_STATIC_Pos),
1226 ALU_STATIC_DYN = (0x0 << ALU_STATIC_Pos),
1227 STATIC_VALID_Pos = 31,
1228 STATIC_VALID_Msk = (0x1 << STATIC_VALID_Pos),
1229 STATIC_VALID_TRUE = (0x1 << STATIC_VALID_Pos),
1230 STATIC_VALID_FALSE = (0x0 << STATIC_VALID_Pos),
1231 };
1232
1233 inline uint32_t MSTP(uint32_t _x)
1234 { return (((_x) << MSTP_Pos) & MSTP_Msk); }
1235 inline uint32_t PRIO_AGE(uint32_t _x)
1236 { return (((_x) << PRIO_AGE_Pos) & PRIO_AGE_Msk); }
1237
1238}
1239namespace ALU_VAL_B {
1240 enum {
1241 PORTS_Pos = 0,
1242 PORTS_Msk = (0x1FFFFFFF << PORTS_Pos),
1243 USE_FID_Pos = 30,
1244 USE_FID_Msk = (0x1 << USE_FID_Pos),
1245 USE_FID_ENABLED = (0x1 << USE_FID_Pos),
1246 USE_FID_DISABLED = (0x0 << USE_FID_Pos),
1247 OVERRIDE_Pos = 31,
1248 OVERRIDE_Msk = (0x1 << OVERRIDE_Pos),
1249 OVERRIDE_ENABLED = (0x1 << OVERRIDE_Pos),
1250 OVERRIDE_DISABLED = (0x0 << OVERRIDE_Pos),
1251 };
1252
1253 inline uint32_t PORT(uint32_t _x)
1254 { return (((_x) << PORTS_Pos) & PORTS_Msk); }
1255
1256}
1257namespace ALU_VAL_C {
1258 enum {
1259 MAC_ADDR_HI_Pos = 0,
1260 MAC_ADDR_HI_Msk = (0xFFFF << MAC_ADDR_HI_Pos),
1261 FID_Pos = 16,
1262 FID_Msk = (0x7F << FID_Pos),
1263 };
1264
1265 inline uint32_t MAC_ADDR_HI(uint32_t _x)
1266 { return (((_x) << MAC_ADDR_HI_Pos) & MAC_ADDR_HI_Msk); }
1267 inline uint32_t FID(uint32_t _x)
1268 { return (((_x) << FID_Pos) & FID_Msk); }
1269
1270}
1271namespace ALU_VAL_D {
1272 enum {
1273 MAC_ADDR_LO_Pos = 0,
1274 MAC_ADDR_LO_Msk = (0xFFFFFFFF << MAC_ADDR_LO_Pos),
1275 };
1276
1277 inline uint32_t MAC_ADDR_LO(uint32_t _x)
1278 { return (((_x) << MAC_ADDR_LO_Pos) & MAC_ADDR_LO_Msk); }
1279
1280}
1281
1282namespace PTP_CLK_CTRL {
1283 enum {
1284 CLK_RESET_Pos = 0,
1285 CLK_RESET_Msk = (0x1 << CLK_RESET_Pos),
1286 CLK_RESET_RESET = (0x1 << CLK_RESET_Pos),
1287 CLK_Pos = 1,
1288 CLK_Msk = (0x1 << CLK_Pos),
1289 CLK_ENABLED = (0x1 << CLK_Pos),
1290 CLK_DISABLED = (0x0 << CLK_Pos),
1291 CLK_ADJ_Pos = 2,
1292 CLK_ADJ_Msk = (0x1 << CLK_ADJ_Pos),
1293 CLK_ADJ_ENABLED = (0x1 << CLK_ADJ_Pos),
1294 CLK_ADJ_DISABLED = (0x0 << CLK_ADJ_Pos),
1295 LOAD_Pos = 3,
1296 LOAD_Msk = (0x1 << LOAD_Pos),
1297 LOAD_ENABLED = (0x1 << LOAD_Pos),
1298 READ_Pos = 4,
1299 READ_Msk = (0x1 << READ_Pos),
1300 READ_ENABLED = (0x1 << READ_Pos),
1301 STEP_DIR_Pos = 5,
1302 STEP_DIR_Msk = (0x1 << STEP_DIR_Pos),
1303 STEP_DIR_ADD = (0x1 << STEP_DIR_Pos),
1304 STEP_DIR_SUB = (0x0 << STEP_DIR_Pos),
1305 STEP_ADJ_Pos = 6,
1306 STEP_ADJ_Msk = (0x1 << STEP_ADJ_Pos),
1307 STEP_ADJ_ENABLED = (0x1 << STEP_ADJ_Pos),
1308 STEP_ADJ_DISABLED = (0x0 << STEP_ADJ_Pos),
1309 SW_FREQ_ADJ_Pos = 15,
1310 SW_FREQ_ADJ_Msk = (0x1 << SW_FREQ_ADJ_Pos),
1311 SW_FREQ_ADJ_ENABLED = (0x1 << SW_FREQ_ADJ_Pos),
1312 SW_FREQ_ADJ_DISABLED = (0x0 << SW_FREQ_ADJ_Pos),
1313 };
1314
1315}
1316namespace PTP_RTC_PHASE {
1317 enum {
1318 PHASE_Pos = 0,
1319 PHASE_Msk = (0x3 << PHASE_Pos),
1320 };
1321
1322 inline uint32_t PHASE(uint32_t _x)
1323 { return (((_x) << PHASE_Pos) & PHASE_Msk); }
1324
1325}
1326namespace PTP_RTC_NANO {
1327 enum {
1328 NANOSEC_Pos = 0,
1329 NANOSEC_Msk = (0xFFFFFFFF << NANOSEC_Pos),
1330 };
1331
1332 inline uint32_t NANOSEC(uint32_t _x)
1333 { return (((_x) << NANOSEC_Pos) & NANOSEC_Msk); }
1334
1335}
1336namespace PTP_RTC_SEC {
1337 enum {
1338 SEC_Pos = 0,
1339 SEC_Msk = (0xFFFFFFFF << SEC_Pos),
1340 };
1341
1342 inline uint32_t SEC(uint32_t _x)
1343 { return (((_x) << SEC_Pos) & SEC_Msk); }
1344
1345}
1346namespace PTP_RTC_SUBNANO {
1347 enum {
1348 SUB_NANO_Pos = 0,
1349 SUB_NANO_Msk = (0x3FFFFFFF << SUB_NANO_Pos),
1350 TMP_ADJ_Pos = 30,
1351 TMP_ADJ_Msk = (0x1 << TMP_ADJ_Pos),
1352 TMP_ADJ_ENABLED = (0x1 << TMP_ADJ_Pos),
1353 TMP_ADJ_DISABLED = (0x0 << TMP_ADJ_Pos),
1354 TMP_ADJ_DIR_Pos = 31,
1355 TMP_ADJ_DIR_Msk = (0x1 << TMP_ADJ_DIR_Pos),
1356 TMP_ADJ_DIR_ENABLED = (0x1 << TMP_ADJ_DIR_Pos),
1357 TMP_ADJ_DIR_DISABLED = (0x0 << TMP_ADJ_DIR_Pos),
1358 };
1359
1360 inline uint32_t SUB_NANO(uint32_t _x)
1361 { return (((_x) << SUB_NANO_Pos) & SUB_NANO_Msk); }
1362
1363}
1364namespace PTP_MSG_CONFIG {
1365 enum {
1366 IPV4_CSUM_UPDATE_Pos = 2,
1367 IPV4_CSUM_UPDATE_Msk = (0x1 << IPV4_CSUM_UPDATE_Pos),
1368 IPV4_CSUM_UPDATE_ENABLED = (0x1 << IPV4_CSUM_UPDATE_Pos),
1369 IPV4_CSUM_UPDATE_DISABLED = (0x0 << IPV4_CSUM_UPDATE_Pos),
1370 DOMAIN_CHECK_Pos = 4,
1371 DOMAIN_CHECK_Msk = (0x1 << DOMAIN_CHECK_Pos),
1372 DOMAIN_CHECK_ENABLED = (0x1 << DOMAIN_CHECK_Pos),
1373 DOMAIN_CHECK_DISABLED = (0x0 << DOMAIN_CHECK_Pos),
1374 DROP_SYNC_DELAY_REQ_Pos = 5,
1375 DROP_SYNC_DELAY_REQ_Msk = (0x1 << DROP_SYNC_DELAY_REQ_Pos),
1376 DROP_SYNC_DELAY_REQ_ENABLED = (0x1 << DROP_SYNC_DELAY_REQ_Pos),
1377 DROP_SYNC_DELAY_REQ_DISABLED = (0x0 << DROP_SYNC_DELAY_REQ_Pos),
1378 PDELAY_CHECK_Pos = 7,
1379 PDELAY_CHECK_Msk = (0x1 << PDELAY_CHECK_Pos),
1380 PDELAY_CHECK_ENABLED = (0x1 << PDELAY_CHECK_Pos),
1381 PDELAY_CHECK_DISABLED = (0x0 << PDELAY_CHECK_Pos),
1382 DELAY_CHECK_Pos = 8,
1383 DELAY_CHECK_Msk = (0x1 << DELAY_CHECK_Pos),
1384 DELAY_CHECK_ENABLED = (0x1 << DELAY_CHECK_Pos),
1385 DELAY_CHECK_DISABLED = (0x0 << DELAY_CHECK_Pos),
1386 SYNC_CHECK_Pos = 9,
1387 SYNC_CHECK_Msk = (0x1 << SYNC_CHECK_Pos),
1388 SYNC_CHECK_ENABLED = (0x1 << SYNC_CHECK_Pos),
1389 SYNC_CHECK_DISABLED = (0x0 << SYNC_CHECK_Pos),
1390 ALL_PTP_HI_PRIO_Pos = 10,
1391 ALL_PTP_HI_PRIO_Msk = (0x1 << ALL_PTP_HI_PRIO_Pos),
1392 ALL_PTP_HI_PRIO_ENABLED = (0x1 << ALL_PTP_HI_PRIO_Pos),
1393 ALL_PTP_HI_PRIO_DISABLED = (0x0 << ALL_PTP_HI_PRIO_Pos),
1394 ALT_MASTER_Pos = 11,
1395 ALT_MASTER_Msk = (0x1 << ALT_MASTER_Pos),
1396 ALT_MASTER_ENABLED = (0x1 << ALT_MASTER_Pos),
1397 ALT_MASTER_DISABLED = (0x0 << ALT_MASTER_Pos),
1398 UNICAST_Pos = 12,
1399 UNICAST_Msk = (0x1 << UNICAST_Pos),
1400 UNICAST_ENABLED = (0x1 << UNICAST_Pos),
1401 UNICAST_DISABLED = (0x0 << UNICAST_Pos),
1402 MODE_Pos = 17,
1403 MODE_Msk = (0x1 << MODE_Pos),
1404 MODE_MASTER = (0x1 << MODE_Pos),
1405 MODE_SLAVE = (0x0 << MODE_Pos),
1406 TC_Pos = 18,
1407 TC_Msk = (0x1 << TC_Pos),
1408 TC_P2P = (0x1 << TC_Pos),
1409 TC_E2E = (0x0 << TC_Pos),
1410 IPV6_UDP_Pos = 19,
1411 IPV6_UDP_Msk = (0x1 << IPV6_UDP_Pos),
1412 IPV6_UDP_ENABLED = (0x1 << IPV6_UDP_Pos),
1413 IPV6_UDP_DISABLED = (0x0 << IPV6_UDP_Pos),
1414 IPV4_UDP_Pos = 20,
1415 IPV4_UDP_Msk = (0x1 << IPV4_UDP_Pos),
1416 IPV4_UDP_ENABLED = (0x1 << IPV4_UDP_Pos),
1417 IPV4_UDP_DISABLED = (0x0 << IPV4_UDP_Pos),
1418 ETH_MSG_Pos = 21,
1419 ETH_MSG_Msk = (0x1 << ETH_MSG_Pos),
1420 ETH_MSG_ENABLED = (0x1 << ETH_MSG_Pos),
1421 ETH_MSG_DISABLED = (0x0 << ETH_MSG_Pos),
1422 PTP_Pos = 22,
1423 PTP_Msk = (0x1 << PTP_Pos),
1424 PTP_ENABLED = (0x1 << PTP_Pos),
1425 PTP_DISABLED = (0x0 << PTP_Pos),
1426 };
1427
1428}
1429namespace PTP_DOMAIN_VERSION {
1430 enum {
1431 DOMAIN_Pos = 0,
1432 DOMAIN_Msk = (0xFF << DOMAIN_Pos),
1433 VERSION_Pos = 8,
1434 VERSION_Msk = (0xF << VERSION_Pos),
1435 };
1436
1437 inline uint32_t DOMAIN_VAL(uint32_t _x)
1438 { return (((_x) << DOMAIN_Pos) & DOMAIN_Msk); }
1439 inline uint32_t VERSION_VAL(uint32_t _x)
1440 { return (((_x) << VERSION_Pos) & VERSION_Msk); }
1441
1442}
1443namespace PTP_UNIT_INDEX {
1444 enum {
1445 TRIG_UNIT_Pos = 0,
1446 TRIG_UNIT_Msk = (0x3 << TRIG_UNIT_Pos),
1447 TIMESTAMP_UNIT_Pos = 8,
1448 TIMESTAMP_UNIT_Msk = (0x1 << TIMESTAMP_UNIT_Pos),
1449 GPIO_INDEX_Pos = 16,
1450 GPIO_INDEX_Msk = (0xFF << GPIO_INDEX_Pos),
1451 };
1452
1453 inline uint32_t TRIG_UNIT(uint32_t _x)
1454 { return (((_x) << TRIG_UNIT_Pos) & TRIG_UNIT_Msk); }
1455 inline uint32_t TIMESTAMP_UNIT(uint32_t _x)
1456 { return (((_x) << TIMESTAMP_UNIT_Pos) & TIMESTAMP_UNIT_Msk); }
1457 inline uint32_t GPIO_INDEX(uint32_t _x)
1458 { return (((_x) << GPIO_INDEX_Pos) & GPIO_INDEX_Msk); }
1459
1460}
1461namespace PTP_TRIG_STATUS {
1462 enum {
1463 DONE_Pos = 0,
1464 DONE_Msk = (0x7 << DONE_Pos),
1465 ERROR_Pos = 16,
1466 ERROR_Msk = (0x7 << ERROR_Pos),
1467 };
1468
1469 inline uint32_t DONE(uint32_t _x)
1470 { return (((_x) << DONE_Pos) & DONE_Msk); }
1471 inline uint32_t ERROR(uint32_t _x)
1472 { return (((_x) << ERROR_Pos) & ERROR_Msk); }
1473
1474}
1475namespace PTP_INT_STATUS {
1476 enum {
1477 TIMESTAMP_IRQ_Pos = 0,
1478 TIMESTAMP_IRQ_Msk = (0x7 << TIMESTAMP_IRQ_Pos),
1479 TRIG_IRQ_Pos = 16,
1480 TRIG_IRQ_Msk = (0x7 << TRIG_IRQ_Pos),
1481 };
1482
1483 inline uint32_t TIMESTAMP_IRQ(uint32_t _x)
1484 { return (((_x) << TIMESTAMP_IRQ_Pos) & TIMESTAMP_IRQ_Msk); }
1485 inline uint32_t TRIG_IRQ(uint32_t _x)
1486 { return (((_x) << TRIG_IRQ_Pos) & TRIG_IRQ_Msk); }
1487
1488}
1489namespace PTP_TS_CTRL {
1490 enum {
1491 TS_SW_RESET_Pos = 0,
1492 TS_SW_RESET_Msk = (0x1 << TS_SW_RESET_Pos),
1493 TS_SW_RESET = (0x1 << TS_SW_RESET_Pos),
1494 TS_Pos = 1,
1495 TS_Msk = (0x1 << TS_Pos),
1496 TS_ENABLED = (0x1 << TS_Pos),
1497 TS_DISABLED = (0x0 << TS_Pos),
1498 TRIG_RESET_Pos = 2,
1499 TRIG_RESET_Msk = (0x1 << TRIG_RESET_Pos),
1500 TRIG_RESET = (0x1 << TRIG_RESET_Pos),
1501 TRIG_Pos = 3,
1502 TRIG_Msk = (0x1 << TRIG_Pos),
1503 TRIG_ENABLED = (0x1 << TRIG_Pos),
1504 TRIG_DISABLED = (0x0 << TRIG_Pos),
1505 TRIG_ACTIVE_Pos = 4,
1506 TRIG_ACTIVE_Msk = (0x1 << TRIG_ACTIVE_Pos),
1507 TRIG_ACTIVE_ENABLED = (0x1 << TRIG_ACTIVE_Pos),
1508 TRIG_ACTIVE_DISABLED = (0x0 << TRIG_ACTIVE_Pos),
1509 TS_INT_Pos = 5,
1510 TS_INT_Msk = (0x1 << TS_INT_Pos),
1511 TS_INT_ENABLED = (0x1 << TS_INT_Pos),
1512 TS_INT_DISABLED = (0x0 << TS_INT_Pos),
1513 GPIO_DIR_Pos = 6,
1514 GPIO_DIR_Msk = (0x1 << GPIO_DIR_Pos),
1515 GPIO_DIR_TS_INPUT = (0x1 << GPIO_DIR_Pos),
1516 GPIO_DIR_TRIG_OUT = (0x0 << GPIO_DIR_Pos),
1517 GPIO_IN_Pos = 7,
1518 GPIO_IN_Msk = (0x1 << GPIO_IN_Pos),
1519 GPIO_OUT_SEL_Pos = 8,
1520 GPIO_OUT_SEL_Msk = (0x1 << GPIO_OUT_SEL_Pos),
1521 GPIO_OUT_SEL_COMB = (0x1 << GPIO_OUT_SEL_Pos),
1522 GPIO_OUT_SEL_FF = (0x0 << GPIO_OUT_SEL_Pos),
1523 };
1524
1525}
1526namespace PTP_TRIG_TARGET_NANO {
1527 enum {
1528 NANOSEC_Pos = 0,
1529 NANOSEC_Msk = (0x3FFFFFFF << NANOSEC_Pos),
1530 };
1531
1532 inline uint32_t NANOSEC(uint32_t _x)
1533 { return (((_x) << NANOSEC_Pos) & NANOSEC_Msk); }
1534
1535}
1536namespace PTP_TRIG_TARGET_SEC {
1537 enum {
1538 SEC_Pos = 0,
1539 SEC_Msk = (0xFFFFFFFF << SEC_Pos),
1540 };
1541
1542 inline uint32_t SEC(uint32_t _x)
1543 { return (((_x) << SEC_Pos) & SEC_Msk); }
1544
1545}
1546namespace PTP_TRIG_CTRL {
1547 enum {
1548 TRIG_ITERATION_Pos = 0,
1549 TRIG_ITERATION_Msk = (0xFFFF << TRIG_ITERATION_Pos),
1550 TRIG_GPO_Pos = 16,
1551 TRIG_GPO_Msk = (0x1 << TRIG_GPO_Pos),
1552 TRIG_GPO_GPIO2 = (0x1 << TRIG_GPO_Pos),
1553 TRIG_GPO_GPIO1 = (0x0 << TRIG_GPO_Pos),
1554 TRIG_EVT_OUT_Pos = 20,
1555 TRIG_EVT_OUT_Msk = (0x7 << TRIG_EVT_OUT_Pos),
1556 TRIG_EVT_OUT_EDGE_NEG = (0x0 << TRIG_EVT_OUT_Pos),
1557 TRIG_EVT_OUT_EDGE_POS = (0x1 << TRIG_EVT_OUT_Pos),
1558 TRIG_EVT_OUT_PULSE_NEG = (0x2 << TRIG_EVT_OUT_Pos),
1559 TRIG_EVT_OUT_PLUSE_POS = (0x3 << TRIG_EVT_OUT_Pos),
1560 TRIG_EVT_OUT_PER_NEG = (0x4 << TRIG_EVT_OUT_Pos),
1561 TRIG_EVT_OUT_PER_POS = (0x5 << TRIG_EVT_OUT_Pos),
1562 TRIG_EVT_OUT_PATTERN = (0x6 << TRIG_EVT_OUT_Pos),
1563 TRIG_EDGE_Pos = 23,
1564 TRIG_EDGE_Msk = (0x1 << TRIG_EDGE_Pos),
1565 TRIG_EDGE_POS = (0x0 << TRIG_EDGE_Pos),
1566 TRIG_EDGE_NEG = (0x1 << TRIG_EDGE_Pos),
1567 TRIG_NOTIFY_Pos = 24,
1568 TRIG_NOTIFY_Msk = (0x1 << TRIG_NOTIFY_Pos),
1569 TRIG_NOTIFY_ENABLED = (0x1 << TRIG_NOTIFY_Pos),
1570 TRIG_NOTIFY_DISABLED = (0x0 << TRIG_NOTIFY_Pos),
1571 TRIG_NOW_Pos = 25,
1572 TRIG_NOW_Msk = (0x1 << TRIG_NOW_Pos),
1573 TRIG_NOW = (0x1 << TRIG_NOW_Pos),
1574 CASCADE_UPSTREAM_SEL_Pos = 26,
1575 CASCADE_UPSTREAM_SEL_Msk = (0x3 << CASCADE_UPSTREAM_SEL_Pos),
1576 CASCADE_TAIL_Pos = 30,
1577 CASCADE_TAIL_Msk = (0x1 << CASCADE_TAIL_Pos),
1578 CASCADE_TAIL_ENABLED = (0x1 << CASCADE_TAIL_Pos),
1579 CASCADE_TAIL_DISABLED = (0x0 << CASCADE_TAIL_Pos),
1580 CASCADE_Pos = 31,
1581 CASCADE_Msk = (0x1 << CASCADE_Pos),
1582 CASCADE_ENABLED = (0x1 << CASCADE_Pos),
1583 CASCADE_DISABLED = (0x0 << CASCADE_Pos),
1584 };
1585
1586 inline uint32_t TRIG_ITERATION(uint32_t _x)
1587 { return (((_x) << TRIG_ITERATION_Pos) & TRIG_ITERATION_Msk); }
1588 inline uint32_t CASCADE_UPSTREAM_SEL(uint32_t _x)
1589 { return (((_x) << CASCADE_UPSTREAM_SEL_Pos) & CASCADE_UPSTREAM_SEL_Msk); }
1590
1591}
1592namespace PTP_TRIG_CYC_WIDTH {
1593 enum {
1594 WIDTH_Pos = 0,
1595 WIDTH_Msk = (0xFFFFFFFF << WIDTH_Pos),
1596 };
1597
1598 inline uint32_t WIDTH(uint32_t _x)
1599 { return (((_x) << WIDTH_Pos) & WIDTH_Msk); }
1600
1601}
1602namespace PTP_TRIG_CYC_CNT {
1603 enum {
1604 BIT_PATTERN_Pos = 0,
1605 BIT_PATTERN_Msk = (0xFFFF << BIT_PATTERN_Pos),
1606 CYCLE_CNT_Pos = 16,
1607 CYCLE_CNT_Msk = (0xFFFF << CYCLE_CNT_Pos),
1608 };
1609
1610 inline uint32_t BIT_PATTERN(uint32_t _x)
1611 { return (((_x) << BIT_PATTERN_Pos) & BIT_PATTERN_Msk); }
1612 inline uint32_t CYCLE_CNT(uint32_t _x)
1613 { return (((_x) << CYCLE_CNT_Pos) & CYCLE_CNT_Msk); }
1614
1615}
1616namespace PTP_TRIG_ITER_TIME {
1617 enum {
1618 NANOSEC_Pos = 0,
1619 NANOSEC_Msk = (0xFFFFFFFF << NANOSEC_Pos),
1620 };
1621
1622 inline uint32_t NANOSEC(uint32_t _x)
1623 { return (((_x) << NANOSEC_Pos) & NANOSEC_Msk); }
1624
1625}
1626namespace PTP_TRIG_PULSE {
1627 enum {
1628 OUT_WIDTH_Pos = 0,
1629 OUT_WIDTH_Msk = (0xFFFF << OUT_WIDTH_Pos),
1630 PPS_WIDTH_HI_Pos = 16,
1631 PPS_WIDTH_HI_Msk = (0xFF << PPS_WIDTH_HI_Pos),
1632 };
1633
1634 inline uint32_t OUT_WIDTH(uint32_t _x)
1635 { return (((_x) << OUT_WIDTH_Pos) & OUT_WIDTH_Msk); }
1636 inline uint32_t PPS_WIDTH_HI(uint32_t _x)
1637 { return (((_x) << PPS_WIDTH_HI_Pos) & PPS_WIDTH_HI_Msk); }
1638
1639}
1640namespace PTP_TS_STAT_CTRL {
1641 enum {
1642 TS_CASCADE_Pos = 0,
1643 TS_CASCADE_Msk = (0x1 << TS_CASCADE_Pos),
1644 TS_CASCADE_ENABLED = (0x1 << TS_CASCADE_Pos),
1645 TS_CASCADE_DISABLED = (0x0 << TS_CASCADE_Pos),
1646 TS_CASCADE_UPS_Pos = 1,
1647 TS_CASCADE_UPS_Msk = (0x1 << TS_CASCADE_UPS_Pos),
1648 TS_CASCADE_UPS_TS_1 = (0x1 << TS_CASCADE_UPS_Pos),
1649 TS_CASCADE_UPS_TS_0 = (0x0 << TS_CASCADE_UPS_Pos),
1650 TS_CASCADE_TAIL_Pos = 5,
1651 TS_CASCADE_TAIL_Msk = (0x1 << TS_CASCADE_TAIL_Pos),
1652 TS_CASCADE_TAIL_ENABLED = (0x1 << TS_CASCADE_TAIL_Pos),
1653 TS_CASCADE_TAIL_DISABLED = (0x0 << TS_CASCADE_TAIL_Pos),
1654 TS_DETECT_NEG_Pos = 6,
1655 TS_DETECT_NEG_Msk = (0x1 << TS_DETECT_NEG_Pos),
1656 TS_DETECT_NEG_ENABLED = (0x1 << TS_DETECT_NEG_Pos),
1657 TS_DETECT_NEG_DISABLED = (0x0 << TS_DETECT_NEG_Pos),
1658 TS_DETECT_POS_Pos = 7,
1659 TS_DETECT_POS_Msk = (0x1 << TS_DETECT_POS_Pos),
1660 TS_DETECT_POS_ENABLED = (0x1 << TS_DETECT_POS_Pos),
1661 TS_DETECT_POS_DISABLED = (0x0 << TS_DETECT_POS_Pos),
1662 TS_EVT_OVERFLOW_Pos = 16,
1663 TS_EVT_OVERFLOW_Msk = (0x1 << TS_EVT_OVERFLOW_Pos),
1664 TS_EVT_OVERFLOW_ENABLED = (0x1 << TS_EVT_OVERFLOW_Pos),
1665 TS_EVT_OVERFLOW_DISABLED = (0x0 << TS_EVT_OVERFLOW_Pos),
1666 TS_EVT_CNT_Pos = 17,
1667 TS_EVT_CNT_Msk = (0xF << TS_EVT_CNT_Pos),
1668 };
1669
1670}
1671namespace PTP_TS_EVT_0_NANO {
1672 enum {
1673 NANOSEC_Pos = 0,
1674 NANOSEC_Msk = (0x3FFFFFFF << NANOSEC_Pos),
1675 EVT_EDGE_Pos = 30,
1676 EVT_EDGE_Msk = (0x1 << EVT_EDGE_Pos),
1677 EVT_EDGE_POS = (0x1 << EVT_EDGE_Pos),
1678 EVT_EDGE_NEG = (0x1 << EVT_EDGE_Pos),
1679 };
1680
1681}
1682namespace PTP_TS_EVT_0_SEC {
1683 enum {
1684 SEC_Pos = 0,
1685 SEC_Msk = (0xFFFFFFFF << SEC_Pos),
1686 };
1687
1688}
1689namespace PTP_TS_EVT_0_PHASE {
1690 enum {
1691 PHASE_Pos = 0,
1692 PHASE_Msk = (0x7 << PHASE_Pos),
1693 };
1694
1695}
1696namespace PTP_TS_EVT_1_NANO {
1697 enum {
1698 NANOSEC_Pos = 0,
1699 NANOSEC_Msk = (0x3FFFFFFF << NANOSEC_Pos),
1700 EVT_EDGE_Pos = 30,
1701 EVT_EDGE_Msk = (0x1 << EVT_EDGE_Pos),
1702 EVT_EDGE_POS = (0x1 << EVT_EDGE_Pos),
1703 EVT_EDGE_NEG = (0x1 << EVT_EDGE_Pos),
1704 };
1705
1706}
1707namespace PTP_TS_EVT_1_SEC {
1708 enum {
1709 SEC_Pos = 0,
1710 SEC_Msk = (0xFFFFFFFF << SEC_Pos),
1711 };
1712
1713}
1714namespace PTP_TS_EVT_1_PHASE {
1715 enum {
1716 PHASE_Pos = 0,
1717 PHASE_Msk = (0x7 << PHASE_Pos),
1718 };
1719
1720}
1721namespace PTP_TS_EVT_2_NANO {
1722 enum {
1723 NANOSEC_Pos = 0,
1724 NANOSEC_Msk = (0x3FFFFFFF << NANOSEC_Pos),
1725 EVT_EDGE_Pos = 30,
1726 EVT_EDGE_Msk = (0x1 << EVT_EDGE_Pos),
1727 EVT_EDGE_POS = (0x1 << EVT_EDGE_Pos),
1728 EVT_EDGE_NEG = (0x1 << EVT_EDGE_Pos),
1729 };
1730
1731}
1732namespace PTP_TS_EVT_2_SEC {
1733 enum {
1734 SEC_Pos = 0,
1735 SEC_Msk = (0xFFFFFFFF << SEC_Pos),
1736 };
1737
1738}
1739namespace PTP_TS_EVT_2_PHASE {
1740 enum {
1741 PHASE_Pos = 0,
1742 PHASE_Msk = (0x7 << PHASE_Pos),
1743 };
1744
1745}
1746namespace PTP_TS_EVT_3_NANO {
1747 enum {
1748 NANOSEC_Pos = 0,
1749 NANOSEC_Msk = (0x3FFFFFFF << NANOSEC_Pos),
1750 EVT_EDGE_Pos = 30,
1751 EVT_EDGE_Msk = (0x1 << EVT_EDGE_Pos),
1752 EVT_EDGE_POS = (0x1 << EVT_EDGE_Pos),
1753 EVT_EDGE_NEG = (0x1 << EVT_EDGE_Pos),
1754 };
1755
1756}
1757namespace PTP_TS_EVT_3_SEC {
1758 enum {
1759 SEC_Pos = 0,
1760 SEC_Msk = (0xFFFFFFFF << SEC_Pos),
1761 };
1762
1763}
1764namespace PTP_TS_EVT_3_PHASE {
1765 enum {
1766 PHASE_Pos = 0,
1767 PHASE_Msk = (0x7 << PHASE_Pos),
1768 };
1769
1770}
1771namespace PTP_TS_EVT_4_NANO {
1772 enum {
1773 NANOSEC_Pos = 0,
1774 NANOSEC_Msk = (0x3FFFFFFF << NANOSEC_Pos),
1775 EVT_EDGE_Pos = 30,
1776 EVT_EDGE_Msk = (0x1 << EVT_EDGE_Pos),
1777 EVT_EDGE_POS = (0x1 << EVT_EDGE_Pos),
1778 EVT_EDGE_NEG = (0x1 << EVT_EDGE_Pos),
1779 };
1780
1781}
1782namespace PTP_TS_EVT_4_SEC {
1783 enum {
1784 SEC_Pos = 0,
1785 SEC_Msk = (0xFFFFFFFF << SEC_Pos),
1786 };
1787
1788}
1789namespace PTP_TS_EVT_4_PHASE {
1790 enum {
1791 PHASE_Pos = 0,
1792 PHASE_Msk = (0x7 << PHASE_Pos),
1793 };
1794
1795}
1796namespace PTP_TS_EVT_5_NANO {
1797 enum {
1798 NANOSEC_Pos = 0,
1799 NANOSEC_Msk = (0x3FFFFFFF << NANOSEC_Pos),
1800 EVT_EDGE_Pos = 30,
1801 EVT_EDGE_Msk = (0x1 << EVT_EDGE_Pos),
1802 EVT_EDGE_POS = (0x1 << EVT_EDGE_Pos),
1803 EVT_EDGE_NEG = (0x1 << EVT_EDGE_Pos),
1804 };
1805
1806}
1807namespace PTP_TS_EVT_5_SEC {
1808 enum {
1809 SEC_Pos = 0,
1810 SEC_Msk = (0xFFFFFFFF << SEC_Pos),
1811 };
1812
1813}
1814namespace PTP_TS_EVT_5_PHASE {
1815 enum {
1816 PHASE_Pos = 0,
1817 PHASE_Msk = (0x7 << PHASE_Pos),
1818 };
1819
1820}
1821namespace PTP_TS_EVT_6_NANO {
1822 enum {
1823 NANOSEC_Pos = 0,
1824 NANOSEC_Msk = (0x3FFFFFFF << NANOSEC_Pos),
1825 EVT_EDGE_Pos = 30,
1826 EVT_EDGE_Msk = (0x1 << EVT_EDGE_Pos),
1827 EVT_EDGE_POS = (0x1 << EVT_EDGE_Pos),
1828 EVT_EDGE_NEG = (0x1 << EVT_EDGE_Pos),
1829 };
1830
1831}
1832namespace PTP_TS_EVT_6_SEC {
1833 enum {
1834 SEC_Pos = 0,
1835 SEC_Msk = (0xFFFFFFFF << SEC_Pos),
1836 };
1837
1838}
1839namespace PTP_TS_EVT_6_PHASE {
1840 enum {
1841 PHASE_Pos = 0,
1842 PHASE_Msk = (0x7 << PHASE_Pos),
1843 };
1844
1845}
1846namespace PTP_TS_EVT_7_NANO {
1847 enum {
1848 NANOSEC_Pos = 0,
1849 NANOSEC_Msk = (0x3FFFFFFF << NANOSEC_Pos),
1850 EVT_EDGE_Pos = 30,
1851 EVT_EDGE_Msk = (0x1 << EVT_EDGE_Pos),
1852 EVT_EDGE_POS = (0x1 << EVT_EDGE_Pos),
1853 EVT_EDGE_NEG = (0x1 << EVT_EDGE_Pos),
1854 };
1855
1856}
1857namespace PTP_TS_EVT_7_SEC {
1858 enum {
1859 SEC_Pos = 0,
1860 SEC_Msk = (0xFFFFFFFF << SEC_Pos),
1861 };
1862
1863}
1864namespace PTP_TS_EVT_7_PHASE {
1865 enum {
1866 PHASE_Pos = 0,
1867 PHASE_Msk = (0x7 << PHASE_Pos),
1868 };
1869
1870}
1871
1872namespace PORT_DEFAULT_VID {
1873 enum {
1874 VID_Pos = 0,
1875 VID_Msk = (0xFFF << VID_Pos),
1876 DEI_Pos = 12,
1877 DEI_Msk = (0x1 << DEI_Pos),
1878 PCP_Pos = 13,
1879 PCP_Msk = (0x7 << PCP_Pos),
1880 };
1881
1882 inline uint32_t VID(uint32_t _x)
1883 { return (((_x) << VID_Pos) & VID_Msk); }
1884 inline uint32_t DEI(uint32_t _x)
1885 { return (((_x) << DEI_Pos) & DEI_Msk); }
1886 inline uint32_t PCP(uint32_t _x)
1887 { return (((_x) << PCP_Pos) & PCP_Msk); }
1888
1889}
1890namespace PORT_CUSTOM_VID {
1891 enum {
1892 VID_Pos = 0,
1893 VID_Msk = (0xFFF << VID_Pos),
1894 DEI_Pos = 12,
1895 DEI_Msk = (0x1 << DEI_Pos),
1896 PCP_Pos = 13,
1897 PCP_Msk = (0x7 << PCP_Pos),
1898 };
1899
1900 inline uint32_t VID(uint32_t _x)
1901 { return (((_x) << VID_Pos) & VID_Msk); }
1902 inline uint32_t DEI(uint32_t _x)
1903 { return (((_x) << DEI_Pos) & DEI_Msk); }
1904 inline uint32_t PCP(uint32_t _x)
1905 { return (((_x) << PCP_Pos) & PCP_Msk); }
1906
1907}
1908namespace PORT_AVB_SR_1_VID {
1909 enum {
1910 VID_Pos = 0,
1911 VID_Msk = (0xFFF << VID_Pos),
1912 CFI_Pos = 12,
1913 CFI_Msk = (0x1 << CFI_Pos),
1914 PRIO_Pos = 13,
1915 PRIO_Msk = (0x7 << PRIO_Pos),
1916 };
1917
1918 inline uint32_t VID(uint32_t _x)
1919 { return (((_x) << VID_Pos) & VID_Msk); }
1920 inline uint32_t CFI(uint32_t _x)
1921 { return (((_x) << CFI_Pos) & CFI_Msk); }
1922 inline uint32_t PRIO(uint32_t _x)
1923 { return (((_x) << PRIO_Pos) & PRIO_Msk); }
1924
1925}
1926namespace PORT_AVB_SR_2_VID {
1927 enum {
1928 VID_Pos = 0,
1929 VID_Msk = (0xFFF << VID_Pos),
1930 CFI_Pos = 12,
1931 CFI_Msk = (0x1 << CFI_Pos),
1932 PRIO_Pos = 13,
1933 PRIO_Msk = (0x7 << PRIO_Pos),
1934 };
1935
1936 inline uint32_t VID(uint32_t _x)
1937 { return (((_x) << VID_Pos) & VID_Msk); }
1938 inline uint32_t CFI(uint32_t _x)
1939 { return (((_x) << CFI_Pos) & CFI_Msk); }
1940 inline uint32_t PRIO(uint32_t _x)
1941 { return (((_x) << PRIO_Pos) & PRIO_Msk); }
1942
1943}
1944namespace PORT_WOL_STATUS {
1945 enum {
1946 ENERGY_DETECTED_Pos = 0,
1947 ENERGY_DETECTED_Msk = (0x1 << ENERGY_DETECTED_Pos),
1948 ENERGY_DETECTED = (0x1 << ENERGY_DETECTED_Pos),
1949 LINK_DETECTED_Pos = 1,
1950 LINK_DETECTED_Msk = (0x1 << LINK_DETECTED_Pos),
1951 LINK_DETECTED = (0x1 << LINK_DETECTED_Pos),
1952 MAGIC_PKT_DETECTED_Pos = 2,
1953 MAGIC_PKT_DETECTED_Msk = (0x1 << MAGIC_PKT_DETECTED_Pos),
1954 MAGIC_PKT_DETECTED = (0x1 << MAGIC_PKT_DETECTED_Pos),
1955 };
1956
1957}
1958namespace PORT_WOL_MASK {
1959 enum {
1960 ENERGY_Pos = 0,
1961 ENERGY_Msk = (0x1 << ENERGY_Pos),
1962 ENERGY_ENABLED = (0x1 << ENERGY_Pos),
1963 ENERGY_DISABLED = (0x0 << ENERGY_Pos),
1964 LINK_Pos = 1,
1965 LINK_Msk = (0x1 << LINK_Pos),
1966 LINK_ENABLED = (0x1 << LINK_Pos),
1967 LINK_DISABLED = (0x0 << LINK_Pos),
1968 MAGIC_PKT_Pos = 2,
1969 MAGIC_PKT_Msk = (0x1 << MAGIC_PKT_Pos),
1970 MAGIC_PKT_ENABLED = (0x1 << MAGIC_PKT_Pos),
1971 MAGIC_PKT_DISABLED = (0x0 << MAGIC_PKT_Pos),
1972 };
1973
1974}
1975namespace PORT_INT_STATUS {
1976 enum {
1977 ACL_INT_Pos = 0,
1978 ACL_INT_Msk = (0x1 << ACL_INT_Pos),
1979 ACL_INT = (0x1 << ACL_INT_Pos),
1980 PHY_INT_Pos = 1,
1981 PHY_INT_Msk = (0x1 << PHY_INT_Pos),
1982 PHY_INT = (0x1 << PHY_INT_Pos),
1983 PTP_INT_Pos = 2,
1984 PTP_INT_Msk = (0x1 << PTP_INT_Pos),
1985 PTP_INT = (0x1 << PTP_INT_Pos),
1986 SGMII_INT_Pos = 2,
1987 SGMII_INT_Msk = (0x1 << SGMII_INT_Pos),
1988 SGMII_INT = (0x1 << SGMII_INT_Pos),
1989 };
1990
1991}
1992namespace PORT_INT_MASK {
1993 enum {
1994 ACL_INT_Pos = 0,
1995 ACL_INT_Msk = (0x1 << ACL_INT_Pos),
1996 ACL_INT_ENABLED = (0x0 << ACL_INT_Pos),
1997 ACL_INT_DISABLED = (0x1 << ACL_INT_Pos),
1998 PHY_INT_Pos = 1,
1999 PHY_INT_Msk = (0x1 << PHY_INT_Pos),
2000 PHY_INT_ENABLED = (0x0 << PHY_INT_Pos),
2001 PHY_INT_DISABLED = (0x1 << PHY_INT_Pos),
2002 PTP_INT_Pos = 2,
2003 PTP_INT_Msk = (0x1 << PTP_INT_Pos),
2004 PTP_INT_ENABLED = (0x0 << PTP_INT_Pos),
2005 PTP_INT_DISABLED = (0x1 << PTP_INT_Pos),
2006 SGMII_INT_Pos = 2,
2007 SGMII_INT_Msk = (0x1 << SGMII_INT_Pos),
2008 SGMII_INT_ENABLED = (0x0 << SGMII_INT_Pos),
2009 SGMII_INT_DISABLED = (0x1 << SGMII_INT_Pos),
2010 };
2011
2012}
2013namespace PORT_CTRL {
2014 enum {
2015 SRP_ENABLE_Pos = 16,
2016 SRP_ENABLE_Msk = (0x3 << SRP_ENABLE_Pos),
2017 SRP_ENABLE_NONE = (0x0 << SRP_ENABLE_Pos),
2018 SRP_ENABLE_SRP_1 = (0x1 << SRP_ENABLE_Pos),
2019 SRP_ENABLE_SRP_2 = (0x2 << SRP_ENABLE_Pos),
2020 QUEUE_SPLIT_Pos = 24,
2021 QUEUE_SPLIT_Msk = (0x3 << QUEUE_SPLIT_Pos),
2022 QUEUE_SPLIT_SINGLE = (0x0 << QUEUE_SPLIT_Pos),
2023 QUEUE_SPLIT_DUAL = (0x1 << QUEUE_SPLIT_Pos),
2024 QUEUE_SPLIT_QUAD = (0x2 << QUEUE_SPLIT_Pos),
2025 TAIL_TAG_Pos = 26,
2026 TAIL_TAG_Msk = (0x1 << TAIL_TAG_Pos),
2027 TAIL_TAG_DISABLED = (0x0 << TAIL_TAG_Pos),
2028 TAIL_TAG_ENABLED = (0x1 << TAIL_TAG_Pos),
2029 REMOTE_LOOPBACK_Pos = 30,
2030 REMOTE_LOOPBACK_Msk = (0x1 << REMOTE_LOOPBACK_Pos),
2031 REMOTE_LOOPBACK_DISABLED = (0x0 << REMOTE_LOOPBACK_Pos),
2032 REMOTE_LOOPBACK_ENABLED = (0x1 << REMOTE_LOOPBACK_Pos),
2033 LOCAL_LOOPBACK_Pos = 31,
2034 LOCAL_LOOPBACK_Msk = (0x1 << LOCAL_LOOPBACK_Pos),
2035 LOCAL_LOOPBACK_DISABLED = (0x0 << LOCAL_LOOPBACK_Pos),
2036 LOCAL_LOOPBACK_ENABLED = (0x1 << LOCAL_LOOPBACK_Pos),
2037 };
2038
2039}
2040namespace PORT_STATUS {
2041 enum {
2042 RX_FLOW_CTRL_Pos = 24,
2043 RX_FLOW_CTRL_Msk = (0x1 << RX_FLOW_CTRL_Pos),
2044 RX_FLOW_CTRL_DISABLED = (0x0 << RX_FLOW_CTRL_Pos),
2045 RX_FLOW_CTRL_ENABLED = (0x1 << RX_FLOW_CTRL_Pos),
2046 TX_FLOW_CTRL_Pos = 25,
2047 TX_FLOW_CTRL_Msk = (0x3 << TX_FLOW_CTRL_Pos),
2048 TX_FLOW_CTRL_DISABLED = (0x0 << TX_FLOW_CTRL_Pos),
2049 TX_FLOW_CTRL_ENABLED = (0x1 << TX_FLOW_CTRL_Pos),
2050 DUPLEX_Pos = 26,
2051 DUPLEX_Msk = (0x3 << DUPLEX_Pos),
2052 DUPLEX_HALF = (0x0 << DUPLEX_Pos),
2053 DUPLEX_FULL = (0x1 << DUPLEX_Pos),
2054 SPEED_Pos = 27,
2055 SPEED_Msk = (0x3 << SPEED_Pos),
2056 SPEED_10M = (0x0 << SPEED_Pos),
2057 SPEED_100M = (0x1 << SPEED_Pos),
2058 SPEED_1000M = (0x2 << SPEED_Pos),
2059 };
2060
2061}
2062
2063namespace PHY_BASIC_CTL {
2064 enum {
2065 PHY_SPEED_100M_Pos = 6,
2066 PHY_SPEED_100M_Msk = (0x1 << PHY_SPEED_100M_Pos),
2067 PHY_SPEED_100M_10M = (0x0 << PHY_SPEED_100M_Pos),
2068 PHY_SPEED_100M_100M = (0x1 << PHY_SPEED_100M_Pos),
2069 PHY_SPEED_100M_1000M = (0x0 << PHY_SPEED_100M_Pos),
2070 COL_TEST_Pos = 7,
2071 COL_TEST_Msk = (0x1 << COL_TEST_Pos),
2072 COL_TEST_DISABLED = (0x0 << COL_TEST_Pos),
2073 COL_TEST_ENABLED = (0x1 << COL_TEST_Pos),
2074 DUPLEX_Pos = 8,
2075 DUPLEX_Msk = (0x1 << DUPLEX_Pos),
2076 DUPLEX_HALF = (0x0 << DUPLEX_Pos),
2077 DUPLEX_FULL = (0x1 << DUPLEX_Pos),
2078 RESTART_AUTONEG_Pos = 9,
2079 RESTART_AUTONEG_Msk = (0x1 << RESTART_AUTONEG_Pos),
2080 RESTART_AUTONEG = (0x1 << RESTART_AUTONEG_Pos),
2081 ISOLATE_Pos = 10,
2082 ISOLATE_Msk = (0x1 << ISOLATE_Pos),
2083 ISOLATE_DISABLED = (0x0 << ISOLATE_Pos),
2084 ISOLATE_ENABLED = (0x1 << ISOLATE_Pos),
2085 POWER_DOWN_Pos = 11,
2086 POWER_DOWN_Msk = (0x1 << POWER_DOWN_Pos),
2087 POWER_DOWN_DISABLED = (0x0 << POWER_DOWN_Pos),
2088 POWER_DOWN_ENABLED = (0x1 << POWER_DOWN_Pos),
2089 AUTONEG_Pos = 12,
2090 AUTONEG_Msk = (0x1 << AUTONEG_Pos),
2091 AUTONEG_DISABLED = (0x0 << AUTONEG_Pos),
2092 AUTONEG_ENABLED = (0x1 << AUTONEG_Pos),
2093 PHY_SPEED_1000M_Pos = 13,
2094 PHY_SPEED_1000M_Msk = (0x1 << PHY_SPEED_1000M_Pos),
2095 PHY_SPEED_1000M_10M = (0x0 << PHY_SPEED_1000M_Pos),
2096 PHY_SPEED_1000M_100M = (0x0 << PHY_SPEED_1000M_Pos),
2097 PHY_SPEED_1000M_1000M = (0x1 << PHY_SPEED_1000M_Pos),
2098 LOCAL_LOOPBACK_Pos = 14,
2099 LOCAL_LOOPBACK_Msk = (0x1 << LOCAL_LOOPBACK_Pos),
2100 LOCAL_LOOPBACK_DISABLED = (0x0 << LOCAL_LOOPBACK_Pos),
2101 LOCAL_LOOPBACK_ENABLED = (0x1 << LOCAL_LOOPBACK_Pos),
2102 PHY_RESET_Pos = 15,
2103 PHY_RESET_Msk = (0x1 << PHY_RESET_Pos),
2104 PHY_RESET = (0x1 << PHY_RESET_Pos),
2105 };
2106
2107}
2108namespace PHY_BASIC_ST {
2109 enum {
2110 CAPABILITY_Pos = 0,
2111 CAPABILITY_Msk = (0x1 << CAPABILITY_Pos),
2112 CAPABILITY_BASIC = (0x0 << CAPABILITY_Pos),
2113 CAPABILITY_EXTENDED = (0x1 << CAPABILITY_Pos),
2114 JABBER_Pos = 1,
2115 JABBER_Msk = (0x1 << JABBER_Pos),
2116 JABBER_NONE = (0x0 << JABBER_Pos),
2117 JABBER_DETECTED = (0x1 << JABBER_Pos),
2118 LINK_STATUS_Pos = 2,
2119 LINK_STATUS_Msk = (0x1 << LINK_STATUS_Pos),
2120 LINK_STATUS_DOWN = (0x0 << LINK_STATUS_Pos),
2121 LINK_STATUS_UP = (0x1 << LINK_STATUS_Pos),
2122 AUTONEG_CAPABLE_Pos = 3,
2123 AUTONEG_CAPABLE_Msk = (0x1 << AUTONEG_CAPABLE_Pos),
2124 AUTONEG_CAPABLE_NOT_CAPABLE = (0x0 << AUTONEG_CAPABLE_Pos),
2125 AUTONEG_CAPABLE_CAPABLE = (0x1 << AUTONEG_CAPABLE_Pos),
2126 REMOTE_FAULT_Pos = 4,
2127 REMOTE_FAULT_Msk = (0x1 << REMOTE_FAULT_Pos),
2128 REMOTE_FAULT_NONE = (0x0 << REMOTE_FAULT_Pos),
2129 REMOTE_FAULT_DETECTED = (0x1 << REMOTE_FAULT_Pos),
2130 AUTONEG_STATUS_Pos = 5,
2131 AUTONEG_STATUS_Msk = (0x1 << AUTONEG_STATUS_Pos),
2132 AUTONEG_STATUS_NOT_COMPLETE = (0x0 << AUTONEG_STATUS_Pos),
2133 AUTONEG_STATUS_COMPLETE = (0x1 << AUTONEG_STATUS_Pos),
2134 MF_PREAMBLE_SUPRESS_Pos = 6,
2135 MF_PREAMBLE_SUPRESS_Msk = (0x1 << MF_PREAMBLE_SUPRESS_Pos),
2136 MF_PREAMBLE_SUPRESS_NOT_SUPPORTED = (0x0 << MF_PREAMBLE_SUPRESS_Pos),
2137 MF_PREAMBLE_SUPRESS_SUPPORTED = (0x1 << MF_PREAMBLE_SUPRESS_Pos),
2138 EXT_STATUS_Pos = 8,
2139 EXT_STATUS_Msk = (0x1 << EXT_STATUS_Pos),
2140 EXT_STATUS_NOT_PRESENT = (0x0 << EXT_STATUS_Pos),
2141 EXT_STATUS_PRESENT = (0x1 << EXT_STATUS_Pos),
2142 _100BT_HD_Pos = 11,
2143 _100BT_HD_Msk = (0x1 << _100BT_HD_Pos),
2144 _100BT_HD_NOT_SUPPORTED = (0x0 << _100BT_HD_Pos),
2145 _100BT_HD_SUPPORTED = (0x1 << _100BT_HD_Pos),
2146 _10BT_FD_Pos = 12,
2147 _10BT_FD_Msk = (0x1 << _10BT_FD_Pos),
2148 _10BT_FD_NOT_SUPPORTED = (0x0 << _10BT_FD_Pos),
2149 _10BT_FD_SUPPORTED = (0x1 << _10BT_FD_Pos),
2150 _100BTX_HD_Pos = 13,
2151 _100BTX_HD_Msk = (0x1 << _100BTX_HD_Pos),
2152 _100BTX_HD_NOT_SUPPORTED = (0x0 << _100BTX_HD_Pos),
2153 _100BTX_HD_SUPPORTED = (0x1 << _100BTX_HD_Pos),
2154 _100BTX_FD_Pos = 14,
2155 _100BTX_FD_Msk = (0x1 << _100BTX_FD_Pos),
2156 _100BTX_FD_NOT_SUPPORTED = (0x0 << _100BTX_FD_Pos),
2157 _100BTX_FD_SUPPORTED = (0x1 << _100BTX_FD_Pos),
2158 _100BT4_Pos = 15,
2159 _100BT4_Msk = (0x1 << _100BT4_Pos),
2160 _100BT4_NOT_SUPPORTED = (0x0 << _100BT4_Pos),
2161 _100BT4_SUPPORTED = (0x1 << _100BT4_Pos),
2162 };
2163
2164}
2165namespace PHY_A_NEG_ADVERT {
2166 enum {
2167 SELECTOR_Pos = 0,
2168 SELECTOR_Msk = (0x1F << SELECTOR_Pos),
2169 _10BT_HD_Pos = 5,
2170 _10BT_HD_Msk = (0x1 << _10BT_HD_Pos),
2171 _10BT_HD_NOT_ALLOWED = (0x0 << _10BT_HD_Pos),
2172 _10BT_HD_ALLOWED = (0x1 << _10BT_HD_Pos),
2173 _10BT_FD_Pos = 6,
2174 _10BT_FD_Msk = (0x1 << _10BT_FD_Pos),
2175 _10BT_FD_NOT_ALLOWED = (0x0 << _10BT_FD_Pos),
2176 _10BT_FD_ALLOWED = (0x1 << _10BT_FD_Pos),
2177 _100BTX_HD_Pos = 7,
2178 _100BTX_HD_Msk = (0x1 << _100BTX_HD_Pos),
2179 _100BTX_HD_NOT_ALLOWED = (0x0 << _100BTX_HD_Pos),
2180 _100BTX_HD_ALLOWED = (0x1 << _100BTX_HD_Pos),
2181 _100BTX_FD_Pos = 8,
2182 _100BTX_FD_Msk = (0x1 << _100BTX_FD_Pos),
2183 _100BTX_FD_NOT_ALLOWED = (0x0 << _100BTX_FD_Pos),
2184 _100BTX_FD_ALLOWED = (0x1 << _100BTX_FD_Pos),
2185 _100BT4_Pos = 9,
2186 _100BT4_Msk = (0x1 << _100BT4_Pos),
2187 _100BT4_NOT_ALLOWED = (0x0 << _100BT4_Pos),
2188 _100BT4_ALLOWED = (0x1 << _100BT4_Pos),
2189 SYM_PAUSE_Pos = 10,
2190 SYM_PAUSE_Msk = (0x1 << SYM_PAUSE_Pos),
2191 SYM_PAUSE_NOT_ALLOWED = (0x0 << SYM_PAUSE_Pos),
2192 SYM_PAUSE_ALLOWED = (0x1 << SYM_PAUSE_Pos),
2193 ASYM_PAUSE_Pos = 11,
2194 ASYM_PAUSE_Msk = (0x1 << ASYM_PAUSE_Pos),
2195 ASYM_PAUSE_NOT_ALLOWED = (0x0 << ASYM_PAUSE_Pos),
2196 ASYM_PAUSE_ALLOWED = (0x1 << ASYM_PAUSE_Pos),
2197 REMOTE_FAULT_Pos = 13,
2198 REMOTE_FAULT_Msk = (0x1 << REMOTE_FAULT_Pos),
2199 REMOTE_FAULT_NOT_CAPABLE = (0x0 << REMOTE_FAULT_Pos),
2200 REMOTE_FAULT_CAPABLE = (0x1 << REMOTE_FAULT_Pos),
2201 NEXT_PAGE_Pos = 15,
2202 NEXT_PAGE_Msk = (0x1 << NEXT_PAGE_Pos),
2203 NEXT_PAGE_NOT_CAPABLE = (0x0 << NEXT_PAGE_Pos),
2204 NEXT_PAGE_CAPABLE = (0x1 << NEXT_PAGE_Pos),
2205 };
2206
2207 inline uint32_t SELECTOR(uint32_t _x)
2208 { return (((_x) << SELECTOR_Pos) & SELECTOR_Msk); }
2209
2210}
2211namespace PHY_A_NEG_LPA {
2212 enum {
2213 SELECTOR_Pos = 0,
2214 SELECTOR_Msk = (0x1F << SELECTOR_Pos),
2215 _10BT_HD_Pos = 5,
2216 _10BT_HD_Msk = (0x1 << _10BT_HD_Pos),
2217 _10BT_HD_NOT_ALLOWED = (0x0 << _10BT_HD_Pos),
2218 _10BT_HD_ALLOWED = (0x1 << _10BT_HD_Pos),
2219 _10BT_FD_Pos = 6,
2220 _10BT_FD_Msk = (0x1 << _10BT_FD_Pos),
2221 _10BT_FD_NOT_ALLOWED = (0x0 << _10BT_FD_Pos),
2222 _10BT_FD_ALLOWED = (0x1 << _10BT_FD_Pos),
2223 _100BTX_HD_Pos = 7,
2224 _100BTX_HD_Msk = (0x1 << _100BTX_HD_Pos),
2225 _100BTX_HD_NOT_ALLOWED = (0x0 << _100BTX_HD_Pos),
2226 _100BTX_HD_ALLOWED = (0x1 << _100BTX_HD_Pos),
2227 _100BTX_FD_Pos = 8,
2228 _100BTX_FD_Msk = (0x1 << _100BTX_FD_Pos),
2229 _100BTX_FD_NOT_ALLOWED = (0x0 << _100BTX_FD_Pos),
2230 _100BTX_FD_ALLOWED = (0x1 << _100BTX_FD_Pos),
2231 _100BT4_Pos = 9,
2232 _100BT4_Msk = (0x1 << _100BT4_Pos),
2233 _100BT4_NOT_ALLOWED = (0x0 << _100BT4_Pos),
2234 _100BT4_ALLOWED = (0x1 << _100BT4_Pos),
2235 SYM_PAUSE_Pos = 10,
2236 SYM_PAUSE_Msk = (0x1 << SYM_PAUSE_Pos),
2237 SYM_PAUSE_NOT_ALLOWED = (0x0 << SYM_PAUSE_Pos),
2238 SYM_PAUSE_ALLOWED = (0x1 << SYM_PAUSE_Pos),
2239 ASYM_PAUSE_Pos = 11,
2240 ASYM_PAUSE_Msk = (0x1 << ASYM_PAUSE_Pos),
2241 ASYM_PAUSE_NOT_ALLOWED = (0x0 << ASYM_PAUSE_Pos),
2242 ASYM_PAUSE_ALLOWED = (0x1 << ASYM_PAUSE_Pos),
2243 REMOTE_FAULT_Pos = 13,
2244 REMOTE_FAULT_Msk = (0x1 << REMOTE_FAULT_Pos),
2245 REMOTE_FAULT_NONE = (0x0 << REMOTE_FAULT_Pos),
2246 REMOTE_FAULT_DETECTED = (0x1 << REMOTE_FAULT_Pos),
2247 REMOTE_ACKNOWLEDGE_Pos = 14,
2248 REMOTE_ACKNOWLEDGE_Msk = (0x1 << REMOTE_FAULT_Pos),
2249 REMOTE_ACKNOWLEDGE_NONE = (0x0 << REMOTE_FAULT_Pos),
2250 REMOTE_ACKNOWLEDGE_ACKED = (0x1 << REMOTE_FAULT_Pos),
2251 NEXT_PAGE_Pos = 15,
2252 NEXT_PAGE_Msk = (0x1F << NEXT_PAGE_Pos),
2253 NEXT_PAGE_NOT_CAPABLE = (0x0 << NEXT_PAGE_Pos),
2254 NEXT_PAGE_CAPABLE = (0x1 << NEXT_PAGE_Pos),
2255 };
2256
2257 inline uint32_t SELECTOR(uint32_t _x)
2258 { return (((_x) << SELECTOR_Pos) & SELECTOR_Msk); }
2259
2260}
2261namespace PHY_A_NEG_EXP {
2262 enum {
2263 LP_A_NEG_Pos = 0,
2264 LP_A_NEG_Msk = (0x1 << LP_A_NEG_Pos),
2265 LP_A_NEG_NOT_CAPABLE = (0x0 << LP_A_NEG_Pos) & LP_A_NEG_Msk,
2266 LP_A_NEG_CAPABLE = (0x1 << LP_A_NEG_Pos) & LP_A_NEG_Msk,
2267 PAGE_RX_Pos = 1,
2268 PAGE_RX_Msk = (0x1 << PAGE_RX_Pos),
2269 PAGE_RX_WAITING = (0x0 << PAGE_RX_Pos) & PAGE_RX_Msk,
2270 PAGE_RX_RXED = (0x1 << PAGE_RX_Pos) & PAGE_RX_Msk,
2271 LOCAL_NEXT_PAGE_Pos = 2,
2272 LOCAL_NEXT_PAGE_Msk = (0x1 << LOCAL_NEXT_PAGE_Pos),
2273 LOCAL_NEXT_PAGE_NOT_CAPABLE = (0x0 << LOCAL_NEXT_PAGE_Pos) & LOCAL_NEXT_PAGE_Msk,
2274 LOCAL_NEXT_PAGE_CAPABLE = (0x1 << LOCAL_NEXT_PAGE_Pos) & LOCAL_NEXT_PAGE_Msk,
2275 LPA_NEXT_PAGE_Pos = 3,
2276 LPA_NEXT_PAGE_Msk = (0x1 << LPA_NEXT_PAGE_Pos),
2277 LPA_NEXT_PAGE_NOT_CAPABLE = (0x0 << LPA_NEXT_PAGE_Pos) & LPA_NEXT_PAGE_Msk,
2278 LPA_NEXT_PAGE_CAPABLE = (0x1 << LPA_NEXT_PAGE_Pos) & LPA_NEXT_PAGE_Msk,
2279 PARALLEL_FAULT_Pos = 0,
2280 PARALLEL_FAULT_Msk = (0x1 << PARALLEL_FAULT_Pos),
2281 PARALLEL_FAULT_NONE = (0x0 << PARALLEL_FAULT_Pos) & PARALLEL_FAULT_Msk,
2282 PARALLEL_FAULT_DETECTED = (0x1 << PARALLEL_FAULT_Pos) & PARALLEL_FAULT_Msk,
2283 };
2284
2285}
2286namespace PHY_A_NEG_NEXT_PG {
2287 enum {
2288 MESSAGE_Pos = 0,
2289 MESSAGE_Msk = (0x7FF << MESSAGE_Pos),
2290 TOGGLE_Pos = 11,
2291 TOGGLE_Msk = (0x1 << TOGGLE_Pos),
2292 ACKNOWLEDGE2_Pos = 12,
2293 ACKNOWLEDGE2_Msk = (0x1 << ACKNOWLEDGE2_Pos),
2294 ACKNOWLEDGE2_NACK = (0x0 << ACKNOWLEDGE2_Pos),
2295 ACKNOWLEDGE2_ACK = (0x1 << ACKNOWLEDGE2_Pos),
2296 PAGE_TYPE_Pos = 13,
2297 PAGE_TYPE_Msk = (0x1 << PAGE_TYPE_Pos),
2298 PAGE_TYPE_UNFORMATTED = (0x0 << PAGE_TYPE_Pos),
2299 PAGE_TYPE_MESSAGE = (0x1 << PAGE_TYPE_Pos),
2300 NEXT_PAGE_Pos = 15,
2301 NEXT_PAGE_Msk = (0x1 << NEXT_PAGE_Pos),
2302 NEXT_PAGE_LAST = (0x0 << NEXT_PAGE_Pos),
2303 NEXT_PAGE_MORE_FOLLOW = (0x1 << NEXT_PAGE_Pos),
2304 };
2305
2306 inline uint32_t MESSAGE(uint32_t _x)
2307 { return (((_x) << MESSAGE_Pos) & MESSAGE_Msk); }
2308 inline uint32_t TOGGLE(uint32_t _x)
2309 { return (((_x) << TOGGLE_Pos) & TOGGLE_Msk); }
2310
2311}
2312namespace PHY_LP_NEXT_PG_ABIL {
2313 enum {
2314 MESSAGE_Pos = 0,
2315 MESSAGE_Msk = (0x7FF << MESSAGE_Pos),
2316 TOGGLE_Pos = 11,
2317 TOGGLE_Msk = (0x1 << TOGGLE_Pos),
2318 ACKNOWLEDGE2_Pos = 12,
2319 ACKNOWLEDGE2_Msk = (0x1 << ACKNOWLEDGE2_Pos),
2320 ACKNOWLEDGE2_NACK = (0x0 << ACKNOWLEDGE2_Pos),
2321 ACKNOWLEDGE2_ACK = (0x1 << ACKNOWLEDGE2_Pos),
2322 PAGE_TYPE_Pos = 13,
2323 PAGE_TYPE_Msk = (0x1 << PAGE_TYPE_Pos),
2324 PAGE_TYPE_UNFORMATTED = (0x0 << PAGE_TYPE_Pos),
2325 PAGE_TYPE_MESSAGE = (0x1 << PAGE_TYPE_Pos),
2326 ACKNOWLEDGE_Pos = 14,
2327 ACKNOWLEDGE_Msk = (0x1 << ACKNOWLEDGE_Pos),
2328 ACKNOWLEDGE_NACK = (0x0 << ACKNOWLEDGE_Pos),
2329 ACKNOWLEDGE_ACK = (0x1 << ACKNOWLEDGE_Pos),
2330 NEXT_PAGE_Pos = 15,
2331 NEXT_PAGE_Msk = (0x1 << NEXT_PAGE_Pos),
2332 NEXT_PAGE_LAST = (0x0 << NEXT_PAGE_Pos),
2333 NEXT_PAGE_MORE_FOLLOW = (0x1 << NEXT_PAGE_Pos),
2334 };
2335
2336 inline uint32_t MESSAGE(uint32_t _x)
2337 { return (((_x) << MESSAGE_Pos) & MESSAGE_Msk); }
2338 inline uint32_t TOGGLE(uint32_t _x)
2339 { return (((_x) << TOGGLE_Pos) & TOGGLE_Msk); }
2340
2341}
2342namespace PHY_GBCR {
2343 enum {
2344 _1000BT_HD_Pos = 8,
2345 _1000BT_HD_Msk = (0x1 << _1000BT_HD_Pos),
2346 _1000BT_HD_NOT_CAPABLE = (0x0 << _1000BT_HD_Pos),
2347 _1000BT_HD_CAPABLE = (0x1 << _1000BT_HD_Pos),
2348 _1000BT_FD_Pos = 9,
2349 _1000BT_FD_Msk = (0x1 << _1000BT_FD_Pos),
2350 _1000BT_FD_NOT_CAPABLE = (0x0 << _1000BT_FD_Pos),
2351 _1000BT_FD_CAPABLE = (0x1 << _1000BT_FD_Pos),
2352 DEVICE_TYPE_Pos = 10,
2353 DEVICE_TYPE_Msk = (0x1 << DEVICE_TYPE_Pos),
2354 DEVICE_TYPE_SINGLE_PORT = (0x0 << DEVICE_TYPE_Pos),
2355 DEVICE_TYPE_MULTI_PORT = (0x1 << DEVICE_TYPE_Pos),
2356 MANUAL_ROLE_CFG_Pos = 11,
2357 MANUAL_ROLE_CFG_Msk = (0x1 << MANUAL_ROLE_CFG_Pos),
2358 MANUAL_ROLE_CFG_SLAVE = (0x0 << MANUAL_ROLE_CFG_Pos),
2359 MANUAL_ROLE_CFG_MASTER = (0x1 << MANUAL_ROLE_CFG_Pos),
2360 MANUAL_ROLE_Pos = 12,
2361 MANUAL_ROLE_Msk = (0x1 << MANUAL_ROLE_Pos),
2362 MANUAL_ROLE_DISABLED = (0x0 << MANUAL_ROLE_Pos),
2363 MANUAL_ROLE_ENABLED = (0x1 << MANUAL_ROLE_Pos),
2364 TX_TEST_MODE_Pos = 13,
2365 TX_TEST_MODE_Msk = (0x7 << TX_TEST_MODE_Pos),
2366 TX_TEST_MODE_NORMAL_OPS = (0x0 << TX_TEST_MODE_Pos),
2367 TX_TEST_MODE_MODE_1_WAVE = (0x1 << TX_TEST_MODE_Pos),
2368 TX_TEST_MODE_MODE_2_JITTER_MASTER = (0x2 << TX_TEST_MODE_Pos),
2369 TX_TEST_MODE_MODE_3_JITTER_SLAVE = (0x3 << TX_TEST_MODE_Pos),
2370 TX_TEST_MODE_MODE_4_DISTORTION = (0x4 << TX_TEST_MODE_Pos),
2371 };
2372
2373}
2374namespace PHY_GBSR {
2375 enum {
2376 IDLE_ERR_CNT_Pos = 0,
2377 IDLE_ERR_CNT_Msk = (0xFF << IDLE_ERR_CNT_Pos),
2378 LP_1000BT_HD_Pos = 10,
2379 LP_1000BT_HD_Msk = (0x1 << LP_1000BT_HD_Pos),
2380 LP_1000BT_HD_NOT_CAPABLE = (0x0 << LP_1000BT_HD_Pos),
2381 LP_1000BT_HD_CAPABLE = (0x1 << LP_1000BT_HD_Pos),
2382 LP_1000BT_FD_Pos = 11,
2383 LP_1000BT_FD_Msk = (0x1 << LP_1000BT_FD_Pos),
2384 LP_1000BT_FD_NOT_CAPABLE = (0x0 << LP_1000BT_FD_Pos),
2385 LP_1000BT_FD_CAPABLE = (0x1 << LP_1000BT_FD_Pos),
2386 REMOTE_RX_STAT_Pos = 12,
2387 REMOTE_RX_STAT_Msk = (0x1 << REMOTE_RX_STAT_Pos),
2388 REMOTE_RX_STAT_NOT_OK = (0x0 << REMOTE_RX_STAT_Pos),
2389 REMOTE_RX_STAT_OK = (0x1 << REMOTE_RX_STAT_Pos),
2390 LOCAL_RX_STAT_Pos = 13,
2391 LOCAL_RX_STAT_Msk = (0x1 << LOCAL_RX_STAT_Pos),
2392 LOCAL_RX_STAT_NOT_OK = (0x0 << LOCAL_RX_STAT_Pos),
2393 LOCAL_RX_STAT_OK = (0x1 << LOCAL_RX_STAT_Pos),
2394 LOCAL_ROLE_Pos = 14,
2395 LOCAL_ROLE_Msk = (0x1 << LOCAL_ROLE_Pos),
2396 LOCAL_ROLE_SLAVE = (0x0 << LOCAL_ROLE_Pos),
2397 LOCAL_ROLE_MASTER = (0x1 << LOCAL_ROLE_Pos),
2398 ROLE_FAULT_Pos = 15,
2399 ROLE_FAULT_Msk = (0x1 << ROLE_FAULT_Pos),
2400 ROLE_FAULT_NONE = (0x0 << ROLE_FAULT_Pos),
2401 ROLE_FAULT_DETECTED = (0x1 << ROLE_FAULT_Pos),
2402 };
2403
2404}
2405namespace PHY_MMD_SETUP {
2406 enum {
2407 DEV_ADDR_Pos = 0,
2408 DEV_ADDR_Msk = (0x1F << DEV_ADDR_Pos),
2409 OP_MODE_Pos = 14,
2410 OP_MODE_Msk = (0x3 << OP_MODE_Pos),
2411 OP_MODE_REGISTER = (0x00 << OP_MODE_Pos),
2412 OP_MODE_DATA = (0x01 << OP_MODE_Pos),
2413 OP_MODE_DATA_INCR = (0x02 << OP_MODE_Pos),
2414 OP_MODE_DATA_INCR_WRITE = (0x03 << OP_MODE_Pos),
2415 };
2416
2417 inline uint32_t DEV_ADDR(uint32_t _x)
2418 { return (((_x) << DEV_ADDR_Pos) & DEV_ADDR_Pos); }
2419 inline uint32_t OP_MODE(uint32_t _x)
2420 { return (((_x) << OP_MODE_Pos) & OP_MODE_Pos); }
2421
2422}
2423namespace PHY_EXT_STATUS {
2424 enum {
2425 _1000BT_HD_Pos = 12,
2426 _1000BT_HD_Msk = (0x1 << _1000BT_HD_Pos),
2427 _1000BT_HD_NOT_CAPABLE = (0x0 << _1000BT_HD_Pos),
2428 _1000BT_HD_CAPABLE = (0x1 << _1000BT_HD_Pos),
2429 _1000BT_FD_Pos = 13,
2430 _1000BT_FD_Msk = (0x1 << _1000BT_FD_Pos),
2431 _1000BT_FD_NOT_CAPABLE = (0x0 << _1000BT_FD_Pos),
2432 _1000BT_FD_CAPABLE = (0x1 << _1000BT_FD_Pos),
2433 _1000BX_HD_Pos = 14,
2434 _1000BX_HD_Msk = (0x1 << _1000BX_HD_Pos),
2435 _1000BX_HD_NOT_CAPABLE = (0x0 << _1000BX_HD_Pos),
2436 _1000BX_HD_CAPABLE = (0x1 << _1000BX_HD_Pos),
2437 _1000BX_FD_Pos = 15,
2438 _1000BX_FD_Msk = (0x1 << _1000BX_FD_Pos),
2439 _1000BX_FD_NOT_CAPABLE = (0x0 << _1000BX_FD_Pos),
2440 _1000BX_FD_CAPABLE = (0x1 << _1000BX_FD_Pos),
2441 };
2442
2443}
2444namespace PHY_REMOTE_LOOPBACK {
2445 enum {
2446 LINK_MD_PASS_Pos = 0,
2447 LINK_MD_PASS_Msk = (0x1 << LINK_MD_PASS_Pos),
2448 LINK_MD_PASS_DISABLED = (0x0 << LINK_MD_PASS_Pos),
2449 LINK_MD_PASS_ENABLED = (0x1 << LINK_MD_PASS_Pos),
2450 LINK_MD_10BT_Pos = 1,
2451 LINK_MD_10BT_Msk = (0x1 << LINK_MD_10BT_Pos),
2452 LINK_MD_10BT_DISABLED = (0x0 << LINK_MD_10BT_Pos),
2453 LINK_MD_10BT_ENABLED = (0x1 << LINK_MD_10BT_Pos),
2454 _10BT_PREAMBLE_Pos = 2,
2455 _10BT_PREAMBLE_Msk = (0x1 << _10BT_PREAMBLE_Pos),
2456 _10BT_PREAMBLE_DISABLED = (0x0 << _10BT_PREAMBLE_Pos),
2457 _10BT_PREAMBLE_ENABLED = (0x1 << _10BT_PREAMBLE_Pos),
2458 LED_CTRL_TEST_Pos = 3,
2459 LED_CTRL_TEST_Msk = (0x1 << LED_CTRL_TEST_Pos),
2460 LED_CTRL_TEST_DISABLED = (0x0 << LED_CTRL_TEST_Pos),
2461 LED_CTRL_TEST_ENABLED = (0x1 << LED_CTRL_TEST_Pos),
2462 LED_CTRL_Pos = 4,
2463 LED_CTRL_Msk = (0x1 << LED_CTRL_Pos),
2464 LED_CTRL_DISABLED = (0x0 << LED_CTRL_Pos),
2465 LED_CTRL_ENABLED = (0x1 << LED_CTRL_Pos),
2466 LED_SEL_Pos = 6,
2467 LED_SEL_Msk = (0x1 << LED_SEL_Pos),
2468 LED_SEL_DISABLED = (0x0 << LED_SEL_Pos),
2469 LED_SEL_ENABLED = (0x1 << LED_SEL_Pos),
2470 REMOTE_LOOPBACK_Pos = 8,
2471 REMOTE_LOOPBACK_Msk = (0x1 << REMOTE_LOOPBACK_Pos),
2472 REMOTE_LOOPBACK_DISABLED = (0x0 << REMOTE_LOOPBACK_Pos),
2473 REMOTE_LOOPBACK_ENABLED = (0x1 << REMOTE_LOOPBACK_Pos),
2474 };
2475
2476}
2477namespace PHY_LINK_MD {
2478 enum {
2479 CABLE_STATUS_Pos = 8,
2480 CABLE_STATUS_Msk = (0x3 << CABLE_STATUS_Pos),
2481 CABLE_STATUS_NORMAL = (0x0 << CABLE_STATUS_Pos),
2482 CABLE_STATUS_OPEN = (0x1 << CABLE_STATUS_Pos),
2483 CABLE_STATUS_SHORT = (0x2 << CABLE_STATUS_Pos),
2484 TEST_PAIR_Pos = 12,
2485 TEST_PAIR_Msk = (0x3 << TEST_PAIR_Pos),
2486 TEST_PAIR_A = (0x0 << TEST_PAIR_Pos),
2487 TEST_PAIR_B = (0x1 << TEST_PAIR_Pos),
2488 TEST_PAIR_C = (0x2 << TEST_PAIR_Pos),
2489 TEST_PAIR_D = (0x3 << TEST_PAIR_Pos),
2490 LINX_TX_Pos = 14,
2491 LINX_TX_Msk = (0x1 << LINX_TX_Pos),
2492 LINX_TX_ENABLED = (0x0 << LINX_TX_Pos),
2493 LINX_TX_DISABLED = (0x1 << LINX_TX_Pos),
2494 CABLE_TEST_Pos = 15,
2495 CABLE_TEST_Msk = (0x1 << CABLE_TEST_Pos),
2496 CABLE_TEST_DONE = (0x0 << CABLE_TEST_Pos),
2497 CABLE_TEST_DISABLED = (0x0 << CABLE_TEST_Pos),
2498 CABLE_TEST_ENABLED = (0x1 << CABLE_TEST_Pos),
2499 CABLE_TEST_IN_PROGRESS = (0x1 << CABLE_TEST_Pos),
2500 };
2501
2502}
2503namespace PHY_PMA_STATUS {
2504 enum {
2505 _100BTX_LINK_STATUS_Pos = 0,
2506 _100BTX_LINK_STATUS_Msk = (0x3 << _100BTX_LINK_STATUS_Pos),
2507 _100BTX_LINK_STATUS_DOWN = (0x0 << _100BTX_LINK_STATUS_Pos),
2508 _100BTX_LINK_STATUS_UP = (0x1 << _100BTX_LINK_STATUS_Pos),
2509 _1000BT_LINK_STATUS_Pos = 0,
2510 _1000BT_LINK_STATUS_Msk = (0x3 << _1000BT_LINK_STATUS_Pos),
2511 _1000BT_LINK_STATUS_DOWN = (0x0 << _1000BT_LINK_STATUS_Pos),
2512 _1000BT_LINK_STATUS_UP = (0x1 << _1000BT_LINK_STATUS_Pos),
2513 };
2514
2515}
2516namespace PHY_INT {
2517 enum {
2518 LINK_UP_IRQ_Pos = 0,
2519 LINK_UP_IRQ_Msk = (0x1 << LINK_UP_IRQ_Pos),
2520 REMOTE_FAULT_IRQ_Pos = 1,
2521 REMOTE_FAULT_IRQ_Msk = (0x1 << REMOTE_FAULT_IRQ_Pos),
2522 LINK_DOWN_IRQ_Pos = 2,
2523 LINK_DOWN_IRQ_Msk = (0x1 << LINK_DOWN_IRQ_Pos),
2524 LP_ACK_IRQ_Pos = 3,
2525 LP_ACK_IRQ_Msk = (0x1 << LP_ACK_IRQ_Pos),
2526 PARALLEL_FAULT_IRQ_Pos = 4,
2527 PARALLEL_FAULT_IRQ_Msk = (0x1 << PARALLEL_FAULT_IRQ_Pos),
2528 PG_RX_IRQ_Pos = 5,
2529 PG_RX_IRQ_Msk = (0x1 << PG_RX_IRQ_Pos),
2530 RX_ERR_IRQ_Pos = 6,
2531 RX_ERR_IRQ_Msk = (0x1 << RX_ERR_IRQ_Pos),
2532 JABBER_IRQ_Pos = 7,
2533 JABBER_IRQ_Msk = (0x1 << JABBER_IRQ_Pos),
2534 LINK_UP_Pos = 8,
2535 LINK_UP_Msk = (0x1 << LINK_UP_Pos),
2536 LINK_UP_DISABLED = (0x0 << LINK_UP_Pos),
2537 LINK_UP_ENABLED = (0x1 << LINK_UP_Pos),
2538 REMOTE_FAULT_Pos = 9,
2539 REMOTE_FAULT_Msk = (0x1 << REMOTE_FAULT_Pos),
2540 REMOTE_FAULT_DISABLED = (0x0 << REMOTE_FAULT_Pos),
2541 REMOTE_FAULT_ENABLED = (0x1 << REMOTE_FAULT_Pos),
2542 LINK_DOWN_Pos = 10,
2543 LINK_DOWN_Msk = (0x1 << LINK_DOWN_Pos),
2544 LINK_DOWN_DISABLED = (0x0 << LINK_DOWN_Pos),
2545 LINK_DOWN_ENABLED = (0x1 << LINK_DOWN_Pos),
2546 PARALLEL_FAULT_Pos = 11,
2547 PARALLEL_FAULT_Msk = (0x1 << PARALLEL_FAULT_Pos),
2548 PARALLEL_FAULT_DISABLED = (0x0 << PARALLEL_FAULT_Pos),
2549 PARALLEL_FAULT_ENABLED = (0x1 << PARALLEL_FAULT_Pos),
2550 PG_RX_Pos = 12,
2551 PG_RX_Msk = (0x1 << PG_RX_Pos),
2552 PG_RX_DISABLED = (0x0 << PG_RX_Pos),
2553 PG_RX_ENABLED = (0x1 << PG_RX_Pos),
2554 RX_ERR_Pos = 13,
2555 RX_ERR_Msk = (0x1 << RX_ERR_Pos),
2556 RX_ERR_DISABLED = (0x0 << RX_ERR_Pos),
2557 RX_ERR_ENABLED = (0x1 << RX_ERR_Pos),
2558 JABBER_Pos = 14,
2559 JABBER_Msk = (0x1 << JABBER_Pos),
2560 JABBER_DISABLED = (0x0 << JABBER_Pos),
2561 JABBER_ENABLED = (0x1 << JABBER_Pos),
2562 _100BTX_LINK_STATUS_Pos = 15,
2563 _100BTX_LINK_STATUS_Msk = (0x1 << _100BTX_LINK_STATUS_Pos),
2564 _100BTX_LINK_STATUS_DISABLED = (0x0 << _100BTX_LINK_STATUS_Pos),
2565 _100BTX_LINK_STATUS_ENABLED = (0x1 << _100BTX_LINK_STATUS_Pos),
2566 };
2567
2568}
2569namespace PHY_AUTO_MDIX {
2570 enum {
2571 AUTO_MDIX_DISABLE_Pos = 6,
2572 AUTO_MDIX_DISABLE_Msk = (0x1 << AUTO_MDIX_DISABLE_Pos),
2573 AUTO_MDIX_DISABLE_DISABLED = (0x1 << AUTO_MDIX_DISABLE_Pos),
2574 AUTO_MDIX_DISABLE_ENABLED = (0x0 << AUTO_MDIX_DISABLE_Pos),
2575 MDI_MODE_Pos = 7,
2576 MDI_MODE_Msk = (0x1 << MDI_MODE_Pos),
2577 MDI_MODE_MDI = (0x0 << MDI_MODE_Pos),
2578 MDI_MODE_MDIX = (0x1 << MDI_MODE_Pos),
2579 };
2580
2581}
2582namespace PHY_CTL_2 {
2583 enum {
2584 _1000BT_ROLE_Pos = 2,
2585 _1000BT_ROLE_Msk = (0x1 << _1000BT_ROLE_Pos),
2586 _1000BT_ROLE_MASTER = (0x1 << _1000BT_ROLE_Pos),
2587 _1000BT_ROLE_SLAVE = (0x0 << _1000BT_ROLE_Pos),
2588 DUPLEX_Pos = 3,
2589 DUPLEX_Msk = (0x1 << DUPLEX_Pos),
2590 DUPLEX_FULL = (0x1 << DUPLEX_Pos),
2591 DUPLEX_HALF = (0x0 << DUPLEX_Pos),
2592 SPEED_IS_10BT_Pos = 4,
2593 SPEED_IS_10BT_Msk = (0x1 << SPEED_IS_10BT_Pos),
2594 SPEED_IS_10BT_TRUE = (0x1 << SPEED_IS_10BT_Pos),
2595 SPEED_IS_10BT_FALSE = (0x0 << SPEED_IS_10BT_Pos),
2596 SPEED_IS_100BTX_Pos = 5,
2597 SPEED_IS_100BTX_Msk = (0x1 << SPEED_IS_100BTX_Pos),
2598 SPEED_IS_100BTX_TRUE = (0x1 << SPEED_IS_100BTX_Pos),
2599 SPEED_IS_100BTX_FALSE = (0x0 << SPEED_IS_100BTX_Pos),
2600 SPEED_IS_1000BT_Pos = 6,
2601 SPEED_IS_1000BT_Msk = (0x1 << SPEED_IS_1000BT_Pos),
2602 SPEED_IS_1000BT_TRUE = (0x1 << SPEED_IS_1000BT_Pos),
2603 SPEED_IS_1000BT_FALSE = (0x0 << SPEED_IS_1000BT_Pos),
2604 JABBER_COUNTER_Pos = 9,
2605 JABBER_COUNTER_Msk = (0x1 << JABBER_COUNTER_Pos),
2606 JABBER_COUNTER_DISABLED = (0x0 << JABBER_COUNTER_Pos),
2607 JABBER_COUNTER_ENABLED = (0x1 << JABBER_COUNTER_Pos),
2608 };
2609
2610}
2611
2612namespace PORT_XMII_CTRL {
2613 enum {
2614 RGMII_IBS_LINK_STATUS_Pos = 0,
2615 RGMII_IBS_LINK_STATUS_Msk = (0x1 << RGMII_IBS_LINK_STATUS_Pos),
2616 RGMII_IBS_LINK_STATUS_UP = (0x1 << RGMII_IBS_LINK_STATUS_Pos),
2617 RGMII_IBS_LINK_STATUS_DOWN = (0x0 << RGMII_IBS_LINK_STATUS_Pos),
2618 RGMII_IBS_RCLK_SPD_Pos = 1,
2619 RGMII_IBS_RCLK_SPD_Msk = (0x3 << RGMII_IBS_RCLK_SPD_Pos),
2620 RGMII_IBS_RCLK_SPD_2_5M = (0x0 << RGMII_IBS_RCLK_SPD_Pos),
2621 RGMII_IBS_RCLK_SPD_25M = (0x1 << RGMII_IBS_RCLK_SPD_Pos),
2622 RGMII_IBS_RCLK_SPD_125M = (0x2 << RGMII_IBS_RCLK_SPD_Pos),
2623 RGMII_IBS_DUPLEX_Pos = 3,
2624 RGMII_IBS_DUPLEX_Msk = (0x1 << RGMII_IBS_DUPLEX_Pos),
2625 RGMII_IBS_DUPLEX_FULL = (0x1 << RGMII_IBS_DUPLEX_Pos),
2626 RGMII_IBS_DUPLEX_HALF = (0x0 << RGMII_IBS_DUPLEX_Pos),
2627 MII_MODE_Pos = 16,
2628 MII_MODE_Msk = (0x3 << MII_MODE_Pos),
2629 MII_MODE_MII = (0x0 << MII_MODE_Pos),
2630 MII_MODE_RMII = (0x1 << MII_MODE_Pos),
2631 MII_MODE_GMII = (0x2 << MII_MODE_Pos),
2632 MII_MODE_RGMII = (0x3 << MII_MODE_Pos),
2633 MII_CFG_Pos = 18,
2634 MII_CFG_Msk = (0x1 << MII_CFG_Pos),
2635 MII_CFG_MII_PHY = (0x0 << MII_CFG_Pos),
2636 MII_CFG_MII_MAC = (0x1 << MII_CFG_Pos),
2637 MII_CFG_RMII_CLK_IN = (0x0 << MII_CFG_Pos),
2638 MII_CFG_RMII_CLK_OUT = (0x1 << MII_CFG_Pos),
2639 MII_CFG_RGMII_IBS_DISABLED = (0x0 << MII_CFG_Pos),
2640 MII_CFG_RGMII_IBS_ENABLED = (0x1 << MII_CFG_Pos),
2641 RGMII_EGRESS_DLY_Pos = 19,
2642 RGMII_EGRESS_DLY_Msk = (0x1 << RGMII_EGRESS_DLY_Pos),
2643 RGMII_EGRESS_DLY_ENABLED = (0x1 << RGMII_EGRESS_DLY_Pos),
2644 RGMII_EGRESS_DLY_DISABLED = (0x0 << RGMII_EGRESS_DLY_Pos),
2645 RGMII_INGRESS_DLY_Pos = 20,
2646 RGMII_INGRESS_DLY_Msk = (0x1 << RGMII_INGRESS_DLY_Pos),
2647 RGMII_INGRESS_DLY_ENABLED = (0x1 << RGMII_INGRESS_DLY_Pos),
2648 RGMII_INGRESS_DLY_DISABLED = (0x0 << RGMII_INGRESS_DLY_Pos),
2649 MII_SEL_EDGE_Pos = 21,
2650 MII_SEL_EDGE_Msk = (0x1 << MII_SEL_EDGE_Pos),
2651 MII_SEL_EDGE_FALLINg = (0x1 << MII_SEL_EDGE_Pos),
2652 MII_SEL_EDGE_RISING = (0x0 << MII_SEL_EDGE_Pos),
2653 MII_1000M_Pos = 22,
2654 MII_1000M_Msk = (0x1 << MII_1000M_Pos),
2655 MII_1000M_1000M = (0x1 << MII_1000M_Pos),
2656 MII_1000M_10_OR_100M = (0x0 << MII_1000M_Pos),
2657 MII_CLK_SEL_Pos = 23,
2658 MII_CLK_SEL_Msk = (0x1 << MII_CLK_SEL_Pos),
2659 MII_CLK_SEL_MASTER = (0x1 << MII_CLK_SEL_Pos),
2660 MII_CLK_SEL_SLAVE = (0x0 << MII_CLK_SEL_Pos),
2661 GRXC_Pos = 24,
2662 GRXC_Msk = (0x1 << GRXC_Pos),
2663 GRXC_ENABLED = (0x1 << GRXC_Pos),
2664 GRXC_DISABLED = (0x0 << GRXC_Pos),
2665 RX_FLOW_CTRL_Pos = 27,
2666 RX_FLOW_CTRL_Msk = (0x1 << RX_FLOW_CTRL_Pos),
2667 RX_FLOW_CTRL_ENABLED = (0x1 << RX_FLOW_CTRL_Pos),
2668 RX_FLOW_CTRL_DISABLED = (0x0 << RX_FLOW_CTRL_Pos),
2669 MII_SPEED_Pos = 28,
2670 MII_SPEED_Msk = (0x1 << MII_SPEED_Pos),
2671 MII_SPEED_100M = (0x1 << MII_SPEED_Pos),
2672 MII_SPEED_10M = (0x0 << MII_SPEED_Pos),
2673 TX_FLOW_CTRL_Pos = 29,
2674 TX_FLOW_CTRL_Msk = (0x1 << TX_FLOW_CTRL_Pos),
2675 TX_FLOW_CTRL_ENABLED = (0x1 << TX_FLOW_CTRL_Pos),
2676 TX_FLOW_CTRL_DISABLED = (0x0 << TX_FLOW_CTRL_Pos),
2677 DUPLEX_Pos = 30,
2678 DUPLEX_Msk = (0x1 << DUPLEX_Pos),
2679 DUPLEX_FULL = (0x1 << DUPLEX_Pos),
2680 DUPLEX_HALF = (0x0 << DUPLEX_Pos),
2681 SGMII_MODE_Pos = 31,
2682 SGMII_MODE_Msk = (0x1 << SGMII_MODE_Pos),
2683 SGMII_MODE_ENABLED = (0x1 << SGMII_MODE_Pos),
2684 SGMII_MODE_DISABLED = (0x0 << SGMII_MODE_Pos),
2685 };
2686
2687}
2688
2689namespace PORT_MAC_CTRL {
2690 enum {
2691 COUNT_PREAMBLE_Pos = 0,
2692 COUNT_PREAMBLE_Msk = (0x1 << COUNT_PREAMBLE_Pos),
2693 COUNT_PREAMBLE_ENABLED = (0x1 << COUNT_PREAMBLE_Pos),
2694 COUNT_PREAMBLE_DISABLED = (0x0 << COUNT_PREAMBLE_Pos),
2695 COUNT_IFG_Pos = 1,
2696 COUNT_IFG_Msk = (0x1 << COUNT_IFG_Pos),
2697 COUNT_IFG_ENABLED = (0x1 << COUNT_IFG_Pos),
2698 COUNT_IFG_DISABLED = (0x0 << COUNT_IFG_Pos),
2699 IN_LIMIT_MODE_Pos = 2,
2700 IN_LIMIT_MODE_Msk = (0x3 << IN_LIMIT_MODE_Pos),
2701 IN_LIMIT_MODE_ALL = (0x0 << IN_LIMIT_MODE_Pos),
2702 IN_LIMIT_MODE_UCAST = (0x1 << IN_LIMIT_MODE_Pos),
2703 IN_LIMIT_MODE_MCAST = (0x2 << IN_LIMIT_MODE_Pos),
2704 IN_LIMIT_MODE_BCAST = (0x3 << IN_LIMIT_MODE_Pos),
2705 IN_FLOW_CTRL_Pos = 4,
2706 IN_FLOW_CTRL_Msk = (0x1 << IN_FLOW_CTRL_Pos),
2707 IN_FLOW_CTRL_ENABLED = (0x1 << IN_FLOW_CTRL_Pos),
2708 IN_FLOW_CTRL_DISABLED = (0x0 << IN_FLOW_CTRL_Pos),
2709 IN_PKT_RATE_Pos = 5,
2710 IN_PKT_RATE_Msk = (0x1 << IN_PKT_RATE_Pos),
2711 IN_PKT_RATE_ENABLED = (0x1 << IN_PKT_RATE_Pos),
2712 IN_PKT_RATE_DISABLED = (0x0 << IN_PKT_RATE_Pos),
2713 IN_RATE_Pos = 6,
2714 IN_RATE_Msk = (0x1 << IN_RATE_Pos),
2715 IN_RATE_PORT = (0x1 << IN_RATE_Pos),
2716 IN_RATE_PRIO = (0x0 << IN_RATE_Pos),
2717 _1000BT_EEE_Pos = 14,
2718 _1000BT_EEE_Msk = (0x1 << _1000BT_EEE_Pos),
2719 _1000BT_EEE_ENABLED = (0x0 << _1000BT_EEE_Pos),
2720 _1000BT_EEE_DISABLED = (0x1 << _1000BT_EEE_Pos),
2721 _100BTX_EEE_Pos = 15,
2722 _100BTX_EEE_Msk = (0x1 << _100BTX_EEE_Pos),
2723 _100BTX_EEE_ENABLED = (0x0 << _100BTX_EEE_Pos),
2724 _100BTX_EEE_DISABLED = (0x1 << _100BTX_EEE_Pos),
2725 PASS_ALL_Pos = 16,
2726 PASS_ALL_Msk = (0x1 << PASS_ALL_Pos),
2727 PASS_ALL_ENABLED = (0x1 << PASS_ALL_Pos),
2728 PASS_ALL_DISABLED = (0x0 << PASS_ALL_Pos),
2729 BACK_PRESSURE_Pos = 17,
2730 BACK_PRESSURE_Msk = (0x1 << BACK_PRESSURE_Pos),
2731 BACK_PRESSURE_ENABLED = (0x1 << BACK_PRESSURE_Pos),
2732 BACK_PRESSURE_DISABLED = (0x0 << BACK_PRESSURE_Pos),
2733 JUMBO_FRAME_Pos = 24,
2734 JUMBO_FRAME_Msk = (0x1 << JUMBO_FRAME_Pos),
2735 BCAST_STORM_PROT_Pos = 25,
2736 BCAST_STORM_PROT_Msk = (0x1 << BCAST_STORM_PROT_Pos),
2737 BCAST_STORM_PROT_ENABLED = (0x1 << BCAST_STORM_PROT_Pos),
2738 BCAST_STORM_PROT_DISABLED = (0x0 << BCAST_STORM_PROT_Pos),
2739 };
2740
2741}
2742namespace PORT_IN_RATE_0 {
2743 enum {
2744 RATE_LIMIT_Pos = 0,
2745 RATE_LIMIT_Msk = (0x7F << RATE_LIMIT_Pos),
2746 RATE_LIMIT_640 = (101 << RATE_LIMIT_Pos),
2747 RATE_LIMIT_1280 = (102 << RATE_LIMIT_Pos),
2748 RATE_LIMIT_2560 = (103 << RATE_LIMIT_Pos),
2749 RATE_LIMIT_3840 = (104 << RATE_LIMIT_Pos),
2750 RATE_LIMIT_5120 = (105 << RATE_LIMIT_Pos),
2751 RATE_LIMIT_6400 = (106 << RATE_LIMIT_Pos),
2752 RATE_LIMIT_7680 = (107 << RATE_LIMIT_Pos),
2753 RATE_LIMIT_8960 = (108 << RATE_LIMIT_Pos),
2754 RATE_LIMIT_10240 = (109 << RATE_LIMIT_Pos),
2755 RATE_LIMIT_11520 = (110 << RATE_LIMIT_Pos),
2756 RATE_LIMIT_12800 = (111 << RATE_LIMIT_Pos),
2757 RATE_LIMIT_14080 = (112 << RATE_LIMIT_Pos),
2758 RATE_LIMIT_15360 = (113 << RATE_LIMIT_Pos),
2759 RATE_LIMIT_16640 = (114 << RATE_LIMIT_Pos),
2760 RATE_LIMIT_17920 = (115 << RATE_LIMIT_Pos),
2761 };
2762
2763 inline uint32_t RATE_LIMIT(uint32_t _x)
2764 { return (((_x) << RATE_LIMIT_Pos) & RATE_LIMIT_Msk); }
2765
2766}
2767namespace PORT_IN_RATE_1 {
2768 enum {
2769 RATE_LIMIT_Pos = 0,
2770 RATE_LIMIT_Msk = (0x7F << RATE_LIMIT_Pos),
2771 RATE_LIMIT_640 = (101 << RATE_LIMIT_Pos),
2772 RATE_LIMIT_1280 = (102 << RATE_LIMIT_Pos),
2773 RATE_LIMIT_2560 = (103 << RATE_LIMIT_Pos),
2774 RATE_LIMIT_3840 = (104 << RATE_LIMIT_Pos),
2775 RATE_LIMIT_5120 = (105 << RATE_LIMIT_Pos),
2776 RATE_LIMIT_6400 = (106 << RATE_LIMIT_Pos),
2777 RATE_LIMIT_7680 = (107 << RATE_LIMIT_Pos),
2778 RATE_LIMIT_8960 = (108 << RATE_LIMIT_Pos),
2779 RATE_LIMIT_10240 = (109 << RATE_LIMIT_Pos),
2780 RATE_LIMIT_11520 = (110 << RATE_LIMIT_Pos),
2781 RATE_LIMIT_12800 = (111 << RATE_LIMIT_Pos),
2782 RATE_LIMIT_14080 = (112 << RATE_LIMIT_Pos),
2783 RATE_LIMIT_15360 = (113 << RATE_LIMIT_Pos),
2784 RATE_LIMIT_16640 = (114 << RATE_LIMIT_Pos),
2785 RATE_LIMIT_17920 = (115 << RATE_LIMIT_Pos),
2786 };
2787
2788 inline uint32_t RATE_LIMIT(uint32_t _x)
2789 { return (((_x) << RATE_LIMIT_Pos) & RATE_LIMIT_Msk); }
2790
2791}
2792namespace PORT_IN_RATE_2 {
2793 enum {
2794 RATE_LIMIT_Pos = 0,
2795 RATE_LIMIT_Msk = (0x7F << RATE_LIMIT_Pos),
2796 RATE_LIMIT_640 = (101 << RATE_LIMIT_Pos),
2797 RATE_LIMIT_1280 = (102 << RATE_LIMIT_Pos),
2798 RATE_LIMIT_2560 = (103 << RATE_LIMIT_Pos),
2799 RATE_LIMIT_3840 = (104 << RATE_LIMIT_Pos),
2800 RATE_LIMIT_5120 = (105 << RATE_LIMIT_Pos),
2801 RATE_LIMIT_6400 = (106 << RATE_LIMIT_Pos),
2802 RATE_LIMIT_7680 = (107 << RATE_LIMIT_Pos),
2803 RATE_LIMIT_8960 = (108 << RATE_LIMIT_Pos),
2804 RATE_LIMIT_10240 = (109 << RATE_LIMIT_Pos),
2805 RATE_LIMIT_11520 = (110 << RATE_LIMIT_Pos),
2806 RATE_LIMIT_12800 = (111 << RATE_LIMIT_Pos),
2807 RATE_LIMIT_14080 = (112 << RATE_LIMIT_Pos),
2808 RATE_LIMIT_15360 = (113 << RATE_LIMIT_Pos),
2809 RATE_LIMIT_16640 = (114 << RATE_LIMIT_Pos),
2810 RATE_LIMIT_17920 = (115 << RATE_LIMIT_Pos),
2811 };
2812
2813 inline uint32_t RATE_LIMIT(uint32_t _x)
2814 { return (((_x) << RATE_LIMIT_Pos) & RATE_LIMIT_Msk); }
2815
2816}
2817namespace PORT_IN_RATE_3 {
2818 enum {
2819 RATE_LIMIT_Pos = 0,
2820 RATE_LIMIT_Msk = (0x7F << RATE_LIMIT_Pos),
2821 RATE_LIMIT_640 = (101 << RATE_LIMIT_Pos),
2822 RATE_LIMIT_1280 = (102 << RATE_LIMIT_Pos),
2823 RATE_LIMIT_2560 = (103 << RATE_LIMIT_Pos),
2824 RATE_LIMIT_3840 = (104 << RATE_LIMIT_Pos),
2825 RATE_LIMIT_5120 = (105 << RATE_LIMIT_Pos),
2826 RATE_LIMIT_6400 = (106 << RATE_LIMIT_Pos),
2827 RATE_LIMIT_7680 = (107 << RATE_LIMIT_Pos),
2828 RATE_LIMIT_8960 = (108 << RATE_LIMIT_Pos),
2829 RATE_LIMIT_10240 = (109 << RATE_LIMIT_Pos),
2830 RATE_LIMIT_11520 = (110 << RATE_LIMIT_Pos),
2831 RATE_LIMIT_12800 = (111 << RATE_LIMIT_Pos),
2832 RATE_LIMIT_14080 = (112 << RATE_LIMIT_Pos),
2833 RATE_LIMIT_15360 = (113 << RATE_LIMIT_Pos),
2834 RATE_LIMIT_16640 = (114 << RATE_LIMIT_Pos),
2835 RATE_LIMIT_17920 = (115 << RATE_LIMIT_Pos),
2836 };
2837
2838 inline uint32_t RATE_LIMIT(uint32_t _x)
2839 { return (((_x) << RATE_LIMIT_Pos) & RATE_LIMIT_Msk); }
2840
2841}
2842namespace PORT_IN_RATE_4 {
2843 enum {
2844 RATE_LIMIT_Pos = 0,
2845 RATE_LIMIT_Msk = (0x7F << RATE_LIMIT_Pos),
2846 RATE_LIMIT_640 = (101 << RATE_LIMIT_Pos),
2847 RATE_LIMIT_1280 = (102 << RATE_LIMIT_Pos),
2848 RATE_LIMIT_2560 = (103 << RATE_LIMIT_Pos),
2849 RATE_LIMIT_3840 = (104 << RATE_LIMIT_Pos),
2850 RATE_LIMIT_5120 = (105 << RATE_LIMIT_Pos),
2851 RATE_LIMIT_6400 = (106 << RATE_LIMIT_Pos),
2852 RATE_LIMIT_7680 = (107 << RATE_LIMIT_Pos),
2853 RATE_LIMIT_8960 = (108 << RATE_LIMIT_Pos),
2854 RATE_LIMIT_10240 = (109 << RATE_LIMIT_Pos),
2855 RATE_LIMIT_11520 = (110 << RATE_LIMIT_Pos),
2856 RATE_LIMIT_12800 = (111 << RATE_LIMIT_Pos),
2857 RATE_LIMIT_14080 = (112 << RATE_LIMIT_Pos),
2858 RATE_LIMIT_15360 = (113 << RATE_LIMIT_Pos),
2859 RATE_LIMIT_16640 = (114 << RATE_LIMIT_Pos),
2860 RATE_LIMIT_17920 = (115 << RATE_LIMIT_Pos),
2861 };
2862
2863 inline uint32_t RATE_LIMIT(uint32_t _x)
2864 { return (((_x) << RATE_LIMIT_Pos) & RATE_LIMIT_Msk); }
2865
2866}
2867namespace PORT_IN_RATE_5 {
2868 enum {
2869 RATE_LIMIT_Pos = 0,
2870 RATE_LIMIT_Msk = (0x7F << RATE_LIMIT_Pos),
2871 RATE_LIMIT_640 = (101 << RATE_LIMIT_Pos),
2872 RATE_LIMIT_1280 = (102 << RATE_LIMIT_Pos),
2873 RATE_LIMIT_2560 = (103 << RATE_LIMIT_Pos),
2874 RATE_LIMIT_3840 = (104 << RATE_LIMIT_Pos),
2875 RATE_LIMIT_5120 = (105 << RATE_LIMIT_Pos),
2876 RATE_LIMIT_6400 = (106 << RATE_LIMIT_Pos),
2877 RATE_LIMIT_7680 = (107 << RATE_LIMIT_Pos),
2878 RATE_LIMIT_8960 = (108 << RATE_LIMIT_Pos),
2879 RATE_LIMIT_10240 = (109 << RATE_LIMIT_Pos),
2880 RATE_LIMIT_11520 = (110 << RATE_LIMIT_Pos),
2881 RATE_LIMIT_12800 = (111 << RATE_LIMIT_Pos),
2882 RATE_LIMIT_14080 = (112 << RATE_LIMIT_Pos),
2883 RATE_LIMIT_15360 = (113 << RATE_LIMIT_Pos),
2884 RATE_LIMIT_16640 = (114 << RATE_LIMIT_Pos),
2885 RATE_LIMIT_17920 = (115 << RATE_LIMIT_Pos),
2886 };
2887
2888 inline uint32_t RATE_LIMIT(uint32_t _x)
2889 { return (((_x) << RATE_LIMIT_Pos) & RATE_LIMIT_Msk); }
2890
2891}
2892namespace PORT_IN_RATE_6 {
2893 enum {
2894 RATE_LIMIT_Pos = 0,
2895 RATE_LIMIT_Msk = (0x7F << RATE_LIMIT_Pos),
2896 RATE_LIMIT_640 = (101 << RATE_LIMIT_Pos),
2897 RATE_LIMIT_1280 = (102 << RATE_LIMIT_Pos),
2898 RATE_LIMIT_2560 = (103 << RATE_LIMIT_Pos),
2899 RATE_LIMIT_3840 = (104 << RATE_LIMIT_Pos),
2900 RATE_LIMIT_5120 = (105 << RATE_LIMIT_Pos),
2901 RATE_LIMIT_6400 = (106 << RATE_LIMIT_Pos),
2902 RATE_LIMIT_7680 = (107 << RATE_LIMIT_Pos),
2903 RATE_LIMIT_8960 = (108 << RATE_LIMIT_Pos),
2904 RATE_LIMIT_10240 = (109 << RATE_LIMIT_Pos),
2905 RATE_LIMIT_11520 = (110 << RATE_LIMIT_Pos),
2906 RATE_LIMIT_12800 = (111 << RATE_LIMIT_Pos),
2907 RATE_LIMIT_14080 = (112 << RATE_LIMIT_Pos),
2908 RATE_LIMIT_15360 = (113 << RATE_LIMIT_Pos),
2909 RATE_LIMIT_16640 = (114 << RATE_LIMIT_Pos),
2910 RATE_LIMIT_17920 = (115 << RATE_LIMIT_Pos),
2911 };
2912
2913 inline uint32_t RATE_LIMIT(uint32_t _x)
2914 { return (((_x) << RATE_LIMIT_Pos) & RATE_LIMIT_Msk); }
2915
2916}
2917namespace PORT_IN_RATE_7 {
2918 enum {
2919 RATE_LIMIT_Pos = 0,
2920 RATE_LIMIT_Msk = (0x7F << RATE_LIMIT_Pos),
2921 RATE_LIMIT_640 = (101 << RATE_LIMIT_Pos),
2922 RATE_LIMIT_1280 = (102 << RATE_LIMIT_Pos),
2923 RATE_LIMIT_2560 = (103 << RATE_LIMIT_Pos),
2924 RATE_LIMIT_3840 = (104 << RATE_LIMIT_Pos),
2925 RATE_LIMIT_5120 = (105 << RATE_LIMIT_Pos),
2926 RATE_LIMIT_6400 = (106 << RATE_LIMIT_Pos),
2927 RATE_LIMIT_7680 = (107 << RATE_LIMIT_Pos),
2928 RATE_LIMIT_8960 = (108 << RATE_LIMIT_Pos),
2929 RATE_LIMIT_10240 = (109 << RATE_LIMIT_Pos),
2930 RATE_LIMIT_11520 = (110 << RATE_LIMIT_Pos),
2931 RATE_LIMIT_12800 = (111 << RATE_LIMIT_Pos),
2932 RATE_LIMIT_14080 = (112 << RATE_LIMIT_Pos),
2933 RATE_LIMIT_15360 = (113 << RATE_LIMIT_Pos),
2934 RATE_LIMIT_16640 = (114 << RATE_LIMIT_Pos),
2935 RATE_LIMIT_17920 = (115 << RATE_LIMIT_Pos),
2936 };
2937
2938 inline uint32_t RATE_LIMIT(uint32_t _x)
2939 { return (((_x) << RATE_LIMIT_Pos) & RATE_LIMIT_Msk); }
2940
2941}
2942namespace PORT_OUT_RATE_0 {
2943 enum {
2944 RATE_LIMIT_Pos = 0,
2945 RATE_LIMIT_Msk = (0x7F << RATE_LIMIT_Pos),
2946 RATE_LIMIT_640 = (101 << RATE_LIMIT_Pos),
2947 RATE_LIMIT_1280 = (102 << RATE_LIMIT_Pos),
2948 RATE_LIMIT_2560 = (103 << RATE_LIMIT_Pos),
2949 RATE_LIMIT_3840 = (104 << RATE_LIMIT_Pos),
2950 RATE_LIMIT_5120 = (105 << RATE_LIMIT_Pos),
2951 RATE_LIMIT_6400 = (106 << RATE_LIMIT_Pos),
2952 RATE_LIMIT_7680 = (107 << RATE_LIMIT_Pos),
2953 RATE_LIMIT_8960 = (108 << RATE_LIMIT_Pos),
2954 RATE_LIMIT_10240 = (109 << RATE_LIMIT_Pos),
2955 RATE_LIMIT_11520 = (110 << RATE_LIMIT_Pos),
2956 RATE_LIMIT_12800 = (111 << RATE_LIMIT_Pos),
2957 RATE_LIMIT_14080 = (112 << RATE_LIMIT_Pos),
2958 RATE_LIMIT_15360 = (113 << RATE_LIMIT_Pos),
2959 RATE_LIMIT_16640 = (114 << RATE_LIMIT_Pos),
2960 RATE_LIMIT_17920 = (115 << RATE_LIMIT_Pos),
2961 };
2962
2963 inline uint32_t RATE_LIMIT(uint32_t _x)
2964 { return (((_x) << RATE_LIMIT_Pos) & RATE_LIMIT_Msk); }
2965
2966}
2967namespace PORT_OUT_RATE_1 {
2968 enum {
2969 RATE_LIMIT_Pos = 0,
2970 RATE_LIMIT_Msk = (0x7F << RATE_LIMIT_Pos),
2971 RATE_LIMIT_640 = (101 << RATE_LIMIT_Pos),
2972 RATE_LIMIT_1280 = (102 << RATE_LIMIT_Pos),
2973 RATE_LIMIT_2560 = (103 << RATE_LIMIT_Pos),
2974 RATE_LIMIT_3840 = (104 << RATE_LIMIT_Pos),
2975 RATE_LIMIT_5120 = (105 << RATE_LIMIT_Pos),
2976 RATE_LIMIT_6400 = (106 << RATE_LIMIT_Pos),
2977 RATE_LIMIT_7680 = (107 << RATE_LIMIT_Pos),
2978 RATE_LIMIT_8960 = (108 << RATE_LIMIT_Pos),
2979 RATE_LIMIT_10240 = (109 << RATE_LIMIT_Pos),
2980 RATE_LIMIT_11520 = (110 << RATE_LIMIT_Pos),
2981 RATE_LIMIT_12800 = (111 << RATE_LIMIT_Pos),
2982 RATE_LIMIT_14080 = (112 << RATE_LIMIT_Pos),
2983 RATE_LIMIT_15360 = (113 << RATE_LIMIT_Pos),
2984 RATE_LIMIT_16640 = (114 << RATE_LIMIT_Pos),
2985 RATE_LIMIT_17920 = (115 << RATE_LIMIT_Pos),
2986 };
2987
2988 inline uint32_t RATE_LIMIT(uint32_t _x)
2989 { return (((_x) << RATE_LIMIT_Pos) & RATE_LIMIT_Msk); }
2990
2991}
2992namespace PORT_OUT_RATE_2 {
2993 enum {
2994 RATE_LIMIT_Pos = 0,
2995 RATE_LIMIT_Msk = (0x7F << RATE_LIMIT_Pos),
2996 RATE_LIMIT_640 = (101 << RATE_LIMIT_Pos),
2997 RATE_LIMIT_1280 = (102 << RATE_LIMIT_Pos),
2998 RATE_LIMIT_2560 = (103 << RATE_LIMIT_Pos),
2999 RATE_LIMIT_3840 = (104 << RATE_LIMIT_Pos),
3000 RATE_LIMIT_5120 = (105 << RATE_LIMIT_Pos),
3001 RATE_LIMIT_6400 = (106 << RATE_LIMIT_Pos),
3002 RATE_LIMIT_7680 = (107 << RATE_LIMIT_Pos),
3003 RATE_LIMIT_8960 = (108 << RATE_LIMIT_Pos),
3004 RATE_LIMIT_10240 = (109 << RATE_LIMIT_Pos),
3005 RATE_LIMIT_11520 = (110 << RATE_LIMIT_Pos),
3006 RATE_LIMIT_12800 = (111 << RATE_LIMIT_Pos),
3007 RATE_LIMIT_14080 = (112 << RATE_LIMIT_Pos),
3008 RATE_LIMIT_15360 = (113 << RATE_LIMIT_Pos),
3009 RATE_LIMIT_16640 = (114 << RATE_LIMIT_Pos),
3010 RATE_LIMIT_17920 = (115 << RATE_LIMIT_Pos),
3011 };
3012
3013 inline uint32_t RATE_LIMIT(uint32_t _x)
3014 { return (((_x) << RATE_LIMIT_Pos) & RATE_LIMIT_Msk); }
3015
3016}
3017namespace PORT_OUT_RATE_3 {
3018 enum {
3019 RATE_LIMIT_Pos = 0,
3020 RATE_LIMIT_Msk = (0x7F << RATE_LIMIT_Pos),
3021 RATE_LIMIT_640 = (101 << RATE_LIMIT_Pos),
3022 RATE_LIMIT_1280 = (102 << RATE_LIMIT_Pos),
3023 RATE_LIMIT_2560 = (103 << RATE_LIMIT_Pos),
3024 RATE_LIMIT_3840 = (104 << RATE_LIMIT_Pos),
3025 RATE_LIMIT_5120 = (105 << RATE_LIMIT_Pos),
3026 RATE_LIMIT_6400 = (106 << RATE_LIMIT_Pos),
3027 RATE_LIMIT_7680 = (107 << RATE_LIMIT_Pos),
3028 RATE_LIMIT_8960 = (108 << RATE_LIMIT_Pos),
3029 RATE_LIMIT_10240 = (109 << RATE_LIMIT_Pos),
3030 RATE_LIMIT_11520 = (110 << RATE_LIMIT_Pos),
3031 RATE_LIMIT_12800 = (111 << RATE_LIMIT_Pos),
3032 RATE_LIMIT_14080 = (112 << RATE_LIMIT_Pos),
3033 RATE_LIMIT_15360 = (113 << RATE_LIMIT_Pos),
3034 RATE_LIMIT_16640 = (114 << RATE_LIMIT_Pos),
3035 RATE_LIMIT_17920 = (115 << RATE_LIMIT_Pos),
3036 };
3037
3038 inline uint32_t RATE_LIMIT(uint32_t _x)
3039 { return (((_x) << RATE_LIMIT_Pos) & RATE_LIMIT_Msk); }
3040
3041}
3042
3043namespace PORT_MIB_CTRL_STAT {
3044 enum {
3045 MIB_COUNTER_HI_Pos = 0,
3046 MIB_COUNTER_HI_Msk = (0xF << MIB_COUNTER_HI_Pos),
3047 MIB_INDEX_Pos = 16,
3048 MIB_INDEX_Msk = (0xFF << MIB_INDEX_Pos),
3049 FLUSH_AND_FREEZE_Pos = 24,
3050 FLUSH_AND_FREEZE_Msk = (0x1 << FLUSH_AND_FREEZE_Pos),
3051 FLUSH_AND_FREEZE_DISABLED = (0x0 << FLUSH_AND_FREEZE_Pos),
3052 FLUSH_AND_FREEZE_ENABLED = (0x1 << FLUSH_AND_FREEZE_Pos),
3053 MIB_COUNTER_RD_ENABLE_Pos = 25,
3054 MIB_COUNTER_RD_ENABLE_Msk = (0x1 << MIB_COUNTER_RD_ENABLE_Pos),
3055 MIB_COUNTER_RD_ENABLE_ENABLED= (0x1 << MIB_COUNTER_RD_ENABLE_Pos),
3056 MIB_COUNTER_VALID_Pos = 30,
3057 MIB_COUNTER_VALID_Msk = (0x1 << MIB_COUNTER_VALID_Pos),
3058 MIB_COUNTER_VALID_VALID = (0x0 << MIB_COUNTER_VALID_Pos),
3059 MIB_COUNTER_VALID_INVALID = (0x1 << MIB_COUNTER_VALID_Pos),
3060 COUNTER_OVERFLOW_Pos = 31,
3061 COUNTER_OVERFLOW_Msk = (0x1 << COUNTER_OVERFLOW_Pos),
3062 };
3063
3064 enum {
3065 MIB_COUNTER_ID_RX_HI_PRIO = 0x00,
3066 MIB_COUNTER_ID_RX_UNDRSIZ = 0x01,
3067 MIB_COUNTER_ID_RX_FRAG = 0x02,
3068 MIB_COUNTER_ID_RX_OVRSIZ = 0x03,
3069 MIB_COUNTER_ID_RX_JABBER = 0x04,
3070 MIB_COUNTER_ID_RX_ERR_SYM = 0x05,
3071 MIB_COUNTER_ID_RX_ERR_CRC = 0x06,
3072 MIB_COUNTER_ID_RX_ERR_ALIGN = 0x07,
3073 MIB_COUNTER_ID_RX_CTL_8808 = 0x08,
3074 MIB_COUNTER_ID_RX_PAUSE = 0x09,
3075 MIB_COUNTER_ID_RX_BCAST = 0x0A,
3076 MIB_COUNTER_ID_RX_MCAST = 0x0B,
3077 MIB_COUNTER_ID_RX_UCAST = 0x0C,
3078 MIB_COUNTER_ID_RX_SIZ_64 = 0x0D,
3079 MIB_COUNTER_ID_RX_SIZ_127 = 0x0E,
3080 MIB_COUNTER_ID_RX_SIZ_255 = 0x0F,
3081 MIB_COUNTER_ID_RX_SIZ_511 = 0x10,
3082 MIB_COUNTER_ID_RX_SIZ_1023 = 0x11,
3083 MIB_COUNTER_ID_RX_SIZ_1522 = 0x12,
3084 MIB_COUNTER_ID_RX_SIZ_2000 = 0x13,
3085 MIB_COUNTER_ID_RX_SIZ_2001P = 0x14,
3086 MIB_COUNTER_ID_TX_HI_PRIO = 0x15,
3087 MIB_COUNTER_ID_TX_LATE_COL = 0x16,
3088 MIB_COUNTER_ID_TX_PAUSE = 0x17,
3089 MIB_COUNTER_ID_TX_BCAST = 0x18,
3090 MIB_COUNTER_ID_TX_MCAST = 0x19,
3091 MIB_COUNTER_ID_TX_UCAST = 0x1A,
3092 MIB_COUNTER_ID_TX_DEFFERED = 0x1B,
3093 MIB_COUNTER_ID_TX_TOT_COL = 0x1C,
3094 MIB_COUNTER_ID_TX_EXCESS_COL= 0x1D,
3095 MIB_COUNTER_ID_TX_ONE_COL = 0x1E,
3096 MIB_COUNTER_ID_TX_MULT_COL = 0x1F,
3097 MIB_COUNTER_ID_RX_BYTES = 0x80,
3098 MIB_COUNTER_ID_TX_BYTES = 0x81,
3099 MIB_COUNTER_ID_RX_DROPPED = 0x82,
3100 MIB_COUNTER_ID_TX_DROPPED = 0x83,
3101 };
3102
3103 inline uint32_t MIB_COUNTER_HI(uint32_t _x)
3104 { return (((_x) << MIB_COUNTER_HI_Pos) & MIB_COUNTER_HI_Msk); }
3105 inline uint32_t MIB_INDEX(uint32_t _x)
3106 { return (((_x) << MIB_INDEX_Pos) & MIB_INDEX_Msk); }
3107
3108}
3109
3110namespace PORT_ACL_ACCESS {
3111 enum {
3112 MAC_ADDR_4_Pos = 0,
3113 MAC_ADDR_4_Msk = (0xFF << MAC_ADDR_4_Pos),
3114 MAC_ADDR_5_Pos = 8,
3115 MAC_ADDR_5_Msk = (0xFF << MAC_ADDR_5_Pos),
3116 COMP_MATCH_Pos = 16,
3117 COMP_MATCH_Msk = (0x1 << COMP_MATCH_Pos),
3118 COMP_MATCH_EQUAL = (0x1 << COMP_MATCH_Pos),
3119 COMP_MATCH_NOT_EQUAL = (0x0 << COMP_MATCH_Pos),
3120 SRC_DEST_Pos = 17,
3121 SRC_DEST_Msk = (0x1 << SRC_DEST_Pos),
3122 SRC_DEST_SRC = (0x1 << SRC_DEST_Pos),
3123 SRC_DEST_DEST = (0x0 << COMP_MATCH_Pos),
3124 ENABLE_Pos = 18,
3125 ENABLE_Msk = (0x3 << ENABLE_Pos),
3126 MODE_Pos = 18,
3127 MODE_Msk = (0x3 << MODE_Pos),
3128 MODE_NO_ACTION = (0x0 << MODE_Pos),
3129 MODE_L2_MAC_HDR = (0x1 << MODE_Pos),
3130 MODE_L3_IP_ADDR = (0x2 << MODE_Pos),
3131 MODE_L4_TPORT_IPROT = (0x3 << MODE_Pos),
3132 FIRST_RULE_NUM_Pos = 24,
3133 FIRST_RULE_NUM_Msk = (0xF << FIRST_RULE_NUM_Pos),
3134 };
3135
3136 inline uint32_t MAC_ADDR_4(uint32_t _x)
3137 { return (((_x) << MAC_ADDR_4_Pos) & MAC_ADDR_4_Msk); }
3138 inline uint32_t MAC_ADDR_5(uint32_t _x)
3139 { return (((_x) << MAC_ADDR_5_Pos) & MAC_ADDR_5_Msk); }
3140 inline uint32_t ENABLE(uint32_t _x)
3141 { return (((_x) << ENABLE_Pos) & ENABLE_Msk); }
3142 inline uint32_t FIRST_RULE_NUM(uint32_t _x)
3143 { return (((_x) << FIRST_RULE_NUM_Pos) & FIRST_RULE_NUM_Msk); }
3144
3145}
3146namespace PORT_ACL_ACCESS2 {
3147 enum {
3148 MAC_ADDR_0_Pos = 0,
3149 MAC_ADDR_0_Msk = (0xFF << MAC_ADDR_0_Pos),
3150 MAC_ADDR_1_Pos = 8,
3151 MAC_ADDR_1_Msk = (0xFF << MAC_ADDR_1_Pos),
3152 MAC_ADDR_2_Pos = 16,
3153 MAC_ADDR_2_Msk = (0xFF << MAC_ADDR_2_Pos),
3154 MAC_ADDR_3_Pos = 24,
3155 MAC_ADDR_3_Msk = (0xFF << MAC_ADDR_3_Pos),
3156 };
3157
3158 inline uint32_t MAC_ADDR_0(uint32_t _x)
3159 { return (((_x) << MAC_ADDR_0_Pos) & MAC_ADDR_0_Msk); }
3160 inline uint32_t MAC_ADDR_1(uint32_t _x)
3161 { return (((_x) << MAC_ADDR_1_Pos) & MAC_ADDR_1_Msk); }
3162 inline uint32_t MAC_ADDR_2(uint32_t _x)
3163 { return (((_x) << MAC_ADDR_2_Pos) & MAC_ADDR_2_Msk); }
3164 inline uint32_t MAC_ADDR_3(uint32_t _x)
3165 { return (((_x) << MAC_ADDR_3_Pos) & MAC_ADDR_3_Msk); }
3166
3167}
3168namespace PORT_ACL_ACCESS3 {
3169 enum {
3170 MAP_MODE_Pos = 5,
3171 MAP_MODE_Msk = (0x3 << MAP_MODE_Pos),
3172 REMARK_PRIO_Pos = 7,
3173 REMARK_PRIO_Msk = (0x7 << REMARK_PRIO_Pos),
3174 REMARK_PRIO_ENABLE_Pos = 10,
3175 REMARK_PRIO_ENABLE_Msk = (0x1 << REMARK_PRIO_ENABLE_Pos),
3176 REMARK_PRIO_ENABLE_ENABLED = (0x1 << REMARK_PRIO_ENABLE_Pos),
3177 REMARK_PRIO_ENABLE_DISABLED = (0x0 << REMARK_PRIO_ENABLE_Pos),
3178 PRIORITY_Pos = 11,
3179 PRIORITY_Msk = (0x7 << PRIORITY_Pos),
3180 PRIO_MODE_Pos = 14,
3181 PRIO_MODE_Msk = (0x3 << PRIO_MODE_Pos),
3182 ETHER_TYPE_Pos = 16,
3183 ETHER_TYPE_Msk = (0xFFFF << ETHER_TYPE_Pos),
3184 };
3185
3186 inline uint32_t MAP_MODE(uint32_t _x)
3187 { return (((_x) << MAP_MODE_Pos) & MAP_MODE_Msk); }
3188 inline uint32_t REMARK_PRIO(uint32_t _x)
3189 { return (((_x) << REMARK_PRIO_Pos) & REMARK_PRIO_Msk); }
3190 inline uint32_t PRIORITY(uint32_t _x)
3191 { return (((_x) << PRIORITY_Pos) & PRIORITY_Msk); }
3192 inline uint32_t PRIO_MODE(uint32_t _x)
3193 { return (((_x) << PRIO_MODE_Pos) & PRIO_MODE_Msk); }
3194 inline uint32_t ETHER_TYPE(uint32_t _x)
3195 { return (((_x) << ETHER_TYPE_Pos) & ETHER_TYPE_Msk); }
3196
3197}
3198namespace PORT_ACL_ACCESS4 {
3199 enum {
3200 RULESET_Pos = 0,
3201 RULESET_Msk = (0xFFFF << RULESET_Pos),
3202 FORWARD_MAP_Pos = 16,
3203 FORWARD_MAP_Msk = (0xFF << FORWARD_MAP_Pos),
3204 };
3205
3206 inline uint32_t RULESET(uint32_t _x)
3207 { return (((_x) << RULESET_Pos) & RULESET_Msk); }
3208 inline uint32_t FORWARD_MAP(uint32_t _x)
3209 { return (((_x) << FORWARD_MAP_Pos) & FORWARD_MAP_Msk); }
3210
3211}
3212namespace PORT_ACL_EN_CTRL {
3213 enum {
3214 ACL_IDX_Pos = 8,
3215 ACL_IDX_Msk = (0xF << ACL_IDX_Pos),
3216 RW_Pos = 12,
3217 RW_Msk = (0x1 << RW_Pos),
3218 RW_WRITE = (0x1 << RW_Pos),
3219 RW_READ = (0x0 << RW_Pos),
3220 RD_STATUS_Pos = 13,
3221 RD_STATUS_Msk = (0x1 << RD_STATUS_Pos),
3222 RD_STATUS_COMPLETE = (0x1 << RD_STATUS_Pos),
3223 RD_STATUS_IN_PROGRESS = (0x0 << RD_STATUS_Pos),
3224 WR_STATUS_Pos = 14,
3225 WR_STATUS_Msk = (0x1 << WR_STATUS_Pos),
3226 WR_STATUS_COMPLETE = (0x1 << WR_STATUS_Pos),
3227 WR_STATUS_IN_PROGRESS = (0x0 << WR_STATUS_Pos),
3228 BYTE_EN_MAP_Pos = 16,
3229 BYTE_EN_MAP_Msk = (0xFFFF << BYTE_EN_MAP_Pos),
3230 };
3231
3232 inline uint32_t ACL_IDX(uint32_t _x)
3233 { return (((_x) << ACL_IDX_Pos) & ACL_IDX_Msk); }
3234 inline uint32_t BYTE_EN_MAP(uint32_t _x)
3235 { return (((_x) << BYTE_EN_MAP_Pos) & BYTE_EN_MAP_Msk); }
3236
3237}
3238
3239namespace PORT_MIRROR_CTRL {
3240 enum {
3241 SNIFFER_PORT_Pos = 1,
3242 SNIFFER_PORT_Msk = (0x1 << SNIFFER_PORT_Pos),
3243 SNIFFER_PORT_THIS_PORT = (0x1 << SNIFFER_PORT_Pos),
3244 SNIFFER_PORT_NOT_THIS_PORT = (0x0 << SNIFFER_PORT_Pos),
3245 TX_SNIFF_Pos = 5,
3246 TX_SNIFF_Msk = (0x1 << TX_SNIFF_Pos),
3247 TX_SNIFF_ENABLED = (0x1 << TX_SNIFF_Pos),
3248 TX_SNIFF_DISABLED = (0x0 << TX_SNIFF_Pos),
3249 RX_SNIFF_Pos = 6,
3250 RX_SNIFF_Msk = (0x1 << RX_SNIFF_Pos),
3251 RX_SNIFF_ENABLED = (0x1 << RX_SNIFF_Pos),
3252 RX_SNIFF_DISABLED = (0x0 << RX_SNIFF_Pos),
3253 };
3254
3255}
3256namespace PORT_PRIO_CTRL {
3257 enum {
3258 ACL_PRIO_CLASS_Pos = 0,
3259 ACL_PRIO_CLASS_Msk = (0x1 << ACL_PRIO_CLASS_Pos),
3260 ACL_PRIO_CLASS_ENABLED = (0x1 << ACL_PRIO_CLASS_Pos),
3261 ACL_PRIO_CLASS_DISABLED = (0x0 << ACL_PRIO_CLASS_Pos),
3262 DIFFSERV_PRIO_CLASS_Pos = 1,
3263 DIFFSERV_PRIO_CLASS_Msk = (0x1 << DIFFSERV_PRIO_CLASS_Pos),
3264 DIFFSERV_PRIO_CLASS_ENABLED = (0x1 << DIFFSERV_PRIO_CLASS_Pos),
3265 DIFFSERV_PRIO_CLASS_DISABLED = (0x0 << DIFFSERV_PRIO_CLASS_Pos),
3266 _802_1P_PRIO_CLASS_Pos = 2,
3267 _802_1P_PRIO_CLASS_Msk = (0x1 << _802_1P_PRIO_CLASS_Pos),
3268 _802_1P_PRIO_CLASS_ENABLED = (0x1 << _802_1P_PRIO_CLASS_Pos),
3269 _802_1P_PRIO_CLASS_DISABLED = (0x0 << _802_1P_PRIO_CLASS_Pos),
3270 VLAN_PRIO_CLASS_Pos = 2,
3271 VLAN_PRIO_CLASS_Msk = (0x1 << VLAN_PRIO_CLASS_Pos),
3272 VLAN_PRIO_CLASS_ENABLED = (0x1 << VLAN_PRIO_CLASS_Pos),
3273 VLAN_PRIO_CLASS_DISABLED = (0x0 << VLAN_PRIO_CLASS_Pos),
3274 MAC_ADDR_PRIO_CLASS_Pos = 4,
3275 MAC_ADDR_PRIO_CLASS_Msk = (0x1 << MAC_ADDR_PRIO_CLASS_Pos),
3276 MAC_ADDR_PRIO_CLASS_ENABLED = (0x1 << MAC_ADDR_PRIO_CLASS_Pos),
3277 MAC_ADDR_PRIO_CLASS_DISABLED = (0x0 << MAC_ADDR_PRIO_CLASS_Pos),
3278 BOOLEAN_OR_PRIO_Pos = 6,
3279 BOOLEAN_OR_PRIO_Msk = (0x1 << BOOLEAN_OR_PRIO_Pos),
3280 BOOLEAN_OR_PRIO_ENABLED = (0x1 << BOOLEAN_OR_PRIO_Pos),
3281 BOOLEAN_OR_PRIO_DISABLED = (0x0 << BOOLEAN_OR_PRIO_Pos),
3282 HIGHEST_PRIO_Pos = 6,
3283 HIGHEST_PRIO_Msk = (0x1 << HIGHEST_PRIO_Pos),
3284 HIGHEST_PRIO_ENABLED = (0x1 << HIGHEST_PRIO_Pos),
3285 HIGHEST_PRIO_DISABLED = (0x0 << HIGHEST_PRIO_Pos),
3286 };
3287
3288}
3289namespace PORT_IN_MAC_CTRL {
3290 enum {
3291 PORT_DEF_PRIO_CLASS_Pos = 0,
3292 PORT_DEF_PRIO_CLASS_Msk = (0x7 << PORT_DEF_PRIO_CLASS_Pos),
3293 DISCARD_TAGGED_Pos = 3,
3294 DISCARD_TAGGED_Msk = (0x1 << DISCARD_TAGGED_Pos),
3295 DISCARD_TAGGED_ENABLED = (0x1 << DISCARD_TAGGED_Pos),
3296 DISCARD_TAGGED_DISABLED = (0x0 << DISCARD_TAGGED_Pos),
3297 DISCARD_UNTAGGED_Pos = 4,
3298 DISCARD_UNTAGGED_Msk = (0x1 << DISCARD_UNTAGGED_Pos),
3299 DISCARD_UNTAGGED_ENABLED = (0x1 << DISCARD_UNTAGGED_Pos),
3300 DISCARD_UNTAGGED_DISABLED = (0x0 << DISCARD_UNTAGGED_Pos),
3301 USER_PRIO_CEIL_Pos = 7,
3302 USER_PRIO_CEIL_Msk = (0x1 << USER_PRIO_CEIL_Pos),
3303 USER_PRIO_CEIL_ENABLED = (0x1 << USER_PRIO_CEIL_Pos),
3304 USER_PRIO_CEIL_DISABLED = (0x0 << USER_PRIO_CEIL_Pos),
3305 };
3306
3307 inline uint32_t PORT_DEF_PRIO_CLASS(uint32_t _x)
3308 { return (((_x) << PORT_DEF_PRIO_CLASS_Pos) & PORT_DEF_PRIO_CLASS_Msk); }
3309
3310}
3311namespace PORT_AUTH_CTRL {
3312 enum {
3313 AUTH_MODE_Pos = 0,
3314 AUTH_MODE_Msk = (0x3 << AUTH_MODE_Pos),
3315 ACL_Pos = 3,
3316 ACL_Msk = (0x1 << ACL_Pos),
3317 ACL_ENABLED = (0x1 << ACL_Pos),
3318 ACL_DISABLED = (0x0 << ACL_Pos),
3319 };
3320
3321 inline uint32_t AUTH_MODE(uint32_t _x)
3322 { return (((_x) << AUTH_MODE_Pos) & AUTH_MODE_Msk); }
3323
3324}
3325namespace PORT_POINTER {
3326 enum {
3327 QUEUE_Pos = 0,
3328 QUEUE_Msk = (0x3 << QUEUE_Pos),
3329 PORT_IDX_Pos = 16,
3330 PORT_IDX_Msk = (0x7 << PORT_IDX_Pos),
3331 };
3332
3333 inline uint32_t QUEUE(uint32_t _x)
3334 { return (((_x) << QUEUE_Pos) & QUEUE_Msk); }
3335 inline uint32_t PORT_IDX(uint32_t _x)
3336 { return (((_x) << PORT_IDX_Pos) & PORT_IDX_Msk); }
3337
3338}
3339namespace PORT_PRIO_QUEUE_MAP {
3340 enum {
3341 };
3342
3343 inline uint32_t PRIO_Pos(uint32_t _p)
3344 { return ((_p & 0x7)<< 2); }
3345 inline uint32_t PRIO_Msk(uint32_t _p)
3346 { return ((0x3) << ((_p & 0x7)<< 2)); }
3347 inline uint32_t PRIO(uint32_t _p, uint32_t _x)
3348 { return ((_x << PRIO_Pos(_p)) & PRIO_Msk(_p)); }
3349
3350}
3351namespace PORT_POLICE_CTRL {
3352 enum {
3353 POLICE_ENABLE_Pos = 0,
3354 POLICE_ENABLE_Msk = (0x1 << POLICE_ENABLE_Pos),
3355 POLICE_ENABLE_ENABLED = (0x1 << POLICE_ENABLE_Pos),
3356 POLICE_ENABLE_DISABLED = (0x0 << POLICE_ENABLE_Pos),
3357 POLICE_MODE_Pos = 1,
3358 POLICE_MODE_Msk = (0x1 << POLICE_MODE_Pos),
3359 POLICE_MODE_COLORBLIND = (0x1 << POLICE_MODE_Pos),
3360 POLICE_MODE_RACIST = (0x0 << POLICE_MODE_Pos),
3361 DROP_SRP_Pos = 2,
3362 DROP_SRP_Msk = (0x1 << DROP_SRP_Pos),
3363 DROP_SRP_ENABLED = (0x1 << DROP_SRP_Pos),
3364 DROP_SRP_DISABLED = (0x0 << DROP_SRP_Pos),
3365 COLOR_REMAP_Pos = 3,
3366 COLOR_REMAP_Msk = (0x1 << COLOR_REMAP_Pos),
3367 COLOR_REMAP_ENABLED = (0x1 << COLOR_REMAP_Pos),
3368 COLOR_REMAP_DISABLED = (0x0 << COLOR_REMAP_Pos),
3369 COLOR_MARK_Pos = 4,
3370 COLOR_MARK_Msk = (0x1 << COLOR_MARK_Pos),
3371 COLOR_MARK_ENABLED = (0x1 << COLOR_MARK_Pos),
3372 COLOR_MARK_DISABLED = (0x0 << COLOR_MARK_Pos),
3373 NONDSCP_COLOR_Pos = 5,
3374 NONDSCP_COLOR_Msk = (0x3 << NONDSCP_COLOR_Pos),
3375 PORT_BASED_POLICING_Pos = 7,
3376 PORT_BASED_POLICING_Msk = (0x1 << PORT_BASED_POLICING_Pos),
3377 PORT_BASED_POLICING_ENABLED = (0x1 << PORT_BASED_POLICING_Pos),
3378 PORT_BASED_POLICING_DISABLED = (0x0 << PORT_BASED_POLICING_Pos),
3379 PKT_TYPE_Pos = 8,
3380 PKT_TYPE_Msk = (0x3 << PKT_TYPE_Pos),
3381 DROP_ALL_Pos = 10,
3382 DROP_ALL_Msk = (0x1 << DROP_ALL_Pos),
3383 DROP_ALL_ENABLED = (0x1 << DROP_ALL_Pos),
3384 DROP_ALL_DISABLED = (0x0 << DROP_ALL_Pos),
3385 PMON_DROPPED_COLOR_Pos = 11,
3386 PMON_DROPPED_COLOR_Msk = (0x1 << PMON_DROPPED_COLOR_Pos),
3387 PMON_DROPPED_COLOR_ENABLED = (0x1 << PMON_DROPPED_COLOR_Pos),
3388 PMON_DROPPED_COLOR_DISABLED = (0x0 << PMON_DROPPED_COLOR_Pos),
3389 };
3390
3391 inline uint32_t NONDSCP_COLOR(uint32_t _x)
3392 { return (((_x) << NONDSCP_COLOR_Pos) & NONDSCP_COLOR_Msk); }
3393 inline uint32_t PKT_TYPE(uint32_t _x)
3394 { return (((_x) << PKT_TYPE_Pos) & PKT_TYPE_Msk); }
3395
3396}
3397
3398namespace PORT_TX_QUEUE_IDX {
3399 enum {
3400 QUEUE_IDX_Pos = 0,
3401 QUEUE_IDX_Msk = (0x3 << QUEUE_IDX_Pos),
3402 };
3403
3404 inline uint32_t QUEUE_IDX(uint32_t _x)
3405 { return (((_x) << QUEUE_IDX_Pos) & QUEUE_IDX_Msk); }
3406
3407}
3408namespace PORT_TX_QUEUE_PVID {
3409 enum {
3410 PORT_VID_REPLACE_Pos = 0,
3411 PORT_VID_REPLACE_Msk = (0x1 << PORT_VID_REPLACE_Pos),
3412 PORT_VID_REPLACE_ENABLED = (0x1 << PORT_VID_REPLACE_Pos),
3413 PORT_VID_REPLACE_DISABLED = (0x0 << PORT_VID_REPLACE_Pos),
3414 };
3415
3416}
3417namespace PORT_TX_QUEUE_CTRL {
3418 enum {
3419 QUEUE_WEIGHT_4_WRR_Pos = 0,
3420 QUEUE_WEIGHT_4_WRR_Msk = (0x7F << QUEUE_WEIGHT_4_WRR_Pos),
3421 SCHED_MODE_Pos = 14,
3422 SCHED_MODE_Msk = (0x3 << SCHED_MODE_Pos),
3423 };
3424
3425 inline uint32_t QUEUE_WEIGHT_4_WRR(uint32_t _x)
3426 { return (((_x) << QUEUE_WEIGHT_4_WRR_Pos) & QUEUE_WEIGHT_4_WRR_Msk); }
3427 inline uint32_t SCHED_MODE(uint32_t _x)
3428 { return (((_x) << SCHED_MODE_Pos) & SCHED_MODE_Msk); }
3429
3430}
3431
3432
3433namespace PORT_LUE_CTRL {
3434 enum {
3435 SELF_ADDR_FILT_Pos = 3,
3436 SELF_ADDR_FILT_Msk = (0x1 << SELF_ADDR_FILT_Pos),
3437 SELF_ADDR_FILT_ENABLED = (0x1 << SELF_ADDR_FILT_Pos),
3438 SELF_ADDR_FILT_DISABLED = (0x0 << SELF_ADDR_FILT_Pos),
3439 MAC_8021X_Pos = 4,
3440 MAC_8021X_Msk = (0x1 << MAC_8021X_Pos),
3441 MAC_8021X_ENABLED = (0x1 << MAC_8021X_Pos),
3442 MAC_8021X_DISABLED = (0x0 << MAC_8021X_Pos),
3443 DISCARD_NON_PVID_Pos = 5,
3444 DISCARD_NON_PVID_Msk = (0x1 << DISCARD_NON_PVID_Pos),
3445 DISCARD_NON_PVID_ENABLED = (0x1 << DISCARD_NON_PVID_Pos),
3446 DISCARD_NON_PVID_DISABLED = (0x0 << DISCARD_NON_PVID_Pos),
3447 INGRESS_VLAN_FILT_Pos = 6,
3448 INGRESS_VLAN_FILT_Msk = (0x1 << INGRESS_VLAN_FILT_Pos),
3449 INGRESS_VLAN_FILT_ENABLED = (0x1 << INGRESS_VLAN_FILT_Pos),
3450 INGRESS_VLAN_FILT_DISABLED = (0x0 << INGRESS_VLAN_FILT_Pos),
3451 NULL_VID_LOOKUP_Pos = 7,
3452 NULL_VID_LOOKUP_Msk = (0x1 << NULL_VID_LOOKUP_Pos),
3453 NULL_VID_LOOKUP_ENABLED = (0x1 << NULL_VID_LOOKUP_Pos),
3454 NULL_VID_LOOKUP_DISABLED = (0x0 << NULL_VID_LOOKUP_Pos),
3455 };
3456
3457}
3458namespace PORT_MSTP_STATE {
3459 enum {
3460 PORT_LEARNING_Pos = 0,
3461 PORT_LEARNING_Msk = (0x1 << PORT_LEARNING_Pos),
3462 PORT_LEARNING_ENABLED = (0x0 << PORT_LEARNING_Pos),
3463 PORT_LEARNING_DISABLED = (0x1 << PORT_LEARNING_Pos),
3464 PORT_RX_Pos = 1,
3465 PORT_RX_Msk = (0x1 << PORT_RX_Pos),
3466 PORT_RX_ENABLED = (0x1 << PORT_RX_Pos),
3467 PORT_RX_DISABLED = (0x0 << PORT_RX_Pos),
3468 PORT_TX_Pos = 2,
3469 PORT_TX_Msk = (0x1 << PORT_TX_Pos),
3470 PORT_TX_ENABLED = (0x1 << PORT_TX_Pos),
3471 PORT_TX_DISABLED = (0x0 << PORT_TX_Pos),
3472 };
3473}
3474
3475#endif
3476
3477#define REG_CHIP_ID0 0x0000
3478#define REG_CHIP_ID0_size 1
3479#define REG_CHIP_ID1 0x0001
3480#define REG_CHIP_ID1_size 1
3481#define REG_CHIP_ID1_FAMILY_ID 0x95
3482#define REG_CHIP_ID1_FAMILY_ID_94 0x94
3483#define REG_CHIP_ID1_FAMILY_ID_95 0x95
3484#define REG_CHIP_ID1_FAMILY_ID_85 0x85
3485#define REG_CHIP_ID1_FAMILY_ID_98 0x98
3486#define REG_CHIP_ID1_FAMILY_ID_88 0x88
3487#define REG_CHIP_ID2 0x0002
3488#define REG_CHIP_ID2_size 1
3489#define REG_CHIP_ID2_CHIP_ID_63 0x63
3490#define REG_CHIP_ID2_CHIP_ID_66 0x66
3491#define REG_CHIP_ID2_CHIP_ID_67 0x67
3492#define REG_CHIP_ID2_CHIP_ID_77 0x77
3493#define REG_CHIP_ID2_CHIP_ID_93 0x93
3494#define REG_CHIP_ID2_CHIP_ID_96 0x96
3495#define REG_CHIP_ID2_CHIP_ID_97 0x97
3496
3497#define REG_CHIP_ID3 0x0003
3498#define REG_CHIP_ID3_size 1
3499#define REG_CHIP_ID3_SW_REV_Pos 4
3500#define REG_CHIP_ID3_SW_REV_Msk (0xF << REG_CHIP_ID3_SW_REV_Pos)
3501
3502#define REG_PME_CTRL 0x0006
3503#define REG_PME_CTRL_size 1
3504#define REG_PME_CTRL_PME_ENABLE_Pos 0
3505#define REG_PME_CTRL_PME_ENABLE_Msk (0x1 << REG_PME_CTRL_PME_ENABLE_Pos)
3506#define REG_PME_CTRL_PME_ENABLE(_x) ((_x) << REG_PME_CTRL_PME_ENABLE_Pos)
3507#define REG_PME_CTRL_PME_ENABLE_ENABLED (1 << REG_PME_CTRL_PME_ENABLE_Pos)
3508#define REG_PME_CTRL_PME_ENABLE_DISABLED (0 << REG_PME_CTRL_PME_ENABLE_Pos)
3509#define REG_PME_CTRL_PME_POLARITY_Pos 1
3510#define REG_PME_CTRL_PME_POLARITY_Msk (0x1 << REG_PME_CTRL_PME_POLARITY_Pos)
3511#define REG_PME_CTRL_PME_POLARITY(_x) ((_x) << REG_PME_CTRL_PME_POLARITY_Pos)
3512#define REG_PME_CTRL_PME_POLARITY_HIGH (1 << REG_PME_CTRL_PME_POLARITY_Pos)
3513#define REG_PME_CTRL_PME_POLARITY_LOW (0 << REG_PME_CTRL_PME_POLARITY_Pos)
3514
3515#define REG_GLOBAL_OPTIONS 0x000F
3516#define REG_GLOBAL_OPTIONS_size 1
3517
3518#define REG_GLOBAL_INT_STATUS 0x0010
3519#define REG_GLOBAL_INT_STATUS_size 4
3520#define REG_GLOBAL_INT_STATUS_LUE_INT_Pos 31
3521#define REG_GLOBAL_INT_STATUS_LUE_INT_Msk (0x1 << REG_GLOBAL_INT_STATUS_LUE_INT_Pos)
3522#define REG_GLOBAL_INT_STATUS_TRIG_TS_INT_Pos 30
3523#define REG_GLOBAL_INT_STATUS_TRIG_TS_INT_Msk (0x1 << REG_GLOBAL_INT_STATUS_TRIG_TS_INT_Pos)
3524#define REG_GLOBAL_INT_STATUS_ABP_TIMEOUT_INT_Pos 29
3525#define REG_GLOBAL_INT_STATUS_ABP_TIMEOUT_INT_Msk (0x1 << REG_GLOBAL_INT_STATUS_ABP_TIMEOUT_INT_Pos)
3526
3527#define REG_GLOBAL_INT_MASK 0x0014
3528#define REG_GLOBAL_INT_MASK_size 4
3529#define REG_GLOBAL_INT_MASK_LUE_INT_Pos 31
3530#define REG_GLOBAL_INT_MASK_LUE_INT_Msk (0x1 << REG_GLOBAL_INT_MASK_LUE_INT_Pos)
3531#define REG_GLOBAL_INT_MASK_TRIG_TS_INT_Pos 30
3532#define REG_GLOBAL_INT_MASK_TRIG_TS_INT_Msk (0x1 << REG_GLOBAL_INT_MASK_TRIG_TS_INT_Pos)
3533#define REG_GLOBAL_INT_MASK_ABP_TIMEOUT_INT_Pos 29
3534#define REG_GLOBAL_INT_MASK_ABP_TIMEOUT_INT_Msk (0x1 << REG_GLOBAL_INT_MASK_ABP_TIMEOUT_INT_Pos)
3535
3536#define REG_GLOBAL_PORT_INT_STATUS 0x0018
3537#define REG_GLOBAL_PORT_INT_STATUS_size 4
3538#define REG_GLOBAL_PORT_INT_STATUS_PORT(_x) (0x1 << (_x))
3539
3540#define REG_GLOBAL_PORT_INT_MASK 0x001C
3541#define REG_GLOBAL_PORT_INT_MASK_size 4
3542#define REG_GLOBAL_PORT_INT_MASK_PORT(_x) (0x1 << (_x))
3543
3544#define REG_PHY_INT_STATUS 0x0020
3545#define REG_PHY_INT_STATUS_size 4
3546#define REG_PHY_INT_STATUS_PHY(_x) (0x1 << (_x))
3547
3548#define REG_PHY_INT_MASK 0x0024
3549#define REG_PHY_INT_MASK_size 4
3550#define REG_PHY_INT_MASK_PHY(_x) (0x1 << (_x))
3551
3552#define REG_SERIAL_IO_CTRL 0x0100
3553#define REG_SERIAL_IO_CTRL_size 1
3554#define REG_SERIAL_IO_CTRL_SPI_CLOCK_OUT_RISING_EDGE_Pos 0
3555#define REG_SERIAL_IO_CTRL_SPI_CLOCK_OUT_RISING_EDGE_Msk (0x1 << REG_SERIAL_IO_CTRL_SPI_CLOCK_OUT_RISING_EDGE_Pos)
3556#define REG_SERIAL_IO_CTRL_SPI_CLOCK_OUT_RISING_EDGE(_x) (((_x) << REG_SERIAL_IO_CTRL_SPI_CLOCK_OUT_RISING_EDGE_Pos) &REG_SERIAL_IO_CTRL_SPI_CLOCK_OUT_RISING_EDGE_Msk)
3557#define REG_SERIAL_IO_CTRL_SPI_CLOCK_OUT_RISING_EDGE_TRUE (0x1 << REG_SERIAL_IO_CTRL_SPI_CLOCK_OUT_RISING_EDGE_Pos)
3558#define REG_SERIAL_IO_CTRL_SPI_CLOCK_OUT_RISING_EDGE_FALSE (0x1 << REG_SERIAL_IO_CTRL_SPI_CLOCK_OUT_RISING_EDGE_Pos)
3559#define REG_SERIAL_IO_CTRL_SPI_AUTO_EDGE_DETECTION_Pos 1
3560#define REG_SERIAL_IO_CTRL_SPI_AUTO_EDGE_DETECTION_Msk (0x1 << REG_SERIAL_IO_CTRL_SPI_AUTO_EDGE_DETECTION_Pos)
3561#define REG_SERIAL_IO_CTRL_SPI_AUTO_EDGE_DETECTION_ENABLED (0x1 << REG_SERIAL_IO_CTRL_SPI_AUTO_EDGE_DETECTION_Pos)
3562#define REG_SERIAL_IO_CTRL_SPI_AUTO_EDGE_DETECTION_DISABLED (0x0 << REG_SERIAL_IO_CTRL_SPI_AUTO_EDGE_DETECTION_Pos)
3563#define REG_SERIAL_IO_CTRL_SPI_AUTO_EDGE_DETECTION(_x) ((_x) << REG_SERIAL_IO_CTRL_SPI_AUTO_EDGE_DETECTION_Pos)
3564#define REG_SERIAL_IO_CTRL_MIIM_PREAMBLE_SUPPRESSION_Pos 2
3565#define REG_SERIAL_IO_CTRL_MIIM_PREAMBLE_SUPPRESSION_Msk (0x1 << REG_SERIAL_IO_CTRL_MIIM_PREAMBLE_SUPPRESSION_Pos)
3566#define REG_SERIAL_IO_CTRL_MIIM_PREAMBLE_SUPPRESSION_ENABLED (0x1 << REG_SERIAL_IO_CTRL_MIIM_PREAMBLE_SUPPRESSION_Pos)
3567#define REG_SERIAL_IO_CTRL_MIIM_PREAMBLE_SUPPRESSION_DISABLED (0x0 << REG_SERIAL_IO_CTRL_MIIM_PREAMBLE_SUPPRESSION_Pos)
3568#define REG_SERIAL_IO_CTRL_MIIM_PREAMBLE_SUPPRESSION(_x) ((_x) << REG_SERIAL_IO_CTRL_MIIM_PREAMBLE_SUPPRESSION_Pos)
3569
3570#define REG_OUTPUT_CLOCK_CTRL 0x0103
3571#define REG_OUTPUT_CLOCK_CTRL_size 1
3572#define REG_OUTPUT_CLOCK_CTRL_REFCLKO_IS_125MHZ_Pos 0
3573#define REG_OUTPUT_CLOCK_CTRL_REFCLKO_IS_125MHZ_Msk (0x1 << REG_OUTPUT_CLOCK_CTRL_REFCLKO_IS_125MHZ_Pos)
3574#define REG_OUTPUT_CLOCK_CTRL_REFCLKO_IS_125MHZ_TRUE (0x1 << REG_OUTPUT_CLOCK_CTRL_REFCLKO_IS_125MHZ_Pos)
3575#define REG_OUTPUT_CLOCK_CTRL_REFCLKO_IS_125MHZ_FALSE (0x0 << REG_OUTPUT_CLOCK_CTRL_REFCLKO_IS_125MHZ_Pos)
3576#define REG_OUTPUT_CLOCK_CTRL_REFCLKO_IS_125MHZ(_x) ((_x) << REG_OUTPUT_CLOCK_CTRL_REFCLKO_IS_125MHZ_Pos)
3577#define REG_OUTPUT_CLOCK_CTRL_REFCLKO_Pos 1
3578#define REG_OUTPUT_CLOCK_CTRL_REFCLKO_Msk (0x1 << REG_OUTPUT_CLOCK_CTRL_REFCLKO_Pos)
3579#define REG_OUTPUT_CLOCK_CTRL_REFCLKO_ENABLED (0x1 << REG_OUTPUT_CLOCK_CTRL_REFCLKO_Pos)
3580#define REG_OUTPUT_CLOCK_CTRL_REFCLKO_DISABLED (0x0 << REG_OUTPUT_CLOCK_CTRL_REFCLKO_Pos)
3581#define REG_OUTPUT_CLOCK_CTRL_REFCLKO(_x) ((_x) << REG_OUTPUT_CLOCK_CTRL_REFCLKO_Pos)
3582
3583#define REG_IBA_CTRL 0x0104
3584#define REG_IBA_CTRL_size 4
3585#define REG_IBA_CTRL_IBA_FRAME_TPID_Pos 0
3586#define REG_IBA_CTRL_IBA_FRAME_TPID_Msk (0xFFFF << REG_IBA_CTRL_IBA_FRAME_TPID_Pos)
3587#define REG_IBA_CTRL_IBA_FRAME_TPID(_x) ((_x) << REG_IBA_CTRL_IBA_FRAME_TPID_Pos)
3588#define REG_IBA_CTRL_IBA_PORT_Pos 16
3589#define REG_IBA_CTRL_IBA_PORT_Msk (0x7 << REG_IBA_CTRL_IBA_PORT_Pos)
3590#define REG_IBA_CTRL_IBA_PORT(_x) ((_x) << REG_IBA_CTRL_IBA_PORT_Pos)
3591#define REG_IBA_CTRL_IBA_RESP_PRIO_Pos 22
3592#define REG_IBA_CTRL_IBA_RESP_PRIO_Msk (0x3 << REG_IBA_CTRL_IBA_RESP_PRIO_Pos)
3593#define REG_IBA_CTRL_IBA_RESP_PRIO(_x) ((_x) << REG_IBA_CTRL_IBA_RESP_PRIO_Pos)
3594#define REG_IBA_CTRL_IBA_RESET_Pos 29
3595#define REG_IBA_CTRL_IBA_RESET_Msk (0x1 << REG_IBA_CTRL_IBA_RESET_Pos)
3596#define REG_IBA_CTRL_IBA_RESET(_x) ((_x) << REG_IBA_CTRL_IBA_RESET_Pos)
3597#define REG_IBA_CTRL_IBA_DA_MATCH_Pos 30
3598#define REG_IBA_CTRL_IBA_DA_MATCH_Msk (0x1 << REG_IBA_CTRL_IBA_DA_MATCH_Pos)
3599#define REG_IBA_CTRL_IBA_DA_MATCH_ENABLED (0x1 << REG_IBA_CTRL_IBA_DA_MATCH_Pos)
3600#define REG_IBA_CTRL_IBA_DA_MATCH_DISABLED (0x0 << REG_IBA_CTRL_IBA_DA_MATCH_Pos)
3601#define REG_IBA_CTRL_IBA_DA_MATCH(_x) (((_x) << REG_IBA_CTRL_IBA_DA_MATCH_Pos) &REG_IBA_CTRL_IBA_DA_MATCH_Msk)
3602#define REG_IBA_CTRL_IBA_ENABLE_Pos 31
3603#define REG_IBA_CTRL_IBA_ENABLE_Msk (0x1 << REG_IBA_CTRL_IBA_ENABLE_Pos)
3604#define REG_IBA_CTRL_IBA_ENABLE_ENABLED (0x1 << REG_IBA_CTRL_IBA_ENABLE_Pos)
3605#define REG_IBA_CTRL_IBA_ENABLE_DISABLED (0x0 << REG_IBA_CTRL_IBA_ENABLE_Pos)
3606#define REG_IBA_CTRL_IBA_ENABLE(_x) (((_x) << REG_IBA_CTRL_IBA_ENABLE_Pos) &REG_IBA_CTRL_IBA_ENABLE_Msk)
3607
3608#define REG_APB_TIMEOUT 0x0108
3609#define REG_APB_TIMEOUT_size 4
3610#define REG_APB_TIMEOUT_APB_TIMEOUT_ACK_Pos 31
3611#define REG_APB_TIMEOUT_APB_TIMEOUT_ACK_Msk (0x1 << REG_APB_TIMEOUT_APB_TIMEOUT_ACK_Pos)
3612
3613#define REG_IBA_SYNC 0x010C
3614#define REG_IBA_SYNC_size 1
3615
3616#define REG_IO_DRIVE_STRENGTH 0x010D
3617#define REG_IO_DRIVE_STRENGTH_size 1
3618#define REG_IO_DRIVE_STRENGTH_LO_SPEED_DRIVE_STRENGTH_Pos 0
3619#define REG_IO_DRIVE_STRENGTH_LO_SPEED_DRIVE_STRENGTH_Msk (0x7 << REG_IO_DRIVE_STRENGTH_LO_SPEED_DRIVE_STRENGTH_Pos)
3620#define REG_IO_DRIVE_STRENGTH_LO_SPEED_DRIVE_STRENGTH(_x) (((_x) << REG_IO_DRIVE_STRENGTH_LO_SPEED_DRIVE_STRENGTH_Pos) &REG_IO_DRIVE_STRENGTH_LO_SPEED_DRIVE_STRENGTH_Msk)
3621#define REG_IO_DRIVE_STRENGTH_HI_SPEED_DRIVE_STRENGTH_Pos 4
3622#define REG_IO_DRIVE_STRENGTH_HI_SPEED_DRIVE_STRENGTH_Msk (0x7 << REG_IO_DRIVE_STRENGTH_HI_SPEED_DRIVE_STRENGTH_Pos)
3623#define REG_IO_DRIVE_STRENGTH_HI_SPEED_DRIVE_STRENGTH(_x) (((_x) << REG_IO_DRIVE_STRENGTH_HI_SPEED_DRIVE_STRENGTH_Pos) &REG_IO_DRIVE_STRENGTH_HI_SPEED_DRIVE_STRENGTH_Msk)
3624
3625#define REG_IBA_STATUS 0x0110
3626#define REG_IBA_STATUS_size 4
3627#define REG_IBA_STATUS_IBA_CMD_LOC_Pos 0
3628#define REG_IBA_STATUS_IBA_CMD_LOC_Msk (0x7F << REG_IBA_STATUS_IBA_CMD_LOC_Pos)
3629#define REG_IBA_STATUS_IBA_CMD_LOC(_x) (((_x) << REG_IBA_STATUS_IBA_CMD_LOC_Pos) &REG_IBA_STATUS_IBA_CMD_LOC_Msk)
3630#define REG_IBA_STATUS_IBA_OVERSIZE_ERROR_Pos 10
3631#define REG_IBA_STATUS_IBA_OVERSIZE_ERROR_Msk (0x1 << REG_IBA_STATUS_IBA_OVERSIZE_ERROR_Pos)
3632#define REG_IBA_STATUS_IBA_CMD_ERROR_Pos 11
3633#define REG_IBA_STATUS_IBA_CMD_ERROR_Msk (0x1 << REG_IBA_STATUS_IBA_CMD_ERROR_Pos)
3634#define REG_IBA_STATUS_IBA_CODE_ERROR_Pos 12
3635#define REG_IBA_STATUS_IBA_CODE_ERROR_Msk (0x1 << REG_IBA_STATUS_IBA_CMD_ERROR_Pos)
3636#define REG_IBA_STATUS_IBA_FMT_MISMATCH_Pos 13
3637#define REG_IBA_STATUS_IBA_FMT_MISMATCH_Msk (0x1 << REG_IBA_STATUS_IBA_FMT_MISMATCH_Pos)
3638#define REG_IBA_STATUS_IBA_DA_MISMATCH_Pos 14
3639#define REG_IBA_STATUS_IBA_DA_MISMATCH_Msk (0x1 << REG_IBA_STATUS_IBA_DA_MISMATCH_Pos)
3640#define REG_IBA_STATUS_IBA_EXEC_DONE_Pos 29
3641#define REG_IBA_STATUS_IBA_EXEC_DONE_Msk (0x1 << REG_IBA_STATUS_IBA_EXEC_DONE_Pos)
3642#define REG_IBA_STATUS_IBA_RESP_Pos 30
3643#define REG_IBA_STATUS_IBA_RESP_Msk (0x1 << REG_IBA_STATUS_IBA_RESP_Pos)
3644#define REG_IBA_STATUS_IBA_REQ_Pos 31
3645#define REG_IBA_STATUS_IBA_REQ_Msk (0x1 << REG_IBA_STATUS_IBA_REQ_Pos)
3646
3647#define REG_IBA_STATES 0x0114
3648#define REG_IBA_STATES_size 4
3649#define REG_IBA_STATES_IBA_FMT_ID_Pos 0
3650#define REG_IBA_STATES_IBA_FMT_ID_Msk (0xFFFF << REG_IBA_STATES_IBA_FMT_ID_Pos)
3651#define REG_IBA_STATES_IBA_PACKET_SIZE_Pos 16
3652#define REG_IBA_STATES_IBA_PACKET_SIZE_Msk (0x7F << REG_IBA_STATUS_IBA_PACKET_SIZE_Pos)
3653#define REG_IBA_STATES_IBA_RESP_STATE_Pos 26
3654#define REG_IBA_STATES_IBA_RESP_STATE_Msk (0x3 << REG_IBA_STATES_IBA_RESP_STATE_Pos)
3655#define REG_IBA_STATES_IBA_CMD_STATE_Pos 28
3656#define REG_IBA_STATES_IBA_CMD_STATE_Msk (0x3 << REG_IBA_STATES_IBA_CMD_STATE_Pos)
3657#define REG_IBA_STATES_IBA_BUF_STATE_Pos 30
3658#define REG_IBA_STATES_IBA_BUF_STATE_Msk (0x3 << REG_IBA_STATES_IBA_BUF_STATE_Pos)
3659
3660
3661#define REG_IBA_RESULT 0x0118
3662#define REG_IBA_RESULT_size 4
3663#define REG_IBA_RESULT_IBA_RETRY_CNT_Pos 0
3664#define REG_IBA_RESULT_IBA_RETRY_CNT_Msk (0x3F << REG_IBA_RESULT_IBA_RETRY_CNT_Pos)
3665#define REG_IBA_RESULT_IBA_SIZE_Pos 24
3666#define REG_IBA_RESULT_IBA_SIZE_Msk (0xFF << REG_IBA_RESULT_IBA_SIZE_Pos)
3667
3668#define REG_LED_OVERRIDE 0x0120
3669#define REG_LED_OVERRIDE_size 4
3670#define REG_LED_OVERRIDE_LED_GPO(_x) (1 << (_x))
3671
3672#define REG_LED_OUTPUT 0x0124
3673#define REG_LED_OUTPUT_size 4
3674#define REG_LED_OUTPUT_HIGH(_x) (1 << (_x))
3675
3676#define REG_POWER_MANAGEMENT_CTRL 0x0201
3677#define REG_POWER_MANAGEMENT_CTRL_size 1
3678#define REG_POWER_MANAGEMENT_CTRL_MODE_Pos 3
3679#define REG_POWER_MANAGEMENT_CTRL_MODE_Msk (0x3 << REG_POWER_MANAGEMENT_CTRL_MODE_Pos)
3680#define REG_POWER_MANAGEMENT_CTRL_MODE_NORMAL (0x0 << REG_POWER_MANAGEMENT_CTRL_MODE_Pos)
3681#define REG_POWER_MANAGEMENT_CTRL_MODE_ENERGY_DETECT_POWER_DOWN (0x1 << REG_POWER_MANAGEMENT_CTRL_MODE_Pos)
3682#define REG_POWER_MANAGEMENT_CTRL_MODE_SOFT_POWER_DOWN (0x2 << REG_POWER_MANAGEMENT_CTRL_MODE_Pos)
3683#define REG_POWER_MANAGEMENT_CTRL_PLL_POWER_DOWN_Pos 5
3684#define REG_POWER_MANAGEMENT_CTRL_PLL_POWER_DOWN_Msk (0x1 << REG_POWER_MANAGEMENT_CTRL_MODE_Pos)
3685#define REG_POWER_MANAGEMENT_CTRL_PLL_POWER_DOWN_NORMAL (0x0 << REG_POWER_MANAGEMENT_CTRL_MODE_Pos)
3686#define REG_POWER_MANAGEMENT_CTRL_PLL_POWER_DOWN_PLL_DISABLED (0x1 << REG_POWER_MANAGEMENT_CTRL_MODE_Pos)
3687
3688#define REG_LED_STRAP 0x0210
3689#define REG_LED_STRAP_size 4
3690
3691
3692#define REG_SW_OPERATION 0x0300
3693#define REG_SW_OPERATION_size 1
3694#define REG_SW_OPERATION_SW_START_Pos 0
3695#define REG_SW_OPERATION_SW_START_Msk (0x1 << REG_SW_OPERATION_SW_START_Pos)
3696#define REG_SW_OPERATION_SW_START_ENABLED (0x1 << REG_SW_OPERATION_SW_START_Pos)
3697#define REG_SW_OPERATION_SW_START_DISABLED (0x1 << REG_SW_OPERATION_SW_START_Pos)
3698#define REG_SW_OPERATION_SW_RESET_Pos 1
3699#define REG_SW_OPERATION_SW_RESET_Msk (0x1 << REG_SW_OPERATION_SW_RESET_Pos)
3700#define REG_SW_OPERATION_SW_RESET_RESET (0x1 << REG_SW_OPERATION_SW_RESET_Pos)
3701#define REG_SW_OPERATION_SW_DOUBLE_TAG_Pos 2
3702#define REG_SW_OPERATION_SW_DOUBLE_TAG_Msk (0x1 << REG_SW_OPERATION_SW_DOUBLE_TAG_Pos)
3703#define REG_SW_OPERATION_SW_DOUBLE_TAG_ENABLED (0x1 << REG_SW_OPERATION_SW_DOUBLE_TAG_Pos)
3704#define REG_SW_OPERATION_SW_DOUBLE_TAG_DISABLED (0x0 << REG_SW_OPERATION_SW_DOUBLE_TAG_Pos)
3705
3706#define REG_SW_MAC_ADDR_0 0x0302
3707#define REG_SW_MAC_ADDR_0_size 1
3708#define REG_SW_MAC_ADDR_1 0x0303
3709#define REG_SW_MAC_ADDR_1_size 1
3710#define REG_SW_MAC_ADDR_2 0x0304
3711#define REG_SW_MAC_ADDR_2_size 1
3712#define REG_SW_MAC_ADDR_3 0x0305
3713#define REG_SW_MAC_ADDR_3_size 1
3714#define REG_SW_MAC_ADDR_4 0x0306
3715#define REG_SW_MAC_ADDR_4_size 1
3716#define REG_SW_MAC_ADDR_5 0x0307
3717#define REG_SW_MAC_ADDR_5_size 1
3718
3719#define REG_SW_MTU 0x0308
3720#define REG_SW_MTU_size 2
3721#define REG_SW_MTU_MTU_Pos 0
3722#define REG_SW_MTU_MTU_Msk (0x3FFF << REG_SW_MTU_MTU_Pos)
3723#define REG_SW_MTU_MTU(_x) (((_x) << REG_SW_MTU_MTU_Pos) &REG_SW_MTU_MTU_Msk)
3724
3725#define REG_SW_ISP_TPID 0x030A
3726#define REG_SW_ISP_TPID_size 2
3727#define REG_SW_ISP_TPID_ISP_TPID_Pos 0
3728#define REG_SW_ISP_TPID_ISP_TPID_Msk (0xFFFF << REG_SW_ISP_TPID_ISP_TPID_Pos)
3729#define REG_SW_ISP_TPID_ISP_TPID(_x) (((_x) << REG_SW_ISP_TPID_ISP_TPID_Pos) &REG_SW_ISP_TPID_ISP_TPID_Msk)
3730
3731
3732#define REG_SW_HSR_TPID 0x030C
3733#define REG_SW_HSR_TPID_size 2
3734#define REG_SW_HSR_TPID_HSR_TPID_Pos 0
3735#define REG_SW_HSR_TPID_HSR_TPID_Msk (0xFFFF << REG_SW_HSR_TPID_HSR_TPID_Pos)
3736#define REG_SW_HSR_TPID_ISP_TPID(_x) (((_x) << REG_SW_HSR_TPID_HSR_TPID_Pos) & REG_SW_HSR_TPID_HSR_TPID_Msk)
3737
3738#define REG_SW_AVB_STRATEGY 0x030E
3739#define REG_SW_AVB_STRATEGY_size 2
3740#define REG_SW_AVB_STRATEGY_POLICING_CREDIT_ACCT_Pos 0
3741#define REG_SW_AVB_STRATEGY_POLICING_CREDIT_ACCT_Msk (0x1 << REG_SW_AVB_STRATEGY_POLICING_CREDIT_ACCT_Pos)
3742#define REG_SW_AVB_STRATEGY_SHAPING_CREDIT_ACCT_Pos 1
3743#define REG_SW_AVB_STRATEGY_SHAPING_CREDIT_ACCT_Msk (0x1 << REG_SW_AVB_STRATEGY_SHAPING_CREDIT_ACCT_Pos)
3744
3745
3746#define REG_SW_LUE_CTRL 0x0310
3747#define REG_SW_LUE_CTRL_size 4
3748#define REG_SW_LUE_CTRL_AGE_PERIOD_Pos 0
3749#define REG_SW_LUE_CTRL_AGE_PERIOD_Msk (0xFF << REG_SW_LUE_CTRL_AGE_PERIOD_Pos)
3750#define REG_SW_LUE_CTRL_AGE_PERIOD(_x) (((_x) << REG_SW_LUE_CTRL_AGE_PERIOD_Pos) & REG_SW_LUE_CTRL_AGE_PERIOD_Msk)
3751
3752#define REG_SW_LUE_CTRL_PRIO_Pos 8
3753#define REG_SW_LUE_CTRL_PRIO_Msk (0x3 << REG_SW_LUE_CTRL_PRIO_Pos)
3754#define REG_SW_LUE_CTRL_PRIO_DST_ADDR (0x0 << REG_SW_LUE_CTRL_PRIO_Pos)
3755#define REG_SW_LUE_CTRL_PRIO_SRC_ADDR (0x1 << REG_SW_LUE_CTRL_PRIO_Pos)
3756#define REG_SW_LUE_CTRL_PRIO_HIGHEST_DA_SA (0x2 << REG_SW_LUE_CTRL_PRIO_Pos)
3757#define REG_SW_LUE_CTRL_PRIO_LOWEST_DA_SA (0x3 << REG_SW_LUE_CTRL_PRIO_Pos)
3758#define REG_SW_LUE_CTRL_FLUSH_OPTION_Pos 10
3759#define REG_SW_LUE_CTRL_FLUSH_OPTION_Msk (0x3 << REG_SW_LUE_CTRL_FLUSH_OPTION_Pos)
3760#define REG_SW_LUE_CTRL_FLUSH_OPTION_NONE (0x0 << REG_SW_LUE_CTRL_FLUSH_OPTION_Pos)
3761#define REG_SW_LUE_CTRL_FLUSH_OPTION_DYN_MAC (0x1 << REG_SW_LUE_CTRL_FLUSH_OPTION_Pos)
3762#define REG_SW_LUE_CTRL_FLUSH_OPTION_STA_MAC (0x2 << REG_SW_LUE_CTRL_FLUSH_OPTION_Pos)
3763#define REG_SW_LUE_CTRL_FLUSH_OPTION_BOTH (0x3 << REG_SW_LUE_CTRL_FLUSH_OPTION_Pos)
3764#define REG_SW_LUE_CTRL_EGRESS_VLAN_FILTER_STA_Pos 12
3765#define REG_SW_LUE_CTRL_EGRESS_VLAN_FILTER_STA_Msk (0x3 << REG_SW_LUE_CTRL_EGRESS_VLAN_FILTER_STA_Pos)
3766#define REG_SW_LUE_CTRL_EGRESS_VLAN_FILTER_STA_ENABLED (0x1 << REG_SW_LUE_CTRL_EGRESS_VLAN_FILTER_STA_Pos)
3767#define REG_SW_LUE_CTRL_EGRESS_VLAN_FILTER_STA_DISABLED (0x0 << REG_SW_LUE_CTRL_EGRESS_VLAN_FILTER_STA_Pos)
3768#define REG_SW_LUE_CTRL_EGRESS_VLAN_FILTER_DYN_Pos 13
3769#define REG_SW_LUE_CTRL_EGRESS_VLAN_FILTER_DYN_Msk (0x1 << REG_SW_LUE_CTRL_EGRESS_VLAN_FILTER_DYN_Pos)
3770#define REG_SW_LUE_CTRL_EGRESS_VLAN_FILTER_DYN_ENABLED (0x1 << REG_SW_LUE_CTRL_EGRESS_VLAN_FILTER_DYN_Pos)
3771#define REG_SW_LUE_CTRL_EGRESS_VLAN_FILTER_DYN_DISABLED (0x0 << REG_SW_LUE_CTRL_EGRESS_VLAN_FILTER_DYN_Pos)
3772#define REG_SW_LUE_CTRL_TRAP_DOUBLE_TAG_Pos 14
3773#define REG_SW_LUE_CTRL_TRAP_DOUBLE_TAG_Msk (0x1 << REG_SW_LUE_CTRL_TRAP_DOUBLE_TAG_Pos)
3774#define REG_SW_LUE_CTRL_TRAP_DOUBLE_TAG_ENABLED (0x1 << REG_SW_LUE_CTRL_TRAP_DOUBLE_TAG_Pos)
3775#define REG_SW_LUE_CTRL_TRAP_DOUBLE_TAG_DISABLED (0x0 << REG_SW_LUE_CTRL_TRAP_DOUBLE_TAG_Pos)
3776
3777#define REG_SW_LUE_CTRL_LINK_DOWN_FLUSH_Pos 16
3778#define REG_SW_LUE_CTRL_LINK_DOWN_FLUSH_Msk (0x1 << REG_SW_LUE_CTRL_LINK_DOWN_FLUSH_Pos)
3779#define REG_SW_LUE_CTRL_LINK_DOWN_FLUSH_ENABLED (0x1 << REG_SW_LUE_CTRL_LINK_DOWN_FLUSH_Pos)
3780#define REG_SW_LUE_CTRL_LINK_DOWN_FLUSH_DISABLED (0x0 << REG_SW_LUE_CTRL_LINK_DOWN_FLUSH_Pos)
3781#define REG_SW_LUE_CTRL_FAST_AGING_Pos 17
3782#define REG_SW_LUE_CTRL_FAST_AGING_Msk (0x1 << REG_SW_LUE_CTRL_FAST_AGING_Pos)
3783#define REG_SW_LUE_CTRL_FAST_AGING_ENABLED (0x1 << REG_SW_LUE_CTRL_FAST_AGING_Pos)
3784#define REG_SW_LUE_CTRL_FAST_AGING_DISABLED (0x0 << REG_SW_LUE_CTRL_FAST_AGING_Pos)
3785#define REG_SW_LUE_CTRL_AGING_Pos 18
3786#define REG_SW_LUE_CTRL_AGING_Msk (0x1 << REG_SW_LUE_CTRL_AGING_Pos)
3787#define REG_SW_LUE_CTRL_AGING_ENABLED (0x1 << REG_SW_LUE_CTRL_AGING_Pos)
3788#define REG_SW_LUE_CTRL_AGING_DISABLED (0x0 << REG_SW_LUE_CTRL_AGING_Pos)
3789#define REG_SW_LUE_CTRL_FWD_MCAST_SRC_ADDR_Pos 19
3790#define REG_SW_LUE_CTRL_FWD_MCAST_SRC_ADDR_Msk (0x1 << REG_SW_LUE_CTRL_FWD_MCAST_SRC_ADDR_Pos)
3791#define REG_SW_LUE_CTRL_FWD_MCAST_SRC_ADDR_ENABLED (0x1 << REG_SW_LUE_CTRL_FWD_MCAST_SRC_ADDR_Pos)
3792#define REG_SW_LUE_CTRL_FWD_MCAST_SRC_ADDR_DISABLED (0x0 << REG_SW_LUE_CTRL_FWD_MCAST_SRC_ADDR_Pos)
3793#define REG_SW_LUE_CTRL_FLUSH_MSTP_TABLE_Pos 20
3794#define REG_SW_LUE_CTRL_FLUSH_MSTP_TABLE_Msk (0x1 << REG_SW_LUE_CTRL_FLUSH_MSTP_TABLE_Pos)
3795#define REG_SW_LUE_CTRL_FLUSH_MSTP_TABLE_ENABLED (0x1 << REG_SW_LUE_CTRL_FLUSH_MSTP_TABLE_Pos)
3796#define REG_SW_LUE_CTRL_FLUSH_MSTP_TABLE_DISABLED (0x0 << REG_SW_LUE_CTRL_FLUSH_MSTP_TABLE_Pos)
3797#define REG_SW_LUE_CTRL_FLUSH_STP_TABLE_Pos 21
3798#define REG_SW_LUE_CTRL_FLUSH_STP_TABLE_Msk (0x1 << REG_SW_LUE_CTRL_FLUSH_STP_TABLE_Pos)
3799#define REG_SW_LUE_CTRL_FLUSH_STP_TABLE_ENABLED (0x1 << REG_SW_LUE_CTRL_FLUSH_STP_TABLE_Pos)
3800#define REG_SW_LUE_CTRL_FLUSH_STP_TABLE_DISABLED (0x0 << REG_SW_LUE_CTRL_FLUSH_STP_TABLE_Pos)
3801#define REG_SW_LUE_CTRL_SRC_ADDR_FILTER_Pos 22
3802#define REG_SW_LUE_CTRL_SRC_ADDR_FILTER_Msk (0x1 << REG_SW_LUE_CTRL_SRC_ADDR_FILTER_Pos)
3803#define REG_SW_LUE_CTRL_SRC_ADDR_FILTER_ENABLED (0x1 << REG_SW_LUE_CTRL_SRC_ADDR_FILTER_Pos)
3804#define REG_SW_LUE_CTRL_SRC_ADDR_FILTER_DISABLED (0x0 << REG_SW_LUE_CTRL_SRC_ADDR_FILTER_Pos)
3805#define REG_SW_LUE_CTRL_UNICAST_LEARN_DISABLE_Pos 23
3806#define REG_SW_LUE_CTRL_UNICAST_LEARN_DISABLE_Msk (0x1 << REG_SW_LUE_CTRL_UNICAST_LEAR_DISABLE_Pos)
3807#define REG_SW_LUE_CTRL_UNICAST_LEARN_DISABLE_ENABLED (0x1 << REG_SW_LUE_CTRL_UNICAST_LEARN_DISABLE_Pos)
3808#define REG_SW_LUE_CTRL_UNICAST_LEARN_DISABLE_DISABLED (0x0 << REG_SW_LUE_CTRL_UNICAST_LEARN_DISABLE_Pos)
3809
3810#define REG_SW_LUE_CTRL_HASH_OPTION_Pos 24
3811#define REG_SW_LUE_CTRL_HASH_OPTION_Msk (0x3 << REG_SW_LUE_CTRL_HASH_OPTION_Pos)
3812#define REG_SW_LUE_CTRL_HASH_OPTION_CRC (0x1 << REG_SW_LUE_CTRL_HASH_OPTION_Pos)
3813#define REG_SW_LUE_CTRL_HASH_OPTION_XOR (0x2 << REG_SW_LUE_CTRL_HASH_OPTION_Pos)
3814#define REG_SW_LUE_CTRL_HASH_OPTION_DIRECT (0x3 << REG_SW_LUE_CTRL_HASH_OPTION_Pos)
3815#define REG_SW_LUE_CTRL_RESV_MCAST_Pos 26
3816#define REG_SW_LUE_CTRL_RESV_MCAST_Msk (0x1 << REG_SW_LUE_CTRL_RESV_MCAST_Pos)
3817#define REG_SW_LUE_CTRL_RESV_MCAST_ENABLED (0x1 << REG_SW_LUE_CTRL_RESV_MCAST_Pos)
3818#define REG_SW_LUE_CTRL_RESV_MCAST_DISABLED (0x0 << REG_SW_LUE_CTRL_RESV_MCAST_Pos)
3819#define REG_SW_LUE_CTRL_AGE_CNT_Pos 27
3820#define REG_SW_LUE_CTRL_AGE_CNT_Msk (0x7 << REG_SW_LUE_CTRL_AGE_CNT_Pos)
3821#define REG_SW_LUE_CTRL_AGE_CNT(_x) (((_x) << REG_SW_LUE_CTRL_AGE_CNT_Pos) &REG_SW_LUE_CTRL_AGE_CNT_Msk)
3822#define REG_SW_LUE_CTRL_DROP_INVALID_VID_Pos 30
3823#define REG_SW_LUE_CTRL_DROP_INVALID_VID_Msk (0x1 << REG_SW_LUE_CTRL_DROP_INVALID_VID_Pos)
3824#define REG_SW_LUE_CTRL_DROP_INVALID_VID_ENABLED (0x1 << REG_SW_LUE_CTRL_DROP_INVALID_VID_Pos)
3825#define REG_SW_LUE_CTRL_DROP_INVALID_VID_DISABLED (0x0 << REG_SW_LUE_CTRL_DROP_INVALID_VID_Pos)
3826#define REG_SW_LUE_CTRL_VLAN_ENABLE_Pos 31
3827#define REG_SW_LUE_CTRL_VLAN_ENABLE_Msk (0x1 << REG_SW_LUE_CTRL_VLAN_ENABLE_Pos)
3828#define REG_SW_LUE_CTRL_VLAN_ENABLE_ENABLED (0x1 << REG_SW_LUE_CTRL_VLAN_ENABLE_Pos)
3829#define REG_SW_LUE_CTRL_VLAN_ENABLE_DISABLED (0x0 << REG_SW_LUE_CTRL_VLAN_ENABLE_Pos)
3830
3831
3832#define REG_SW_LUE_INT_STATUS 0x0314
3833#define REG_SW_LUE_INT_STATUS_size 1
3834#define REG_SW_LUE_INT_STATUS_WRITE_FAIL_Pos 0
3835#define REG_SW_LUE_INT_STATUS_WRITE_FAIL_Msk (0x1 << REG_SW_LUE_INT_STATUS_WRITE_FAIL_Pos)
3836#define REG_SW_LUE_INT_STATUS_WRITE_FAIL_ENABLED (0x1 << REG_SW_LUE_INT_STATUS_WRITE_FAIL_Pos)
3837#define REG_SW_LUE_INT_STATUS_WRITE_FAIL_DISABLED (0x0 << REG_SW_LUE_INT_STATUS_WRITE_FAIL_Pos)
3838#define REG_SW_LUE_INT_STATUS_ALMOST_FULL_Pos 1
3839#define REG_SW_LUE_INT_STATUS_ALMOST_FULL_Msk (0x1 << REG_SW_LUE_INT_STATUS_ALMOST_FULL_Pos)
3840#define REG_SW_LUE_INT_STATUS_ALMOST_FULL_ENABLED (0x1 << REG_SW_LUE_INT_STATUS_ALMOST_FULL_Pos)
3841#define REG_SW_LUE_INT_STATUS_ALMOST_FULL_DISABLED (0x0 << REG_SW_LUE_INT_STATUS_ALMOST_FULL_Pos)
3842#define REG_SW_LUE_INT_STATUS_LEARN_FAIL_Pos 2
3843#define REG_SW_LUE_INT_STATUS_LEARN_FAIL_Msk (0x1 << REG_SW_LUE_INT_STATUS_LEARN_FAIL_Pos)
3844#define REG_SW_LUE_INT_STATUS_LEARN_FAIL_ENABLED (0x1 << REG_SW_LUE_INT_STATUS_LEARN_FAIL_Pos)
3845#define REG_SW_LUE_INT_STATUS_LEARN_FAIL_DISABLED (0x0 << REG_SW_LUE_INT_STATUS_LEARN_FAIL_Pos)
3846
3847#define REG_SW_LUE_INT_MASK 0x0315
3848#define REG_SW_LUE_INT_MASK_size 1
3849#define REG_SW_LUE_INT_MASK_WRITE_FAIL_Pos 0
3850#define REG_SW_LUE_INT_MASK_WRITE_FAIL_Msk (0x1 << REG_SW_LUE_INT_MASK_WRITE_FAIL_Pos)
3851#define REG_SW_LUE_INT_MASK_WRITE_FAIL_ENABLED (0x0 << REG_SW_LUE_INT_MASK_WRITE_FAIL_Pos)
3852#define REG_SW_LUE_INT_MASK_WRITE_FAIL_DISABLED (0x1 << REG_SW_LUE_INT_MASK_WRITE_FAIL_Pos)
3853#define REG_SW_LUE_INT_MASK_ALMOST_FULL_Pos 1
3854#define REG_SW_LUE_INT_MASK_ALMOST_FULL_Msk (0x1 << REG_SW_LUE_INT_MASK_ALMOST_FULL_Pos)
3855#define REG_SW_LUE_INT_MASK_ALMOST_FULL_ENABLED (0x0 << REG_SW_LUE_INT_MASK_ALMOST_FULL_Pos)
3856#define REG_SW_LUE_INT_MASK_ALMOST_FULL_DISABLED (0x1 << REG_SW_LUE_INT_MASK_ALMOST_FULL_Pos)
3857#define REG_SW_LUE_INT_MASK_LEARN_FAIL_Pos 2
3858#define REG_SW_LUE_INT_MASK_LEARN_FAIL_Msk (0x1 << REG_SW_LUE_INT_MASK_LEARN_FAIL_Pos)
3859#define REG_SW_LUE_INT_MASK_LEARN_FAIL_ENABLED (0x0 << REG_SW_LUE_INT_MASK_LEARN_FAIL_Pos)
3860#define REG_SW_LUE_INT_MASK_LEARN_FAIL_DISABLED (0x1 << REG_SW_LUE_INT_MASK_LEARN_FAIL_Pos)
3861
3862#define REG_SW_LUE_INDEX_WRITE 0x0316
3863#define REG_SW_LUE_INDEX_WRITE_size 2
3864#define REG_SW_LUE_INDEX_WRITE_FAIL_WRITE_ALMOST_FULL_Pos 0
3865#define REG_SW_LUE_INDEX_WRITE_FAIL_WRITE_ALMOST_FULL_Msk (0xFFF << REG_SW_LUE_INDEX_WRITE_FAIL_WRITE_ALMOST_FULL_Pos)
3866
3867#define REG_SW_LUE_INDEX_LEARN 0x0318
3868#define REG_SW_LUE_INDEX_LEARN_size 2
3869#define REG_SW_LUE_INDEX_LEARN_FAIL_LEARN_Pos 0
3870#define REG_SW_LUE_INDEX_LEARN_FAIL_LEARN_Msk (0x3FF << REG_SW_LUE_INDEX_WRITE_FAIL_LEARN_Pos)
3871
3872#define REG_SW_LUE_INDEX_CPU 0x031A
3873#define REG_SW_LUE_INDEX_CPU_size 2
3874#define REG_SW_LUE_INDEX_CPU_CPU_ACCESS_Pos 0
3875#define REG_SW_LUE_INDEX_CPU_CPU_ACCESS_Msk (0x3FF << REG_SW_LUE_INDEX_WRITE_CPU_ACCESS_Pos)
3876
3877
3878#define REG_SW_UNK_UCAST_CTRL 0x0320
3879#define REG_SW_UNK_UCAST_CTRL_size 4
3880#define REG_SW_UNK_UCAST_CTRL_FWD_PORTS_Pos 0
3881#define REG_SW_UNK_UCAST_CTRL_FWD_PORTS_Msk (0xFF << REG_SW_UNK_UCAST_CTRL_FWD_PORTS_Pos)
3882#define REG_SW_UNK_UCAST_CTRL_FWD_PORT(_x) (((_x) << REG_SW_UNK_UCAST_CTRL_FWD_PORTS_Pos) & REG_SW_UNK_UCAST_CTRL_FWD_PORTS_Msk)
3883#define REG_SW_UNK_UCAST_CTRL_FWD_Pos 31
3884#define REG_SW_UNK_UCAST_CTRL_FWD_Msk (0x1 << REG_SW_UNK_UCAST_CTRL_FWD_Pos)
3885#define REG_SW_UNK_UCAST_CTRL_FWD_ENABLED (0x1 << REG_SW_UNK_UCAST_CTRL_FWD_Pos)
3886#define REG_SW_UNK_UCAST_CTRL_FWD_DISABLED (0x0 << REG_SW_UNK_UCAST_CTRL_FWD_Pos)
3887
3888#define REG_SW_UNK_MCAST_CTRL 0x0324
3889#define REG_SW_UNK_MCAST_CTRL_size 4
3890#define REG_SW_UNK_MCAST_CTRL_FWD_PORTS_Pos 0
3891#define REG_SW_UNK_MCAST_CTRL_FWD_PORTS_Msk (0xFF << REG_SW_UNK_MCAST_CTRL_FWD_PORTS_Pos)
3892#define REG_SW_UNK_MCAST_CTRL_FWD_PORT(_x) (((_x) << REG_SW_UNK_MCAST_CTRL_FWD_PORTS_Pos) &REG_SW_UNK_MCAST_CTRL_FWD_PORTS_Msk)
3893#define REG_SW_UNK_MCAST_CTRL_FWD_Pos 31
3894#define REG_SW_UNK_MCAST_CTRL_FWD_Msk (0x1 << REG_SW_UNK_MCAST_CTRL_FWD_Pos)
3895#define REG_SW_UNK_MCAST_CTRL_FWD_ENABLED (0x1 << REG_SW_UNK_MCAST_CTRL_FWD_Pos)
3896#define REG_SW_UNK_MCAST_CTRL_FWD_DISABLED (0x0 << REG_SW_UNK_MCAST_CTRL_FWD_Pos)
3897
3898#define REG_SW_UNK_VID_CTRL 0x0328
3899#define REG_SW_UNK_VID_CTRL_size 4
3900#define REG_SW_UNK_VID_CTRL_FWD_PORTS_Pos 0
3901#define REG_SW_UNK_VID_CTRL_FWD_PORTS_Msk (0xFF << REG_SW_UNK_VID_CTRL_FWD_PORTS_Pos)
3902#define REG_SW_UNK_VID_CTRL_FWD_PORT(_x) (((_x) << REG_SW_UNK_VID_CTRL_FWD_PORTS_Pos) &REG_SW_UNK_VID_CTRL_FWD_PORTS_Msk)
3903#define REG_SW_UNK_VID_CTRL_FWD_Pos 31
3904#define REG_SW_UNK_VID_CTRL_FWD_Msk (0x1 << REG_SW_UNK_VID_CTRL_FWD_Pos)
3905#define REG_SW_UNK_VID_CTRL_FWD_ENABLED (0x1 << REG_SW_UNK_VID_CTRL_FWD_Pos)
3906#define REG_SW_UNK_VID_CTRL_FWD_DISABLED (0x0 << REG_SW_UNK_VID_CTRL_FWD_Pos)
3907
3908#define REG_SW_MAC_CTRL 0x0330
3909#define REG_SW_MAC_CTRL_size 4
3910#define REG_SW_MAC_CTRL_AGGR_BACKOFF_Pos 24
3911#define REG_SW_MAC_CTRL_AGGR_BACKOFF_Msk (0x1 << REG_SW_MAC_CTRL_AGGR_BACKOFF_Pos)
3912#define REG_SW_MAC_CTRL_AGGR_BACKOFF_ENABLED (0x1 << REG_SW_MAC_CTRL_AGGR_BACKOFF_Pos)
3913#define REG_SW_MAC_CTRL_AGGR_BACKOFF_DISABLED (0x0 << REG_SW_MAC_CTRL_AGGR_BACKOFF_Pos)
3914#define REG_SW_MAC_CTRL_PAUSE_UNH_MODE_Pos 25
3915#define REG_SW_MAC_CTRL_PAUSE_UNH_MODE_Msk (0x1 << REG_SW_MAC_CTRL_PAUSE_UNH_MODE_Pos)
3916#define REG_SW_MAC_CTRL_PAUSE_UNH_MODE_DROP_EITHER (0x1 << REG_SW_MAC_CTRL_PAUSE_UNH_MODE_Pos)
3917#define REG_SW_MAC_CTRL_PAUSE_UNH_MODE_DROP_BOTH (0x0 << REG_SW_MAC_CTRL_PAUSE_UNH_MODE_Pos)
3918#define REG_SW_MAC_CTRL_CHECK_LENGTH_Pos 27
3919#define REG_SW_MAC_CTRL_CHECK_LENGTH_Msk (0x1 << REG_SW_MAC_CTRL_CHECK_LENGTH_Pos)
3920#define REG_SW_MAC_CTRL_CHECK_LENGTH_ENABLED (0x1 << REG_SW_MAC_CTRL_CHECK_LENGTH_Pos)
3921#define REG_SW_MAC_CTRL_CHECK_LENGTH_DISABLED (0x0 << REG_SW_MAC_CTRL_CHECK_LENGTH_Pos)
3922#define REG_SW_MAC_CTRL_NEW_BACKOFF_Pos 31
3923#define REG_SW_MAC_CTRL_NEW_BACKOFF_Msk (0x1 << REG_SW_MAC_CTRL_NEW_BACKOFF_Pos)
3924#define REG_SW_MAC_CTRL_NEW_BACKOFF_ENABLED (0x1 << REG_SW_MAC_CTRL_NEW_BACKOFF_Pos)
3925#define REG_SW_MAC_CTRL_NEW_BACKOFF_DISABLED (0x0 << REG_SW_MAC_CTRL_NEW_BACKOFF_Pos)
3926
3927#define REG_SW_MAC_CTRL_PASS_SHORT_FRAME_Pos 16
3928#define REG_SW_MAC_CTRL_PASS_SHORT_FRAME_Msk (0x1 << REG_SW_MAC_CTRL_PASS_SHORT_FRAME_Pos)
3929#define REG_SW_MAC_CTRL_PASS_SHORT_FRAME_ENABLED (0x1 << REG_SW_MAC_CTRL_PASS_SHORT_FRAME_Pos)
3930#define REG_SW_MAC_CTRL_PASS_SHORT_FRAME_DISABLED (0x0 << REG_SW_MAC_CTRL_PASS_SHORT_FRAME_Pos)
3931#define REG_SW_MAC_CTRL_LEGAL_PACKET_SIZE_CHECK_Pos 17
3932#define REG_SW_MAC_CTRL_LEGAL_PACKET_SIZE_CHECK_Msk (0x1 << REG_SW_MAC_CTRL_LEGAL_PACKET_SIZE_CHECK_Pos)
3933#define REG_SW_MAC_CTRL_LEGAL_PACKET_SIZE_CHECK_ENABLED (0x0 << REG_SW_MAC_CTRL_LEGAL_PACKET_SIZE_CHECK_Pos)
3934#define REG_SW_MAC_CTRL_LEGAL_PACKET_SIZE_CHECK_DISABLED (0x1 << REG_SW_MAC_CTRL_LEGAL_PACKET_SIZE_CHECK_Pos)
3935#define REG_SW_MAC_CTRL_JUMBO_PACKET_Pos 18
3936#define REG_SW_MAC_CTRL_JUMBO_PACKET_Msk (0x1 << REG_SW_MAC_CTRL_JUMBO_PACKET_Pos)
3937#define REG_SW_MAC_CTRL_JUMBO_PACKET_ENABLED (0x1 << REG_SW_MAC_CTRL_JUMBO_PACKET_Pos)
3938#define REG_SW_MAC_CTRL_JUMBO_PACKET_DISABLED (0x0 << REG_SW_MAC_CTRL_JUMBO_PACKET_Pos)
3939#define REG_SW_MAC_CTRL_NO_EXC_COLLISION_DROP_Pos 19
3940#define REG_SW_MAC_CTRL_NO_EXC_COLLISION_DROP_Msk (0x1 << REG_SW_MAC_CTRL_NO_EXC_COLLISION_DROP_Pos)
3941#define REG_SW_MAC_CTRL_NO_EXC_COLLISION_DROP_ENABLED (0x1 << REG_SW_MAC_CTRL_NO_EXC_COLLISION_DROP_Pos)
3942#define REG_SW_MAC_CTRL_NO_EXC_COLLISION_DROP_DISABLED (0x0 << REG_SW_MAC_CTRL_NO_EXC_COLLISION_DROP_Pos)
3943#define REG_SW_MAC_CTRL_FAIR_FLOW_CTRL_Pos 20
3944#define REG_SW_MAC_CTRL_FAIR_FLOW_CTRL_Msk (0x1 << REG_SW_MAC_CTRL_FAIR_FLOW_CTRL_Pos)
3945#define REG_SW_MAC_CTRL_FAIR_FLOW_CTRL_ENABLED (0x1 << REG_SW_MAC_CTRL_FAIR_FLOW_CTRL_Pos)
3946#define REG_SW_MAC_CTRL_FAIR_FLOW_CTRL_DISABLED (0x0 << REG_SW_MAC_CTRL_FAIR_FLOW_CTRL_Pos)
3947#define REG_SW_MAC_CTRL_BACK_PRESSURE_Pos 21
3948#define REG_SW_MAC_CTRL_BACK_PRESSURE_Msk (0x1 << REG_SW_MAC_CTRL_BACK_PRESSURE_Pos)
3949#define REG_SW_MAC_CTRL_BACK_PRESSURE_CARRIER_SENSE (0x1 << REG_SW_MAC_CTRL_BACK_PRESSURE_Pos)
3950#define REG_SW_MAC_CTRL_BACK_PRESSURE_COLLISION (0x0 << REG_SW_MAC_CTRL_BACK_PRESSURE_Pos)
3951#define REG_SW_MAC_CTRL_MCAST_STORM_PROT_Pos 22
3952#define REG_SW_MAC_CTRL_MCAST_STORM_PROT_Msk (0x1 << REG_SW_MAC_CTRL_MCAST_STORM_PROT_Pos)
3953#define REG_SW_MAC_CTRL_MCAST_STORM_PROT_ENABLED (0x0 << REG_SW_MAC_CTRL_MCAST_STORM_PROT_Pos)
3954#define REG_SW_MAC_CTRL_MCAST_STORM_PROT_DISABLED (0x1 << REG_SW_MAC_CTRL_MCAST_STORM_PROT_Pos)
3955
3956#define REG_SW_MAC_CTRL_NULL_VID_REPLACE_Pos 11
3957#define REG_SW_MAC_CTRL_NULL_VID_REPLACE_Msk (0x1 << REG_SW_MAC_CTRL_NULL_VID_REPLACE_Pos)
3958#define REG_SW_MAC_CTRL_NULL_VID_REPLACE_ENABLED (0x1 << REG_SW_MAC_CTRL_NULL_VID_REPLACE_Pos)
3959#define REG_SW_MAC_CTRL_NULL_VID_REPLACE_DISABLED (0x0 << REG_SW_MAC_CTRL_NULL_VID_REPLACE_Pos)
3960#define REG_SW_MAC_CTRL_BCAST_STORM_RATE_Pos 0
3961#define REG_SW_MAC_CTRL_BCAST_STORM_RATE_Msk (0x7FF << REG_SW_MAC_CTRL_BCAST_STORM_RATE_Pos)
3962#define REG_SW_MAC_CTRL_BCAST_STORM_RATE(_x) (((_x) << REG_SW_MAC_CTRL_BCAST_STORM_RATE_Pos &REG_SW_MAC_CTRL_BCAST_STORM_RATE_Msk))
3963#define REG_SW_MAC_CTRL_BCAST_STORM_RATE_DISABLED (0x0 << REG_SW_MAC_CTRL_BCAST_STORM_RATE_Pos)
3964
3965
3966#define REG_SW_MAC_CTRL2 0x0334
3967#define REG_SW_MAC_CTRL2_size 4
3968#define REG_SW_MAC_CTRL2_PASS_PAUSE_Pos 24
3969#define REG_SW_MAC_CTRL2_PASS_PAUSE_Msk (0x1 << REG_SW_MAC_CTRL2_PASS_PAUSE_Pos)
3970#define REG_SW_MAC_CTRL2_PASS_PAUSE_ENABLED (0x1 << REG_SW_MAC_CTRL2_PASS_PAUSE_Pos)
3971#define REG_SW_MAC_CTRL2_PASS_PAUSE_DISABLED (0x0 << REG_SW_MAC_CTRL2_PASS_PAUSE_Pos)
3972#define REG_SW_MAC_CTRL2_INGRESS_RATE_LIMIT_PERIOD_Pos 20
3973#define REG_SW_MAC_CTRL2_INGRESS_RATE_LIMIT_PERIOD_Msk (0x3 << REG_SW_MAC_CTRL2_INGRESS_RATE_LIMIT_PERIOD_Pos)
3974#define REG_SW_MAC_CTRL2_INGRESS_RATE_LIMIT_PERIOD_16MS (0x0 << REG_SW_MAC_CTRL2_INGRESS_RATE_LIMIT_PERIOD_Pos)
3975#define REG_SW_MAC_CTRL2_INGRESS_RATE_LIMIT_PERIOD_64MS (0x1 << REG_SW_MAC_CTRL2_INGRESS_RATE_LIMIT_PERIOD_Pos)
3976#define REG_SW_MAC_CTRL2_INGRESS_RATE_LIMIT_PERIOD_256MS (0x2 << REG_SW_MAC_CTRL2_INGRESS_RATE_LIMIT_PERIOD_Pos)
3977#define REG_SW_MAC_CTRL2_EGRESS_RATE_LIMIT_BY_Pos 19
3978#define REG_SW_MAC_CTRL2_EGRESS_RATE_LIMIT_BY_Msk (0x1 << REG_SW_MAC_CTRL2_EGRESS_RATE_LIMIT_BY_Pos)
3979#define REG_SW_MAC_CTRL2_EGRESS_RATE_LIMIT_BY_QUEUE (0x1 << REG_SW_MAC_CTRL2_EGRESS_RATE_LIMIT_BY_Pos)
3980#define REG_SW_MAC_CTRL2_EGRESS_RATE_LIMIT_BY_PORT (0x0 << REG_SW_MAC_CTRL2_EGRESS_RATE_LIMIT_BY_Pos)
3981#define REG_SW_MAC_CTRL2_MIB_COUNTER_FLUSH_Pos 15
3982#define REG_SW_MAC_CTRL2_MIB_COUNTER_FLUSH_Msk (0x1 << REG_SW_MAC_CTRL2_MIB_COUNTER_FLUSH_Pos)
3983#define REG_SW_MAC_CTRL2_MIB_COUNTER_FLUSH_ENABLED (0x1 << REG_SW_MAC_CTRL2_MIB_COUNTER_FLUSH_Pos)
3984#define REG_SW_MAC_CTRL2_MIB_COUNTER_FLUSH_DISABLED (0x0 << REG_SW_MAC_CTRL2_MIB_COUNTER_FLUSH_Pos)
3985#define REG_SW_MAC_CTRL2_MIB_COUNTER_FREEZE_Pos 14
3986#define REG_SW_MAC_CTRL2_MIB_COUNTER_FREEZE_Msk (0x1 << REG_SW_MAC_CTRL2_MIB_COUNTER_FREEZE_Pos)
3987#define REG_SW_MAC_CTRL2_MIB_COUNTER_FREEZE_ENABLED (0x1 << REG_SW_MAC_CTRL2_MIB_COUNTER_FREEZE_Pos)
3988#define REG_SW_MAC_CTRL2_MIB_COUNTER_FREEZE_DISABLED (0x0 << REG_SW_MAC_CTRL2_MIB_COUNTER_FREEZE_Pos)
3989
3990#define REG_SW_MAC_802_1P_MAP 0x0338
3991#define REG_SW_MAC_802_1P_MAP_size 4
3992#define REG_SW_MAC_802_1P_MAP_PCP_VAL_Pos(_x) (28-((!(_x&1))*4)-(((_x>>1)&0x3)*8))
3993#define REG_SW_MAC_802_1P_MAP_PCP_VAL_Msk(_x) (0xF << REG_SW_MAC_802_1P_MAP_PCP_VAL_Pos(_x))
3994#define REG_SW_MAC_802_1P_MAP_PCP_VAL(_x, _val) (((_val) << REG_SW_MAC_802_1P_MAP_PCP_VAL_Pos(_x) &REG_SW_MAC_802_1P_MAP_PCP_VAL_Msk(_x)))
3995
3996#define REG_SW_MAC_TOS_CTRL 0x033E
3997#define REG_SW_MAC_TOS_CTRL_size 4
3998#define REG_SW_MAC_TOS_CTRL_TOS_DCSP_REMAP_Pos 0
3999#define REG_SW_MAC_TOS_CTRL_TOS_DCSP_REMAP_Msk (0x1 << REG_SW_MAC_TOS_CTRL_TOS_DCSP_REMAP_Pos)
4000#define REG_SW_MAC_TOS_CTRL_TOS_DCSP_REMAP_ENABLED (0x1 << REG_SW_MAC_TOS_CTRL_TOS_DCSP_REMAP_Pos)
4001#define REG_SW_MAC_TOS_CTRL_TOS_DCSP_REMAP_DISABLED (0x0 << REG_SW_MAC_TOS_CTRL_TOS_DCSP_REMAP_Pos)
4002#define REG_SW_MAC_TOS_CTRL_TOS_DCSP_REMARK_Pos 1
4003#define REG_SW_MAC_TOS_CTRL_TOS_DCSP_REMARK_Msk (0x1 << REG_SW_MAC_TOS_CTRL_TOS_DCSP_REMARK_Pos)
4004#define REG_SW_MAC_TOS_CTRL_TOS_DCSP_REMARK_ENABLED (0x1 << REG_SW_MAC_TOS_CTRL_TOS_DCSP_REMARK_Pos)
4005#define REG_SW_MAC_TOS_CTRL_TOS_DCSP_REMARK_DISABLED (0x0 << REG_SW_MAC_TOS_CTRL_TOS_DCSP_REMARK_Pos)
4006
4007#define REG_SW_MAC_TOS_PRIO_0 0x0340
4008#define REG_SW_MAC_TOS_PRIO_0_size 1
4009#define REG_SW_MAC_TOS_PRIO_1 0x0341
4010#define REG_SW_MAC_TOS_PRIO_1_size 1
4011#define REG_SW_MAC_TOS_PRIO_2 0x0342
4012#define REG_SW_MAC_TOS_PRIO_2_size 1
4013#define REG_SW_MAC_TOS_PRIO_3 0x0343
4014#define REG_SW_MAC_TOS_PRIO_3_size 1
4015#define REG_SW_MAC_TOS_PRIO_4 0x0344
4016#define REG_SW_MAC_TOS_PRIO_4_size 1
4017#define REG_SW_MAC_TOS_PRIO_5 0x0345
4018#define REG_SW_MAC_TOS_PRIO_5_size 1
4019#define REG_SW_MAC_TOS_PRIO_6 0x0346
4020#define REG_SW_MAC_TOS_PRIO_6_size 1
4021#define REG_SW_MAC_TOS_PRIO_7 0x0347
4022#define REG_SW_MAC_TOS_PRIO_7_size 1
4023#define REG_SW_MAC_TOS_PRIO_8 0x0348
4024#define REG_SW_MAC_TOS_PRIO_8_size 1
4025#define REG_SW_MAC_TOS_PRIO_9 0x0349
4026#define REG_SW_MAC_TOS_PRIO_9_size 1
4027#define REG_SW_MAC_TOS_PRIO_10 0x034A
4028#define REG_SW_MAC_TOS_PRIO_10_size 1
4029#define REG_SW_MAC_TOS_PRIO_11 0x034B
4030#define REG_SW_MAC_TOS_PRIO_11_size 1
4031#define REG_SW_MAC_TOS_PRIO_12 0x034C
4032#define REG_SW_MAC_TOS_PRIO_12_size 1
4033#define REG_SW_MAC_TOS_PRIO_13 0x034D
4034#define REG_SW_MAC_TOS_PRIO_13_size 1
4035#define REG_SW_MAC_TOS_PRIO_14 0x034E
4036#define REG_SW_MAC_TOS_PRIO_14_size 1
4037#define REG_SW_MAC_TOS_PRIO_15 0x034F
4038#define REG_SW_MAC_TOS_PRIO_15_size 1
4039#define REG_SW_MAC_TOS_PRIO_16 0x0350
4040#define REG_SW_MAC_TOS_PRIO_16_size 1
4041#define REG_SW_MAC_TOS_PRIO_17 0x0351
4042#define REG_SW_MAC_TOS_PRIO_17_size 1
4043#define REG_SW_MAC_TOS_PRIO_18 0x0352
4044#define REG_SW_MAC_TOS_PRIO_18_size 1
4045#define REG_SW_MAC_TOS_PRIO_19 0x0353
4046#define REG_SW_MAC_TOS_PRIO_19_size 1
4047#define REG_SW_MAC_TOS_PRIO_20 0x0354
4048#define REG_SW_MAC_TOS_PRIO_20_size 1
4049#define REG_SW_MAC_TOS_PRIO_21 0x0355
4050#define REG_SW_MAC_TOS_PRIO_21_size 1
4051#define REG_SW_MAC_TOS_PRIO_22 0x0356
4052#define REG_SW_MAC_TOS_PRIO_22_size 1
4053#define REG_SW_MAC_TOS_PRIO_23 0x0357
4054#define REG_SW_MAC_TOS_PRIO_23_size 1
4055#define REG_SW_MAC_TOS_PRIO_24 0x0358
4056#define REG_SW_MAC_TOS_PRIO_24_size 1
4057#define REG_SW_MAC_TOS_PRIO_25 0x0359
4058#define REG_SW_MAC_TOS_PRIO_25_size 1
4059#define REG_SW_MAC_TOS_PRIO_26 0x035A
4060#define REG_SW_MAC_TOS_PRIO_26_size 1
4061#define REG_SW_MAC_TOS_PRIO_27 0x035B
4062#define REG_SW_MAC_TOS_PRIO_27_size 1
4063#define REG_SW_MAC_TOS_PRIO_28 0x035C
4064#define REG_SW_MAC_TOS_PRIO_28_size 1
4065#define REG_SW_MAC_TOS_PRIO_29 0x035D
4066#define REG_SW_MAC_TOS_PRIO_29_size 1
4067#define REG_SW_MAC_TOS_PRIO_30 0x035E
4068#define REG_SW_MAC_TOS_PRIO_30_size 1
4069#define REG_SW_MAC_TOS_PRIO_31 0x035F
4070#define REG_SW_MAC_TOS_PRIO_31_size 1
4071
4072#define REG_SW_MAC_TOS_PRIO_REG(_x) ((_x>>1)&0x1F)
4073#define REG_SW_MAC_TOS_PRIO_DCSP_VAL_Pos(_x) (((_x&1))*4)
4074#define REG_SW_MAC_TOS_PRIO_DCSP_VAL_Msk(_x) (0xF << REG_SW_MAC_TOS_PRIO_DCSP_VAL_Pos(_x))
4075#define REG_SW_MAC_TOS_PRIO_DCSP_VAL(_x, _val) (((_val) << REG_SW_MAC_TOS_PRIO_DCSP_VAL_Pos(_x) &REG_SW_MAC_TOS_PRIO_DCSP_VAL_Msk(_x)))
4076
4077#define REG_SW_MRI_CTRL 0x0370
4078#define REG_SW_MRI_CTRL_size 1
4079#define REG_SW_MRI_CTRL_MIRROR_FILTER_Pos 0
4080#define REG_SW_MRI_CTRL_MIRROR_FILTER_Msk (0x1 << REG_SW_LUE_CTRL2_MIRROR_FILTER_Pos)
4081#define REG_SW_MRI_CTRL_MIRROR_FILTER_AND (0x1 << REG_SW_MRI_CTRL_MIRROR_FILTER_Pos)
4082#define REG_SW_MRI_CTRL_MIRROR_FILTER_OR (0x0 << REG_SW_MRI_CTRL_MIRROR_FILTER_Pos)
4083#define REG_SW_MRI_CTRL_IPV6_MLD_SNOOP_Pos 2
4084#define REG_SW_MRI_CTRL_IPV6_MLD_SNOOP_Msk (0x1 << REG_SW_LUE_CTRL2_IPV6_MLD_SNOOP_Pos)
4085#define REG_SW_MRI_CTRL_IPV6_MLD_SNOOP_ENABLED (0x1 << REG_SW_MRI_CTRL_IPV6_MLD_SNOOP_Pos)
4086#define REG_SW_MRI_CTRL_IPV6_MLD_SNOOP_DISABLED (0x0 << REG_SW_MRI_CTRL_IPV6_MLD_SNOOP_Pos)
4087#define REG_SW_MRI_CTRL_IPV6_MLD_OPTION_Pos 3
4088#define REG_SW_MRI_CTRL_IPV6_MLD_OPTION_Msk (0x1 << REG_SW_LUE_CTRL2_IPV6_MLD_OPTION_Pos)
4089#define REG_SW_MRI_CTRL_IPV6_MLD_OPTION_ENABLED (0x1 << REG_SW_MRI_CTRL_IPV6_MLD_OPTION_Pos)
4090#define REG_SW_MRI_CTRL_IPV6_MLD_OPTION_DISABLED (0x0 << REG_SW_MRI_CTRL_IPV6_MLD_OPTION_Pos)
4091#define REG_SW_MRI_CTRL_IGMP_SNOOP_Pos 6
4092#define REG_SW_MRI_CTRL_IGMP_SNOOP_Msk (0x1 << REG_SW_LUE_CTRL2_IGMP_SNOOP_Pos)
4093#define REG_SW_MRI_CTRL_IGMP_SNOOP_ENABLED (0x1 << REG_SW_MRI_CTRL_IGMP_SNOOP_Pos)
4094#define REG_SW_MRI_CTRL_IGMP_SNOOP_DISABLED (0x0 << REG_SW_MRI_CTRL_IGMP_SNOOP_Pos)
4095
4096#define REG_SW_WRED_DSCP_COLOR 0x0378
4097#define REG_SW_WRED_DSCP_COLOR_size 1
4098#define REG_SW_WRED_DSCP_COLOR_GREEN_Pos 0
4099#define REG_SW_WRED_DSCP_COLOR_GREEN_Msk (0x3 << REG_SW_WRED_DSCP_COLOR_GREEN_Pos)
4100#define REG_SW_WRED_DSCP_COLOR_GREEN(_x) (((_x) << REG_SW_WRED_DSCP_COLOR_GREEN_Pos) &REG_SW_WRED_DSCP_COLOR_GREEN_Msk)
4101#define REG_SW_WRED_DSCP_COLOR_YELLOW_Pos 2
4102#define REG_SW_WRED_DSCP_COLOR_YELLOW_Msk (0x3 << REG_SW_WRED_DSCP_COLOR_YELLOW_Pos)
4103#define REG_SW_WRED_DSCP_COLOR_YELLOW(_x) (((_x) << REG_SW_WRED_DSCP_COLOR_YELLOW_Pos) &REG_SW_WRED_DSCP_COLOR_YELLOW_Msk)
4104#define REG_SW_WRED_DSCP_COLOR_RED_Pos 4
4105#define REG_SW_WRED_DSCP_COLOR_RED_Msk (0x3 << REG_SW_WRED_DSCP_COLOR_RED_Pos)
4106#define REG_SW_WRED_DSCP_COLOR_RED(_x) (((_x) << REG_SW_WRED_DSCP_COLOR_RED_Pos) &REG_SW_WRED_DSCP_COLOR_RED_Msk)
4107#define REG_SW_WRED_DSCP_COLOR_NO_COLOR_Pos 6
4108#define REG_SW_WRED_DSCP_COLOR_NO_COLOR_Msk (0x3 << REG_SW_WRED_DSCP_COLOR_NO_COLOR_Pos)
4109#define REG_SW_WRED_DSCP_COLOR_NO_COLOR(_x) (((_x) << REG_SW_WRED_DSCP_COLOR_NO_COLOR_Pos) &REG_SW_WRED_DSCP_COLOR_NO_COLOR_Msk)
4110
4111#define REG_SW_QM_CTRL 0x0390
4112#define REG_SW_QM_CTRL_size 4
4113#define REG_SW_QM_CTRL_UNICAST_VLAN_BOUNDARY_Pos 1
4114#define REG_SW_QM_CTRL_UNICAST_VLAN_BOUNDARY_Msk (0x1 << REG_SW_QM_CTRL_UNICAST_VLAN_BOUNDARY_Pos)
4115#define REG_SW_QM_CTRL_UNICAST_VLAN_BOUNDARY_ENABLED (0x1 << REG_SW_QM_CTRL_UNICAST_VLAN_BOUNDARY_Pos)
4116#define REG_SW_QM_CTRL_UNICAST_VLAN_BOUNDARY_DISABLED (0x0 << REG_SW_QM_CTRL_UNICAST_VLAN_BOUNDARY_Pos)
4117#define REG_SW_QM_CTRL_PRIO_SCHEME_SELECT_Pos 6
4118#define REG_SW_QM_CTRL_PRIO_SCHEME_SELECT_Msk (0x1 << REG_SW_QM_CTRL_PRIO_SCHEME_SELECT_Pos)
4119#define REG_SW_QM_CTRL_PRIO_SCHEME_SELECT_MAP_3_HI (0x0 << REG_SW_QM_CTRL_PRIO_SCHEME_SELECT_Pos)
4120#define REG_SW_QM_CTRL_PRIO_SCHEME_SELECT_MAP_2_HI (0x2 << REG_SW_QM_CTRL_PRIO_SCHEME_SELECT_Pos)
4121#define REG_SW_QM_CTRL_PRIO_SCHEME_SELECT_MAP_0_LO (0x3 << REG_SW_QM_CTRL_PRIO_SCHEME_SELECT_Pos)
4122
4123#define REG_SW_EEE_TXQ_WAIT_TIME 0x03C2
4124#define REG_SW_EEE_TXQ_WAIT_TIME_size 2
4125
4126#define REG_VLAN_ENTRY 0x0400
4127#define REG_VLAN_ENTRY_size 4
4128#define REG_VLAN_ENTRY_FID_Pos 0
4129#define REG_VLAN_ENTRY_FID_Msk (0x7F << REG_VLAN_ENTRY_FID_Pos)
4130#define REG_VLAN_ENTRY_FID(_x) (((_x) << REG_VLAN_ENTRY_FID_Pos) &REG_VLAN_ENTRY_FID_Msk)
4131#define REG_VLAN_ENTRY_MSTP_INDEX_Pos 12
4132#define REG_VLAN_ENTRY_MSTP_INDEX_Msk (0x7 << REG_VLAN_ENTRY_MSTP_INDEX_Pos)
4133#define REG_VLAN_ENTRY_MSTP_INDEX(_x) (((_x) << REG_VLAN_ENTRY_MSTP_INDEX_Pos) &REG_VLAN_ENTRY_MSTP_INDEX_Msk)
4134#define REG_VLAN_ENTRY_PRIORITY_Pos 24
4135#define REG_VLAN_ENTRY_PRIORITY_Msk (0x7 << REG_VLAN_ENTRY_PRIORITY_Pos)
4136#define REG_VLAN_ENTRY_PRIORITY(_x) (((_x) << REG_VLAN_ENTRY_PRIORITY_Pos) &REG_VLAN_ENTRY_PRIORITY_Msk)
4137#define REG_VLAN_ENTRY_FORWARD_OPTION_Pos 27
4138#define REG_VLAN_ENTRY_FORWARD_OPTION_Msk (0x7 << REG_VLAN_ENTRY_FORWARD_OPTION_Pos)
4139#define REG_VLAN_ENTRY_FORWARD_OPTION_OTHER (0x0 << REG_VLAN_ENTRY_FORWARD_OPTION_Pos)
4140#define REG_VLAN_ENTRY_FORWARD_OPTION_VLAN_MAP (0x1 << REG_VLAN_ENTRY_FORWARD_OPTION_Pos)
4141#define REG_VLAN_ENTRY_VALID_Pos 27
4142#define REG_VLAN_ENTRY_VALID_Msk (0x7 << REG_VLAN_ENTRY_VALID_Pos)
4143#define REG_VLAN_ENTRY_VALID_FALSE (0x0 << REG_VLAN_ENTRY_VALID_Pos)
4144#define REG_VLAN_ENTRY_VALID_TRUE (0x1 << REG_VLAN_ENTRY_VALID_Pos)
4145
4146#define REG_VLAN_UNTAG 0x0404
4147#define REG_VLAN_UNTAG_size 4
4148#define REG_VLAN_UNTAG_PORT(_x) (( 0x1 << (((_x)-1) &0x1F)))
4149
4150#define REG_VLAN_FORWARD 0x0408
4151#define REG_VLAN_FORWARD_size 4
4152#define REG_VLAN_FORWARD_PORT(_x) (( 0x1 << (((_x)-1) &0x1F)))
4153
4154#define REG_VLAN_INDEX 0x040C
4155#define REG_VLAN_INDEX_size 2
4156#define REG_VLAN_INDEX_INDEX_Pos 0
4157#define REG_VLAN_INDEX_INDEX_Msk (0xFFF << REG_VLAN_INDEX_INDEX_Pos)
4158#define REG_VLAN_INDEX_INDEX(_x) (((_x) << REG_VLAN_INDEX_INDEX_Pos) &REG_VLAN_INDEX_INDEX_Msk)
4159
4160#define REG_VLAN_CTRL 0x040E
4161#define REG_VLAN_CTRL_size 2
4162#define REG_VLAN_CTRL_ACTION_Pos 0
4163#define REG_VLAN_CTRL_ACTION_Msk (0x3 << REG_VLAN_CTRL_ACTION_Pos)
4164#define REG_VLAN_CTRL_ACTION_NOP (0x0 << REG_VLAN_CTRL_ACTION_Pos)
4165#define REG_VLAN_CTRL_ACTION_WRITE (0x1 << REG_VLAN_CTRL_ACTION_Pos)
4166#define REG_VLAN_CTRL_ACTION_READ (0x2 << REG_VLAN_CTRL_ACTION_Pos)
4167#define REG_VLAN_CTRL_ACTION_CLEAR (0x3 << REG_VLAN_CTRL_ACTION_Pos)
4168#define REG_VLAN_CTRL_START_ACTION_Pos 0
4169#define REG_VLAN_CTRL_START_ACTION_Msk (0x1 << REG_VLAN_CTRL_START_ACTION_Pos)
4170#define REG_VLAN_CTRL_START_ACTION_START (0x1 << REG_VLAN_CTRL_START_ACTION_Pos)
4171#define REG_VLAN_CTRL_START_ACTION_COMPLETE (0x1 << REG_VLAN_CTRL_START_ACTION_Pos)
4172
4173#define REG_ALU_INDEX 0x0410
4174#define REG_ALU_INDEX_size 4
4175#define REG_ALU_INDEX_MAC_ADDR_HI_Pos 0
4176#define REG_ALU_INDEX_MAC_ADDR_HI_Msk (0xFFFF << REG_ALU_INDEX_MAC_ADDR_HI_Pos)
4177#define REG_ALU_INDEX_MAC_ADDR_HI(_x) (((_x) << REG_ALU_INDEX_MAC_ADDR_HI_Pos) &REG_ALU_INDEX_MAC_ADDR_HI_Msk)
4178#define REG_ALU_INDEX_FID_INDEX_Pos 16
4179#define REG_ALU_INDEX_FID_INDEX_Msk (0x7F << REG_ALU_INDEX_FID_INDEX_Pos)
4180#define REG_ALU_INDEX_FID_INDEX(_x) (((_x) << REG_ALU_INDEX_FID_INDEX_Pos) &REG_ALU_INDEX_FID_INDEX_Msk)
4181
4182#define REG_ALU_INDEX2 0x0414
4183#define REG_ALU_INDEX2_size 4
4184#define REG_ALU_INDEX2_MAC_ADDR_LO_Pos 0
4185#define REG_ALU_INDEX2_MAC_ADDR_LO_Msk (0xFFFFFFFF << REG_ALU_INDEX2_MAC_ADDR_LO_Pos)
4186#define REG_ALU_INDEX2_MAC_ADDR_LO(_x) (((_x) << REG_ALU_INDEX2_MAC_ADDR_LO_Pos) &REG_ALU_INDEX2_MAC_ADDR_LO_Msk)
4187#define REG_ALU_INDEX2_ALU_DIRECT_INDEX_Pos 0
4188#define REG_ALU_INDEX2_ALU_DIRECT_INDEX_Msk (0xFFF << REG_ALU_INDEX2_ALU_DIRECT_INDEX_Pos)
4189#define REG_ALU_INDEX2_ALU_DIRECT_INDEX(_x) (((_x) << REG_ALU_INDEX2_ALU_DIRECT_INDEX_Pos) &REG_ALU_INDEX2_ALU_DIRECT_INDEX_Msk)
4190
4191#define REG_ALU_CTRL 0x0418
4192#define REG_ALU_CTRL_size 4
4193#define REG_ALU_CTRL_ACTION_Pos 0
4194#define REG_ALU_CTRL_ACTION_Msk (0x3 << REG_ALU_CTRL_ACTION_Pos)
4195#define REG_ALU_CTRL_ACTION_NOP (0x0 << REG_ALU_CTRL_ACTION_Pos)
4196#define REG_ALU_CTRL_ACTION_WRITE (0x1 << REG_ALU_CTRL_ACTION_Pos)
4197#define REG_ALU_CTRL_ACTION_READ (0x2 << REG_ALU_CTRL_ACTION_Pos)
4198#define REG_ALU_CTRL_ACTION_SEARCH (0x3 << REG_ALU_CTRL_ACTION_Pos)
4199#define REG_ALU_CTRL_DIRECT_Pos 2
4200#define REG_ALU_CTRL_DIRECT_Msk (0x1 << REG_ALU_CTRL_DIRECT_Pos)
4201#define REG_ALU_CTRL_DIRECT_DIRECT (0x1 << REG_ALU_CTRL_DIRECT_Pos)
4202#define REG_ALU_CTRL_DIRECT_HASHED (0x0 << REG_ALU_CTRL_DIRECT_Pos)
4203#define REG_ALU_CTRL_VALID_OR_STOP_Pos 5
4204#define REG_ALU_CTRL_VALID_OR_STOP_Msk (0x1 << REG_ALU_CTRL_VALID_OR_STOP_Pos)
4205#define REG_ALU_CTRL_VALID_OR_STOP_TRUE (0x1 << REG_ALU_CTRL_VALID_OR_STOP_Pos)
4206#define REG_ALU_CTRL_VALID_OR_STOP_FALSE (0x0 << REG_ALU_CTRL_VALID_OR_STOP_Pos)
4207#define REG_ALU_CTRL_VALID_Pos 6
4208#define REG_ALU_CTRL_VALID_Msk (0x1 << REG_ALU_CTRL_VALID_Pos)
4209#define REG_ALU_CTRL_VALID_TRUE (0x1 << REG_ALU_CTRL_VALID_Pos)
4210#define REG_ALU_CTRL_VALID_FALSE (0x0 << REG_ALU_CTRL_VALID_Pos)
4211#define REG_ALU_CTRL_START_Pos 7
4212#define REG_ALU_CTRL_START_Msk (0x1 << REG_ALU_CTRL_START_Pos)
4213#define REG_ALU_CTRL_START_START (0x1 << REG_ALU_CTRL_START_Pos)
4214#define REG_ALU_CTRL_START_COMPLETE (0x0 << REG_ALU_CTRL_START_Pos)
4215#define REG_ALU_CTRL_VALID_CNT_Pos 0
4216#define REG_ALU_CTRL_VALID_CNT_Msk (0x3FFF << REG_ALU_CTRL_VALID_CNT_Pos)
4217
4218#define REG_ALU_STAT_CTRL 0x041C
4219#define REG_ALU_STAT_CTRL_size 4
4220#define REG_ALU_STAT_CTRL_ACTION_Pos 0
4221#define REG_ALU_STAT_CTRL_ACTION_Msk (0x1 << REG_ALU_STAT_CTRL_ACTION_Pos)
4222#define REG_ALU_STAT_CTRL_ACTION_WRITE (0x0 << REG_ALU_STAT_CTRL_ACTION_Pos)
4223#define REG_ALU_STAT_CTRL_ACTION_READ (0x1 << REG_ALU_STAT_CTRL_ACTION_Pos)
4224#define REG_ALU_STAT_CTRL_TABLE_Pos 1
4225#define REG_ALU_STAT_CTRL_TABLE_Msk (0x1 << REG_ALU_STAT_CTRL_TABLE_Pos)
4226#define REG_ALU_STAT_CTRL_TABLE_STATIC_ADDR (0x0 << REG_ALU_STAT_CTRL_TABLE_Pos)
4227#define REG_ALU_STAT_CTRL_TABLE_STATIC_RESV_MCAST (0x1 << REG_ALU_STAT_CTRL_TABLE_Pos)
4228#define REG_ALU_STAT_CTRL_START_Pos 7
4229#define REG_ALU_STAT_CTRL_START_Msk (0x1 << REG_ALU_STAT_CTRL_START_Pos)
4230#define REG_ALU_STAT_CTRL_START_NOP (0x0 << REG_ALU_STAT_CTRL_START_Pos)
4231#define REG_ALU_STAT_CTRL_START_START (0x1 << REG_ALU_STAT_CTRL_START_Pos)
4232#define REG_ALU_STAT_CTRL_START_COMPLETE (0x0 << REG_ALU_STAT_CTRL_START_Pos)
4233#define REG_ALU_STAT_CTRL_TABLE_INDEX_Pos 16
4234#define REG_ALU_STAT_CTRL_TABLE_INDEX_Msk (0x3F << REG_ALU_STAT_CTRL_TABLE_INDEX_Pos)
4235#define REG_ALU_STAT_CTRL_TABLE_INDEX(_x) (((_x) << REG_ALU_STAT_CTRL_TABLE_INDEX_Pos) &REG_ALU_STAT_CTRL_TABLE_INDEX_Msk)
4236
4237#define REG_ALU_VAL_A 0x0420
4238#define REG_ALU_VAL_A_size 4
4239#define REG_ALU_VAL_A_MSTP_Pos 0
4240#define REG_ALU_VAL_A_MSTP_Msk (0x7 << REG_ALU_VAL_A_MSTP_Pos)
4241#define REG_ALU_VAL_A_MSTP(_x) (((_x) << REG_ALU_VAL_A_MSTP_Pos) &REG_ALU_VAL_A_MSTP_Msk)
4242#define REG_ALU_VAL_A_PRIO_AGE_Pos 26
4243#define REG_ALU_VAL_A_PRIO_AGE_Msk (0x3 << REG_ALU_VAL_A_PRIO_AGE_Pos)
4244#define REG_ALU_VAL_A_PRIO_AGE(_x) (((_x) << REG_ALU_VAL_A_PRIO_AGE_Pos) &REG_ALU_VAL_A_PRIO_AGE_Msk)
4245#define REG_ALU_VAL_A_DST_FILTER_Pos 29
4246#define REG_ALU_VAL_A_DST_FILTER_Msk (0x1 << REG_ALU_VAL_A_DST_FILTER_Pos)
4247#define REG_ALU_VAL_A_DST_FILTER_ENABLED (0x1 << REG_ALU_VAL_A_DST_FILTER_Pos)
4248#define REG_ALU_VAL_A_DST_FILTER_DISABLED (0x0 << REG_ALU_VAL_A_DST_FILTER_Pos)
4249#define REG_ALU_VAL_A_SRC_FILTER_Pos 30
4250#define REG_ALU_VAL_A_SRC_FILTER_Msk (0x1 << REG_ALU_VAL_A_SRC_FILTER_Pos)
4251#define REG_ALU_VAL_A_SRC_FILTER_ENABLED (0x1 << REG_ALU_VAL_A_SRC_FILTER_Pos)
4252#define REG_ALU_VAL_A_SRC_FILTER_DISABLED (0x0 << REG_ALU_VAL_A_SRC_FILTER_Pos)
4253#define REG_ALU_VAL_A_ALU_STATIC_Pos 31
4254#define REG_ALU_VAL_A_ALU_STATIC_Msk (0x1 << REG_ALU_VAL_A_ALU_STATIC_Pos)
4255#define REG_ALU_VAL_A_ALU_STATIC_STATIC (0x1 << REG_ALU_VAL_A_ALU_STATIC_Pos)
4256#define REG_ALU_VAL_A_ALU_STATIC_DYN (0x0 << REG_ALU_VAL_A_ALU_STATIC_Pos)
4257#define REG_ALU_VAL_A_STATIC_VALID_Pos 31
4258#define REG_ALU_VAL_A_STATIC_VALID_Msk (0x1 << REG_ALU_VAL_A_STATIC_VALID_Pos)
4259#define REG_ALU_VAL_A_STATIC_VALID_TRUE (0x1 << REG_ALU_VAL_A_STATIC_VALID_Pos)
4260#define REG_ALU_VAL_A_STATIC_VALID_FALSE (0x0 << REG_ALU_VAL_A_STATIC_VALID_Pos)
4261
4262
4263#define REG_ALU_VAL_B 0x0424
4264#define REG_ALU_VAL_B_size 4
4265#define REG_ALU_VAL_B_PORTS_Pos 0
4266#define REG_ALU_VAL_B_PORTS_Msk (0x1FFFFFFF << REG_ALU_VAL_B_MSTP_Pos)
4267#define REG_ALU_VAL_B_PORT(_x) (((_x) << REG_ALU_VAL_B_PORTS_Pos) & REG_ALU_VAL_B_PORTS_Msk)
4268#define REG_ALU_VAL_B_USE_FID_Pos 30
4269#define REG_ALU_VAL_B_USE_FID_Msk (0x1 << REG_ALU_VAL_B_USE_FID_Pos)
4270#define REG_ALU_VAL_B_USE_FID_ENABLED (0x1 << REG_ALU_VAL_B_USE_FID_Pos)
4271#define REG_ALU_VAL_B_USE_FID_DISABLED (0x0 << REG_ALU_VAL_B_USE_FID_Pos)
4272#define REG_ALU_VAL_B_OVERRIDE_Pos 31
4273#define REG_ALU_VAL_B_OVERRIDE_Msk (0x1 << REG_ALU_VAL_B_OVERRIDE_Pos)
4274#define REG_ALU_VAL_B_OVERRIDE_ENABLED (0x1 << REG_ALU_VAL_B_OVERRIDE_Pos)
4275#define REG_ALU_VAL_B_OVERRIDE_DISABLED (0x0 << REG_ALU_VAL_B_OVERRIDE_Pos)
4276
4277#define REG_ALU_VAL_C 0x0428
4278#define REG_ALU_VAL_C_size 4
4279#define REG_ALU_VAL_C_MAC_ADDR_HI_Pos 0
4280#define REG_ALU_VAL_C_MAC_ADDR_HI_Msk (0xFFFF << REG_ALU_VAL_C_MAC_ADDR_HI_Pos)
4281#define REG_ALU_VAL_C_MAC_ADDR_HI(_x) (((_x) << REG_ALU_VAL_C_MAC_ADDR_HI_Pos) &REG_ALU_VAL_C_MAC_ADDR_HI_Msk)
4282#define REG_ALU_VAL_C_FID_Pos 16
4283#define REG_ALU_VAL_C_FID_Msk (0x7F << REG_ALU_VAL_C_FID_Pos)
4284#define REG_ALU_VAL_C_FID(_x) (((_x) << REG_ALU_VAL_C_FID_Pos) &REG_ALU_VAL_C_FID_Msk)
4285
4286#define REG_ALU_VAL_D 0x042C
4287#define REG_ALU_VAL_D_size 4
4288#define REG_ALU_VAL_D_MAC_ADDR_LO_Pos 0
4289#define REG_ALU_VAL_D_MAC_ADDR_LO_Msk (0xFFFFFFFF << REG_ALU_VAL_D_MAC_ADDR_LO_Pos)
4290#define REG_ALU_VAL_D_MAC_ADDR_LO(_x) (((_x) << REG_ALU_VAL_D_MAC_ADDR_LO_Pos) &REG_ALU_VAL_D_MAC_ADDR_LO_Msk)
4291
4292
4293#define REG_PTP_CLK_CTRL 0x0500
4294#define REG_PTP_CLK_CTRL_size 2
4295#define REG_PTP_CLK_CTRL_CLK_RESET_Pos 0
4296#define REG_PTP_CLK_CTRL_CLK_RESET_Msk (0x1 << REG_PTP_CLK_CTRL_CLK_RESET_Pos)
4297#define REG_PTP_CLK_CTRL_CLK_RESET_RESET (0x1 << REG_PTP_CLK_CTRL_CLK_RESET_Pos)
4298#define REG_PTP_CLK_CTRL_CLK_Pos 1
4299#define REG_PTP_CLK_CTRL_CLK_Msk (0x1 << REG_PTP_CLK_CTRL_CLK_Pos)
4300#define REG_PTP_CLK_CTRL_CLK_ENABLED (0x1 << REG_PTP_CLK_CTRL_CLK_Pos)
4301#define REG_PTP_CLK_CTRL_CLK_DISABLED (0x0 << REG_PTP_CLK_CTRL_CLK_Pos)
4302#define REG_PTP_CLK_CTRL_CLK_ADJ_Pos 2
4303#define REG_PTP_CLK_CTRL_CLK_ADJ_Msk (0x1 << REG_PTP_CLK_CTRL_CLK_ADJ_Pos)
4304#define REG_PTP_CLK_CTRL_CLK_ADJ_ENABLED (0x1 << REG_PTP_CLK_CTRL_CLK_ADJ_Pos)
4305#define REG_PTP_CLK_CTRL_CLK_ADJ_DISABLED (0x0 << REG_PTP_CLK_CTRL_CLK_ADJPos)
4306#define REG_PTP_CLK_CTRL_LOAD_Pos 3
4307#define REG_PTP_CLK_CTRL_LOAD_Msk (0x1 << REG_PTP_CLK_CTRL_LOAD_Pos)
4308#define REG_PTP_CLK_CTRL_LOAD_ENABLED (0x1 << REG_PTP_CLK_CTRL_LOAD_Pos)
4309#define REG_PTP_CLK_CTRL_READ_Pos 4
4310#define REG_PTP_CLK_CTRL_READ_Msk (0x1 << REG_PTP_CLK_CTRL_READ_Pos)
4311#define REG_PTP_CLK_CTRL_READ_ENABLED (0x1 << REG_PTP_CLK_CTRL_READ_Pos)
4312#define REG_PTP_CLK_CTRL_STEP_DIR_Pos 5
4313#define REG_PTP_CLK_CTRL_STEP_DIR_Msk (0x1 << REG_PTP_CLK_CTRL_STEP_DIR_Pos)
4314#define REG_PTP_CLK_CTRL_STEP_DIR_ADD (0x1 << REG_PTP_CLK_CTRL_STEP_DIR_Pos)
4315#define REG_PTP_CLK_CTRL_STEP_DIR_SUB (0x0 << REG_PTP_CLK_CTRL_STEP_DIR_Pos)
4316#define REG_PTP_CLK_CTRL_STEP_ADJ_Pos 6
4317#define REG_PTP_CLK_CTRL_STEP_ADJ_Msk (0x1 << REG_PTP_CLK_CTRL_STEP_ADJ_Pos)
4318#define REG_PTP_CLK_CTRL_STEP_ADJ_ENABLED (0x1 << REG_PTP_CLK_CTRL_STEP_ADJ_Pos)
4319#define REG_PTP_CLK_CTRL_STEP_ADJ_DISABLED (0x0 << REG_PTP_CLK_CTRL_STEP_ADJ_Pos)
4320#define REG_PTP_CLK_CTRL_SW_FREQ_ADJ_Pos 15
4321#define REG_PTP_CLK_CTRL_SW_FREQ_ADJ_Msk (0x1 << REG_PTP_CLK_CTRL_SW_FREQ_ADJ_Pos)
4322#define REG_PTP_CLK_CTRL_SW_FREQ_ADJ_ENABLED (0x1 << REG_PTP_CLK_CTRL_SW_FREQ_ADJ_Pos)
4323#define REG_PTP_CLK_CTRL_SW_FREQ_ADJ_DISABLED (0x0 << REG_PTP_CLK_CTRL_SW_FREQ_ADJ_Pos)
4324
4325#define REG_PTP_RTC_PHASE 0x0502
4326#define REG_PTP_RTC_PHASE_size 2
4327#define REG_PTP_RTC_PHASE_PHASE_Pos 0
4328#define REG_PTP_RTC_PHASE_PHASE_Msk (0x3 << REG_PTC_RTC_PHASE_PHASE_Pos)
4329#define REG_PTP_RTC_PHASE_PHASE(_x) (((_x) << REG_PTC_RTC_PHASE_PHASE_Pos) &REG_PTC_RTC_PHASE_PHASE_Msk)
4330
4331#define REG_PTP_RTC_NANO 0x0504
4332#define REG_PTP_RTC_NANO_size 4
4333#define REG_PTP_RTC_NANO_NANOSEC_Pos 0
4334#define REG_PTP_RTC_NANO_NANOSEC_Msk (0xFFFFFFFF << REG_PTC_RTC_NANO_NANOSEC_Pos)
4335#define REG_PTP_RTC_NANO_NANOSEC(_x) (((_x) << REG_PTC_RTC_NANO_NANOSEC_Pos) &REG_PTC_RTC_NANO_NANOSEC_Msk)
4336
4337#define REG_PTP_RTC_SEC 0x0508
4338#define REG_PTP_RTC_SEC_size 4
4339#define REG_PTP_RTC_SEC_SEC_Pos 0
4340#define REG_PTP_RTC_SEC_SEC_Msk (0xFFFFFFFF << REG_PTC_RTC_SEC_SEC_Pos)
4341#define REG_PTP_RTC_NANO_SEC(_x) (((_x) << REG_PTC_RTC_SEC_SEC_Pos) &REG_PTC_RTC_SEC_SEC_Msk)
4342
4343#define REG_PTP_RTC_SUBNANO 0x050C
4344#define REG_PTP_RTC_SUBNANO_size 4
4345#define REG_PTP_RTC_SUBNANO_SUB_NANO_Pos 0
4346#define REG_PTP_RTC_SUBNANO_SUB_NANO_Msk (0x3FFFFFFF << REG_PTC_RTC_SUBNANO_SUB_NANO_Pos)
4347#define REG_PTP_RTC_SUBNANO_SUB_NANO(_x) (((_x) << REG_PTC_RTC_SUBNANO_SUB_NANO_Pos) &REG_PTC_RTC_SUBNANO_SUB_NANO_Msk)
4348#define REG_PTP_RTC_SUBNANO_TMP_ADJ_Pos 30
4349#define REG_PTP_RTC_SUBNANO_TMP_ADJ_Msk (0x1 << REG_PTP_RTC_SUBNANO_TMP_ADJ_Pos)
4350#define REG_PTP_RTC_SUBNANO_TMP_ADJ_ENABLED (0x1 << REG_PTP_RTC_SUBNANO_TMP_ADJ_Pos)
4351#define REG_PTP_RTC_SUBNANO_TMP_ADJ_DISABLED (0x0 << REG_PTP_RTC_SUBNANO_TMP_ADJ_Pos)
4352#define REG_PTP_RTC_SUBNANO_TMP_ADJ_DIR_Pos 31
4353#define REG_PTP_RTC_SUBNANO_TMP_ADJ_DIR_Msk (0x1 << REG_PTP_RTC_SUBNANO_TMP_ADJ_DIR_Pos)
4354#define REG_PTP_RTC_SUBNANO_TMP_ADJ_DIR_ENABLED (0x1 << REG_PTP_RTC_SUBNANO_TMP_ADJ_DIR_Pos)
4355#define REG_PTP_RTC_SUBNANO_TMP_ADJ_DIR_DISABLED (0x0 << REG_PTP_RTC_SUBNANO_TMP_ADJ_DIR_Pos)
4356
4357#define REG_PTP_RTC_TMP_ADJ 0x0510
4358#define REG_PTP_RTC_TMP_ADJ_size 4
4359
4360#define REG_PTP_MSG_CONFIG 0x0514
4361#define REG_PTP_MSG_CONFIG_size 4
4362#define REG_PTP_MSG_CONFIG_IPV4_CSUM_UPDATE_Pos 2
4363#define REG_PTP_MSG_CONFIG_IPV4_CSUM_UPDATE_Msk (0x1 << REG_PTP_MSG_CONFIG_IPV4_CSUM_UPDATE_Pos)
4364#define REG_PTP_MSG_CONFIG_IPV4_CSUM_UPDATE_ENABLED (0x1 << REG_PTP_MSG_CONFIG_IPV4_CSUM_UPDATE_Pos)
4365#define REG_PTP_MSG_CONFIG_IPV4_CSUM_UPDATE_DISABLED (0x0 << REG_PTP_MSG_CONFIG_IPV4_CSUM_UPDATE_Pos)
4366#define REG_PTP_MSG_CONFIG_DOMAIN_CHECK_Pos 4
4367#define REG_PTP_MSG_CONFIG_DOMAIN_CHECK_Msk (0x1 << REG_PTP_MSG_CONFIG_DOMAIN_CHECK_Pos)
4368#define REG_PTP_MSG_CONFIG_DOMAIN_CHECK_ENABLED (0x1 << REG_PTP_MSG_CONFIG_DOMAIN_CHECK_Pos)
4369#define REG_PTP_MSG_CONFIG_DOMAIN_CHECK_DISABLED (0x0 << REG_PTP_MSG_CONFIG_DOMAIN_CHECK_Pos)
4370#define REG_PTP_MSG_CONFIG_DROP_SYNC_DELAY_REQ_Pos 5
4371#define REG_PTP_MSG_CONFIG_DROP_SYNC_DELAY_REQ_Msk (0x1 << REG_PTP_MSG_CONFIG_DROP_SYNC_DELAY_REQ_Pos)
4372#define REG_PTP_MSG_CONFIG_DROP_SYNC_DELAY_REQ_ENABLED (0x1 << REG_PTP_MSG_CONFIG_DROP_SYNC_DELAY_REQ_Pos)
4373#define REG_PTP_MSG_CONFIG_DROP_SYNC_DELAY_REQ_DISABLED (0x0 << REG_PTP_MSG_CONFIG_DROP_SYNC_DELAY_REQ_Pos)
4374#define REG_PTP_MSG_CONFIG_PDELAY_CHECK_Pos 7
4375#define REG_PTP_MSG_CONFIG_PDELAY_CHECK_Msk (0x1 << REG_PTP_MSG_CONFIG_PDELAY_CHECK_Pos)
4376#define REG_PTP_MSG_CONFIG_PDELAY_CHECK_ENABLED (0x1 << REG_PTP_MSG_CONFIG_PDELAY_CHECK_Pos)
4377#define REG_PTP_MSG_CONFIG_PDELAY_CHECK_DISABLED (0x0 << REG_PTP_MSG_CONFIG_PDELAY_CHECK_Pos)
4378#define REG_PTP_MSG_CONFIG_DELAY_CHECK_Pos 8
4379#define REG_PTP_MSG_CONFIG_DELAY_CHECK_Msk (0x1 << REG_PTP_MSG_CONFIG_DELAY_CHECK_Pos)
4380#define REG_PTP_MSG_CONFIG_DELAY_CHECK_ENABLED (0x1 << REG_PTP_MSG_CONFIG_DELAY_CHECK_Pos)
4381#define REG_PTP_MSG_CONFIG_DELAY_CHECK_DISABLED (0x0 << REG_PTP_MSG_CONFIG_DELAY_CHECK_Pos)
4382#define REG_PTP_MSG_CONFIG_SYNC_CHECK_Pos 9
4383#define REG_PTP_MSG_CONFIG_SYNC_CHECK_Msk (0x1 << REG_PTP_MSG_CONFIG_SYNC_CHECK_Pos)
4384#define REG_PTP_MSG_CONFIG_SYNC_CHECK_ENABLED (0x1 << REG_PTP_MSG_CONFIG_SYNC_CHECK_Pos)
4385#define REG_PTP_MSG_CONFIG_SYNC_CHECK_DISABLED (0x0 << REG_PTP_MSG_CONFIG_SYNC_CHECK_Pos)
4386#define REG_PTP_MSG_CONFIG_ALL_PTP_HI_PRIO_Pos 10
4387#define REG_PTP_MSG_CONFIG_ALL_PTP_HI_PRIO_Msk (0x1 << REG_PTP_MSG_CONFIG_ALL_PTP_HI_PRIO_Pos)
4388#define REG_PTP_MSG_CONFIG_ALL_PTP_HI_PRIO_ENABLED (0x1 << REG_PTP_MSG_CONFIG_ALL_PTP_HI_PRIO_Pos)
4389#define REG_PTP_MSG_CONFIG_ALL_PTP_HI_PRIO_DISABLED (0x0 << REG_PTP_MSG_CONFIG_ALL_PTP_HI_PRIO_Pos)
4390#define REG_PTP_MSG_CONFIG_ALT_MASTER_Pos 11
4391#define REG_PTP_MSG_CONFIG_ALT_MASTER_Msk (0x1 << REG_PTP_MSG_CONFIG_ALT_MASTER_Pos)
4392#define REG_PTP_MSG_CONFIG_ALT_MASTER_ENABLED (0x1 << REG_PTP_MSG_CONFIG_ALT_MASTER_Pos)
4393#define REG_PTP_MSG_CONFIG_ALT_MASTER_DISABLED (0x0 << REG_PTP_MSG_CONFIG_ALT_MASTER_Pos)
4394#define REG_PTP_MSG_CONFIG_UNICAST_Pos 12
4395#define REG_PTP_MSG_CONFIG_UNICAST_Msk (0x1 << REG_PTP_MSG_CONFIG_UNICAST_Pos)
4396#define REG_PTP_MSG_CONFIG_UNICAST_ENABLED (0x1 << REG_PTP_MSG_CONFIG_UNICAST_Pos)
4397#define REG_PTP_MSG_CONFIG_UNICAST_DISABLED (0x0 << REG_PTP_MSG_CONFIG_UNICAST_Pos)
4398#define REG_PTP_MSG_CONFIG_MODE_Pos 17
4399#define REG_PTP_MSG_CONFIG_MODE_Msk (0x1 << REG_PTP_MSG_CONFIG_MODE_Pos)
4400#define REG_PTP_MSG_CONFIG_MODE_MASTER (0x1 << REG_PTP_MSG_CONFIG_MODE_Pos)
4401#define REG_PTP_MSG_CONFIG_MODE_SLAVE (0x0 << REG_PTP_MSG_CONFIG_MODE_Pos)
4402#define REG_PTP_MSG_CONFIG_TC_Pos 18
4403#define REG_PTP_MSG_CONFIG_TC_Msk (0x1 << REG_PTP_MSG_CONFIG_TC_Pos)
4404#define REG_PTP_MSG_CONFIG_TC_P2P (0x1 << REG_PTP_MSG_CONFIG_TC_Pos)
4405#define REG_PTP_MSG_CONFIG_TC_E2E (0x0 << REG_PTP_MSG_CONFIG_TC_Pos)
4406#define REG_PTP_MSG_CONFIG_IPV6_UDP_Pos 19
4407#define REG_PTP_MSG_CONFIG_IPV6_UDP_Msk (0x1 << REG_PTP_MSG_CONFIG_IPV6_UDP_Pos)
4408#define REG_PTP_MSG_CONFIG_IPV6_UDP_ENABLED (0x1 << REG_PTP_MSG_CONFIG_IPV6_UDP_Pos)
4409#define REG_PTP_MSG_CONFIG_IPV6_UDP_DISABLED (0x0 << REG_PTP_MSG_CONFIG_IPV6_UDP_Pos)
4410#define REG_PTP_MSG_CONFIG_IPV4_UDP_Pos 20
4411#define REG_PTP_MSG_CONFIG_IPV4_UDP_Msk (0x1 << REG_PTP_MSG_CONFIG_IPV4_UDP_Pos)
4412#define REG_PTP_MSG_CONFIG_IPV4_UDP_ENABLED (0x1 << REG_PTP_MSG_CONFIG_IPV4_UDP_Pos)
4413#define REG_PTP_MSG_CONFIG_IPV4_UDP_DISABLED (0x0 << REG_PTP_MSG_CONFIG_IPV4_UDP_Pos)
4414#define REG_PTP_MSG_CONFIG_ETH_MSG_Pos 21
4415#define REG_PTP_MSG_CONFIG_ETH_MSG_Msk (0x1 << REG_PTP_MSG_CONFIG_ETH_MSG_Pos)
4416#define REG_PTP_MSG_CONFIG_ETH_MSG_ENABLED (0x1 << REG_PTP_MSG_CONFIG_ETH_MSG_Pos)
4417#define REG_PTP_MSG_CONFIG_ETH_MSG_DISABLED (0x0 << REG_PTP_MSG_CONFIG_ETH_MSG_Pos)
4418#define REG_PTP_MSG_CONFIG_PTP_Pos 22
4419#define REG_PTP_MSG_CONFIG_PTP_Msk (0x1 << REG_PTP_MSG_CONFIG_PTP_Pos)
4420#define REG_PTP_MSG_CONFIG_PTP_ENABLED (0x1 << REG_PTP_MSG_CONFIG_PTP_Pos)
4421#define REG_PTP_MSG_CONFIG_PTP_DISABLED (0x0 << REG_PTP_MSG_CONFIG_PTP_Pos)
4422
4423
4424#define REG_PTP_DOMAIN_VERSION 0x0518
4425#define REG_PTP_DOMAIN_VERSION_size 2
4426#define REG_PTP_DOMAIN_VERSION_DOMAIN_Pos 0
4427#define REG_PTP_DOMAIN_VERSION_DOMAIN_Msk (0xFF << REG_PTP_DOMAIN_VERSION_DOMAIN_Pos)
4428#define REG_PTP_DOMAIN_VERSION_DOMAIN(_x) (((_x) << REG_PTP_DOMAIN_VERSION_DOMAIN_Pos) & REG_PTP_DOMAIN_VERSION_DOMAIN_Msk)
4429#define REG_PTP_DOMAIN_VERSION_VERSION_Pos 8
4430#define REG_PTP_DOMAIN_VERSION_VERSION_Msk (0xF << REG_PTP_DOMAIN_VERSION_VERSION_Pos)
4431#define REG_PTP_DOMAIN_VERSION_VERSION(_x) (((_x) << REG_PTP_DOMAIN_VERSION_VERSION_Pos) & REG_PTP_DOMAIN_VERSION_VERSION_Msk)
4432
4433#define REG_PTP_UNIT_INDEX 0x0520
4434#define REG_PTP_UNIT_INDEX_size 4
4435#define REG_PTP_UNIT_INDEX_TRIG_UNIT_Pos 0
4436#define REG_PTP_UNIT_INDEX_TRIG_UNIT_Msk (0x3 << REG_PTP_UNIT_INDEX_TRIG_UNIT_Pos)
4437#define REG_PTP_UNIT_INDEX_TRIG_UNIT(_x) (((_x) << REG_PTP_UNIT_INDEX_TRIG_UNIT_Pos) &REG_PTP_UNIT_INDEX_TRIG_UNIT_Msk)
4438#define REG_PTP_UNIT_INDEX_TIMESTAMP_UNIT_Pos 8
4439#define REG_PTP_UNIT_INDEX_TIMESTAMP_UNIT_Msk (0x1 << REG_PTP_UNIT_INDEX_TIMESTAMP_UNIT_Pos)
4440#define REG_PTP_UNIT_INDEX_TIMESTAMP_UNIT(_x) (((_x) << REG_PTP_UNIT_INDEX_TIMESTAMP_UNIT_Pos) &REG_PTP_UNIT_INDEX_TIMESTAMP_UNIT_Msk)
4441#define REG_PTP_UNIT_INDEX_GPIO_INDEX_Pos 16
4442#define REG_PTP_UNIT_INDEX_GPIO_INDEX_Msk (0xFF << REG_PTP_UNIT_INDEX_GPIO_INDEX_Pos)
4443#define REG_PTP_UNIT_INDEX_GPIO_INDEX(_x) (((_x) << REG_PTP_UNIT_INDEX_GPIO_INDEX_Pos) &REG_PTP_UNIT_INDEX_GPIO_INDEX_Msk)
4444
4445#define REG_PTP_TRIG_STATUS 0x0524
4446#define REG_PTP_TRIG_STATUS_size 4
4447#define REG_PTP_TRIG_STATUS_DONE_Pos 0
4448#define REG_PTP_TRIG_STATUS_DONE_Msk (0x7 << REG_PTP_TRIG_STATUS_DONE_Pos)
4449#define REG_PTP_TRIG_STATUS_DONE(_x) (((_x) << REG_PTP_TRIG_STATUS_DONE_Pos) &REG_PTP_TRIG_STATUS_DONE_Msk)
4450#define REG_PTP_TRIG_STATUS_ERROR_Pos 16
4451#define REG_PTP_TRIG_STATUS_ERROR_Msk (0x7 << REG_PTP_TRIG_STATUS_ERROR_Pos)
4452#define REG_PTP_TRIG_STATUS_ERROR(_x) (((_x) << REG_PTP_TRIG_STATUS_ERROR_Pos) &REG_PTP_TRIG_STATUS_ERROR_Msk)
4453
4454#define REG_PTP_INT_STATUS 0x0528
4455#define REG_PTP_INT_STATUS_size 4
4456#define REG_PTP_INT_STATUS_TIMESTAMP_IRQ_Pos 0
4457#define REG_PTP_INT_STATUS_TIMESTAMP_IRQ_Msk (0x7 << REG_PTP_INT_STATUS_TIMESTAMP_IRQ_Pos)
4458#define REG_PTP_INT_STATUS_TIMESTAMP_IRQ(_x) (((_x) << REG_PTP_INT_STATUS_TIMESTAMP_IRQ_Pos) &REG_PTP_INT_STATUS_TIMESTAMP_IRQ_Msk)
4459#define REG_PTP_INT_STATUS_TRIG_IRQ_Pos 16
4460#define REG_PTP_INT_STATUS_TRIG_IRQ_Msk (0x7 << REG_PTP_INT_STATUS_TRIG_IRQ_Pos)
4461#define REG_PTP_INT_STATUS_TRIG_IRQ(_x) (((_x) << REG_PTP_INT_STATUS_TRIG_IRQ_Pos) &REG_PTP_INT_STATUS_TRIG_IRQ_Msk)
4462
4463#define REG_PTP_TS_CTRL 0x052C
4464#define REG_PTP_TS_CTRL_size 4
4465#define REG_PTP_TS_CTRL_TS_SW_RESET_Pos 0
4466#define REG_PTP_TS_CTRL_TS_SW_RESET_Msk (0x1 << REG_PTP_TS_CTRL_TS_SW_RESET_Pos)
4467#define REG_PTP_TS_CTRL_TS_SW_RESET (0x1 << REG_PTP_TS_CTRL_TS_SW_RESET_Pos)
4468#define REG_PTP_TS_CTRL_TS_Pos 1
4469#define REG_PTP_TS_CTRL_TS_Msk (0x1 << REG_PTP_TS_CTRL_TS_Pos)
4470#define REG_PTP_TS_CTRL_TS_ENABLED (0x1 << REG_PTP_TS_CTRL_TS_Pos)
4471#define REG_PTP_TS_CTRL_TS_DISABLED (0x0 << REG_PTP_TS_CTRL_TS_Pos)
4472#define REG_PTP_TS_CTRL_TRIG_RESET_Pos 2
4473#define REG_PTP_TS_CTRL_TRIG_RESET_Msk (0x1 << REG_PTP_TS_CTRL_TRIG_RESET_Pos)
4474#define REG_PTP_TS_CTRL_TRIG_RESET (0x1 << REG_PTP_TS_CTRL_TRIG_RESET_Pos)
4475#define REG_PTP_TS_CTRL_TRIG_Pos 3
4476#define REG_PTP_TS_CTRL_TRIG_Msk (0x1 << REG_PTP_TS_CTRL_TRIG_Pos)
4477#define REG_PTP_TS_CTRL_TRIG_ENABLED (0x1 << REG_PTP_TS_CTRL_TRIG_Pos)
4478#define REG_PTP_TS_CTRL_TRIG_DISABLED (0x0 << REG_PTP_TS_CTRL_TRIG_Pos)
4479#define REG_PTP_TS_CTRL_TRIG_ACTIVE_Pos 4
4480#define REG_PTP_TS_CTRL_TRIG_ACTIVE_Msk (0x1 << REG_PTP_TS_CTRL_TRIG_ACTIVE_Pos)
4481#define REG_PTP_TS_CTRL_TRIG_ACTIVE_ENABLED (0x1 << REG_PTP_TS_CTRL_TRIG_ACTIVE_Pos)
4482#define REG_PTP_TS_CTRL_TRIG_ACTIVE_DISABLED (0x0 << REG_PTP_TS_CTRL_TRIG_ACTIVE_Pos)
4483#define REG_PTP_TS_CTRL_TS_INT_Pos 5
4484#define REG_PTP_TS_CTRL_TS_INT_Msk (0x1 << REG_PTP_TS_CTRL_TS_INT_Pos)
4485#define REG_PTP_TS_CTRL_TS_INT_ENABLED (0x1 << REG_PTP_TS_CTRL_TS_INT_Pos)
4486#define REG_PTP_TS_CTRL_TS_INT_DISABLED (0x0 << REG_PTP_TS_CTRL_TS_INT_Pos)
4487#define REG_PTP_TS_CTRL_GPIO_DIR_Pos 6
4488#define REG_PTP_TS_CTRL_GPIO_DIR_Msk (0x1 << REG_PTP_TS_CTRL_GPIO_DIR_Pos)
4489#define REG_PTP_TS_CTRL_GPIO_DIR_TS_INPUT (0x1 << REG_PTP_TS_CTRL_GPIO_DIR_Pos)
4490#define REG_PTP_TS_CTRL_GPIO_DIR_TRIG_OUT (0x0 << REG_PTP_TS_CTRL_GPIO_DIR_Pos)
4491#define REG_PTP_TS_CTRL_GPIO_IN_Pos 7
4492#define REG_PTP_TS_CTRL_GPIO_IN_Msk (0x1 << REG_PTP_TS_CTRL_GPIO_IN_Pos)
4493#define REG_PTP_TS_CTRL_GPIO_OUT_SEL_Pos 8
4494#define REG_PTP_TS_CTRL_GPIO_OUT_SEL_Msk (0x1 << REG_PTP_TS_CTRL_GPIO_OUT_SEL_Pos)
4495#define REG_PTP_TS_CTRL_GPIO_OUT_SEL_COMB (0x1 << REG_PTP_TS_CTRL_GPIO_OUT_SEL_Pos)
4496#define REG_PTP_TS_CTRL_GPIO_OUT_SEL_FF (0x0 << REG_PTP_TS_CTRL_GPIO_OUT_SEL_Pos)
4497
4498#define REG_PTP_TRIG_TARGET_NANO 0x0530
4499#define REG_PTP_TRIG_TARGET_NANO_size 4
4500#define REG_PTP_TRIG_TARGET_NANO_NANOSEC_Pos 0
4501#define REG_PTP_TRIG_TARGET_NANO_NANOSEC_Msk (0x3FFFFFFF << REG_PTC_TRIG_TARGET_NANO_NANOSEC_Pos)
4502#define REG_PTP_TRIG_TARGET_NANO_NANOSEC(_x) (((_x) << REG_PTC_TRIG_TARGET_NANO_NANOSEC_Pos) &REG_PTC_TRIG_TARGET_NANO_NANOSEC_Msk)
4503
4504#define REG_PTP_TRIG_TARGET_SEC 0x0534
4505#define REG_PTP_TRIG_TARGET_SEC_size 4
4506#define REG_PTP_TRIG_TARGET_SEC_SEC_Pos 0
4507#define REG_PTP_TRIG_TARGET_SEC_SEC_Msk (0xFFFFFFFF << REG_PTC_TRIG_TARGET_SEC_SEC_Pos)
4508#define REG_PTP_TRIG_TARGET_SEC_SEC(_x) (((_x) << REG_PTC_TRIG_TARGET_SEC_SEC_Pos) &REG_PTC_TRIG_TARGET_SEC_SEC_Msk)
4509
4510#define REG_PTP_TRIG_CTRL 0x0538
4511#define REG_PTP_TRIG_CTRL_size 4
4512#define REG_PTP_TRIG_CTRL_TRIG_ITERATION_Pos 0
4513#define REG_PTP_TRIG_CTRL_TRIG_ITERATION_Msk (0xFFFF << REG_PTP_TRIG_CTRL_TRIG_ITERATION_Pos)
4514#define REG_PTP_TRIG_CTRL_TRIG_ITERATION(_x) (((_x) << REG_PTP_TRIG_CTRL_TRIG_ITERATION_Pos) &REG_PTP_TRIG_CTRL_TRIG_ITERATION_Msk)
4515#define REG_PTP_TRIG_CTRL_TRIG_GPO_Pos 16
4516#define REG_PTP_TRIG_CTRL_TRIG_GPO_Msk (0x1 << REG_PTP_TRIG_CTRL_TRIG_GPO_Pos)
4517#define REG_PTP_TRIG_CTRL_TRIG_GPO_GPIO2 (0x1 << REG_PTP_TRIG_CTRL_TRIG_GPO_Pos)
4518#define REG_PTP_TRIG_CTRL_TRIG_GPO_GPIO1 (0x0 << REG_PTP_TRIG_CTRL_TRIG_GPO_Pos)
4519#define REG_PTP_TRIG_CTRL_TRIG_EVT_OUT_Pos 20
4520#define REG_PTP_TRIG_CTRL_TRIG_EVT_OUT_Msk (0x7 << REG_PTP_TRIG_CTRL_TRIG_EVT_OUT_Pos)
4521#define REG_PTP_TRIG_CTRL_TRIG_EVT_OUT_EDGE_NEG (0x0 << REG_PTP_TRIG_CTRL_TRIG_EVT_OUT_Pos)
4522#define REG_PTP_TRIG_CTRL_TRIG_EVT_OUT_EDGE_POS (0x1 << REG_PTP_TRIG_CTRL_TRIG_EVT_OUT_Pos)
4523#define REG_PTP_TRIG_CTRL_TRIG_EVT_OUT_PULSE_NEG (0x2 << REG_PTP_TRIG_CTRL_TRIG_EVT_OUT_Pos)
4524#define REG_PTP_TRIG_CTRL_TRIG_EVT_OUT_PLUSE_POS (0x3 << REG_PTP_TRIG_CTRL_TRIG_EVT_OUT_Pos)
4525#define REG_PTP_TRIG_CTRL_TRIG_EVT_OUT_PER_NEG (0x4 << REG_PTP_TRIG_CTRL_TRIG_EVT_OUT_Pos)
4526#define REG_PTP_TRIG_CTRL_TRIG_EVT_OUT_PER_POS (0x5 << REG_PTP_TRIG_CTRL_TRIG_EVT_OUT_Pos)
4527#define REG_PTP_TRIG_CTRL_TRIG_EVT_OUT_PATTERN (0x6 << REG_PTP_TRIG_CTRL_TRIG_EVT_OUT_Pos)
4528#define REG_PTP_TRIG_CTRL_TRIG_EDGE_Pos 23
4529#define REG_PTP_TRIG_CTRL_TRIG_EDGE_Msk (0x1 << REG_PTP_TRIG_CTRL_TRIG_EDGE_Pos)
4530#define REG_PTP_TRIG_CTRL_TRIG_EDGE_POS (0x0 << REG_PTP_TRIG_CTRL_TRIG_EDGE_Pos)
4531#define REG_PTP_TRIG_CTRL_TRIG_EDGE_NEG (0x1 << REG_PTP_TRIG_CTRL_TRIG_EDGE_Pos)
4532#define REG_PTP_TRIG_CTRL_TRIG_NOTIFY_Pos 24
4533#define REG_PTP_TRIG_CTRL_TRIG_NOTIFY_Msk (0x1 << REG_PTP_TRIG_CTRL_TRIG_NOTIFY_Pos)
4534#define REG_PTP_TRIG_CTRL_TRIG_NOTIFY_ENABLED (0x1 << REG_PTP_TRIG_CTRL_TRIG_NOTIFY_Pos)
4535#define REG_PTP_TRIG_CTRL_TRIG_NOTIFY_DISABLED (0x0 << REG_PTP_TRIG_CTRL_TRIG_NOTIFY_Pos)
4536#define REG_PTP_TRIG_CTRL_TRIG_NOW_Pos 25
4537#define REG_PTP_TRIG_CTRL_TRIG_NOW_Msk (0x1 << REG_PTP_TRIG_CTRL_TRIG_NOW_Pos)
4538#define REG_PTP_TRIG_CTRL_TRIG_NOW (0x1 << REG_PTP_TRIG_CTRL_TRIG_NOW_Pos)
4539#define REG_PTP_TRIG_CTRL_CASCADE_UPSTREAM_SEL_Pos 26
4540#define REG_PTP_TRIG_CTRL_CASCADE_UPSTREAM_SEL_Msk (0x3 << REG_PTP_TRIG_CTRL_CASCADE_UPSTREAM_SEL_Pos)
4541#define REG_PTP_TRIG_CTRL_CASCADE_UPSTREAM_SEL(_x) (((_x) << REG_PTP_TRIG_CTRL_CASCADE_UPSTREAM_SEL_Pos) &REG_PTP_TRIG_CTRL_CASCADE_UPSTREAM_SEL_Msk)
4542#define REG_PTP_TRIG_CTRL_CASCADE_TAIL_Pos 30
4543#define REG_PTP_TRIG_CTRL_CASCADE_TAIL_Msk (0x1 << REG_PTP_TRIG_CTRL_CASCADE_TAIL_Pos)
4544#define REG_PTP_TRIG_CTRL_CASCADE_TAIL_ENABLED (0x1 << REG_PTP_TRIG_CTRL_CASCADE_TAIL_Pos)
4545#define REG_PTP_TRIG_CTRL_CASCADE_TAIL_DISABLED (0x0 << REG_PTP_TRIG_CTRL_CASCADE_TAIL_Pos)
4546#define REG_PTP_TRIG_CTRL_CASCADE_Pos 31
4547#define REG_PTP_TRIG_CTRL_CASCADE_Msk (0x1 << REG_PTP_TRIG_CTRL_CASCADE_Pos)
4548#define REG_PTP_TRIG_CTRL_CASCADE_ENABLED (0x1 << REG_PTP_TRIG_CTRL_CASCADE_Pos)
4549#define REG_PTP_TRIG_CTRL_CASCADE_DISABLED (0x0 << REG_PTP_TRIG_CTRL_CASCADE_Pos)
4550
4551#define REG_PTP_TRIG_CYC_WIDTH 0x053C
4552#define REG_PTP_TRIG_CYC_WIDTH_size 4
4553#define REG_PTP_TRIG_CYC_WIDTH_WIDTH_Pos 0
4554#define REG_PTP_TRIG_CYC_WIDTH_WIDTH_Msk (0xFFFFFFFF << REG_PTP_TRIG_CYC_WIDTH_WIDTH_Pos)
4555#define REG_PTP_TRIG_CYC_WIDTH_WIDTH(_x) (((_x) << REG_PTP_TRIG_CYC_WIDTH_WIDTH_Pos) &REG_PTP_TRIG_CYC_WIDTH_WIDTH_Msk)
4556
4557#define REG_PTP_TRIG_CYC_CNT 0x0540
4558#define REG_PTP_TRIG_CYC_CNT_size 4
4559#define REG_PTP_TRIG_CYC_CNT_BIT_PATTERN_Pos 0
4560#define REG_PTP_TRIG_CYC_CNT_BIT_PATTERN_Msk (0xFFFF << REG_PTP_TRIG_CYC_CNT_BIT_PATTERN_Pos)
4561#define REG_PTP_TRIG_CYC_CNT_BIT_PATTERN(_x) (((_x) << REG_PTP_TRIG_CYC_CNT_BIT_PATTERN_Pos) &REG_PTP_TRIG_CYC_CNT_BIT_PATTERN_Msk)
4562#define REG_PTP_TRIG_CYC_CNT_CYCLE_CNT_Pos 16
4563#define REG_PTP_TRIG_CYC_CNT_CYCLE_CNT_Msk (0xFFFF << REG_PTP_TRIG_CYC_CNT_CYCLE_CNT_Pos)
4564#define REG_PTP_TRIG_CYC_CNT_CYCLE_CNT(_x) (((_x) << REG_PTP_TRIG_CYC_CNT_CYCLE_CNT_Pos) &REG_PTP_TRIG_CYC_CNT_CYCLE_CNT_Msk)
4565
4566#define REG_PTP_TRIG_ITER_TIME 0x0544
4567#define REG_PTP_TRIG_ITER_TIME_size 4
4568#define REG_PTP_TRIG_ITER_TIME_NANOSEC_Pos 0
4569#define REG_PTP_TRIG_ITER_TIME_NANOSEC_Msk (0xFFFFFFFF << REG_PTP_TRIG_ITER_TIME_NANOSEC_Pos)
4570#define REG_PTP_TRIG_ITER_TIME_NANOSEC(_x) (((_x) << REG_PTP_TRIG_ITER_TIME_NANOSEC_Pos) &REG_PTP_TRIG_ITER_TIME_NANOSEC_Msk)
4571
4572#define REG_PTP_TRIG_PULSE 0x0548
4573#define REG_PTP_TRIG_PULSE_size 4
4574#define REG_PTP_TRIG_PULSE_OUT_WIDTH_Pos 0
4575#define REG_PTP_TRIG_PULSE_OUT_WIDTH_Msk (0xFFFF << REG_PTP_TRIG_PULSE_OUT_WIDTH_Pos)
4576#define REG_PTP_TRIG_PULSE_OUT_WIDTH(_x) (((_x) << REG_PTP_TRIG_PULSE_OUT_WIDTH_Pos) &REG_PTP_TRIG_PULSE_OUT_WIDTH_Msk)
4577#define REG_PTP_TRIG_PULSE_PPS_WIDTH_HI_Pos 16
4578#define REG_PTP_TRIG_PULSE_PPS_WIDTH_HI_Msk (0xFF << REG_PTP_TRIG_PULSE_PPS_WIDTH_HI_Pos)
4579#define REG_PTP_TRIG_PULSE_PPS_WIDTH_HI(_x) (((_x) << REG_PTP_TRIG_PULSE_PPS_WIDTH_HI_Pos) &REG_PTP_TRIG_PULSE_PPS_WIDTH_HI_Msk)
4580
4581#define REG_PTP_TS_STAT_CTRL 0x0550
4582#define REG_PTP_TS_STAT_CTRL_size 4
4583#define REG_PTP_TS_STAT_CTRL_TS_CASCADE_Pos 0
4584#define REG_PTP_TS_STAT_CTRL_TS_CASCADE_Msk (0x1 << REG_PTP_TS_STAT_CTRL_TS_CASCADE_Pos)
4585#define REG_PTP_TS_STAT_CTRL_TS_CASCADE_ENABLED (0x1 << REG_PTP_TS_STAT_CTRL_TS_CASCADE_Pos)
4586#define REG_PTP_TS_STAT_CTRL_TS_CASCADE_DISABLED (0x0 << REG_PTP_TS_STAT_CTRL_TS_CASCADE_Pos)
4587#define REG_PTP_TS_STAT_CTRL_TS_CASCADE_UPS_Pos 1
4588#define REG_PTP_TS_STAT_CTRL_TS_CASCADE_UPS_Msk (0x1 << REG_PTP_TS_STAT_CTRL_TS_CASCADE_UPS_Pos)
4589#define REG_PTP_TS_STAT_CTRL_TS_CASCADE_UPS_TS_1 (0x1 << REG_PTP_TS_STAT_CTRL_TS_CASCADE_UPS_Pos)
4590#define REG_PTP_TS_STAT_CTRL_TS_CASCADE_UPS_TS_0 (0x0 << REG_PTP_TS_STAT_CTRL_TS_CASCADE_UPS_Pos)
4591#define REG_PTP_TS_STAT_CTRL_TS_CASCADE_TAIL_Pos 5
4592#define REG_PTP_TS_STAT_CTRL_TS_CASCADE_TAIL_Msk (0x1 << REG_PTP_TS_STAT_CTRL_TS_CASCADE_TAIL_Pos)
4593#define REG_PTP_TS_STAT_CTRL_TS_CASCADE_TAIL_ENABLED (0x1 << REG_PTP_TS_STAT_CTRL_TS_CASCADE_TAIL_Pos)
4594#define REG_PTP_TS_STAT_CTRL_TS_CASCADE_TAIL_DISABLED (0x0 << REG_PTP_TS_STAT_CTRL_TS_CASCADE_TAIL_Pos)
4595#define REG_PTP_TS_STAT_CTRL_TS_DETECT_NEG_Pos 6
4596#define REG_PTP_TS_STAT_CTRL_TS_DETECT_NEG_Msk (0x1 << REG_PTP_TS_STAT_CTRL_TS_DETECT_NEG_Pos)
4597#define REG_PTP_TS_STAT_CTRL_TS_DETECT_NEG_ENABLED (0x1 << REG_PTP_TS_STAT_CTRL_TS_DETECT_NEG_Pos)
4598#define REG_PTP_TS_STAT_CTRL_TS_DETECT_NEG_DISABLED (0x0 << REG_PTP_TS_STAT_CTRL_TS_DETECT_NEG_Pos)
4599#define REG_PTP_TS_STAT_CTRL_TS_DETECT_POS_Pos 7
4600#define REG_PTP_TS_STAT_CTRL_TS_DETECT_POS_Msk (0x1 << REG_PTP_TS_STAT_CTRL_TS_DETECT_POS_Pos)
4601#define REG_PTP_TS_STAT_CTRL_TS_DETECT_POS_ENABLED (0x1 << REG_PTP_TS_STAT_CTRL_TS_DETECT_POS_Pos)
4602#define REG_PTP_TS_STAT_CTRL_TS_DETECT_POS_DISABLED (0x0 << REG_PTP_TS_STAT_CTRL_TS_DETECT_POS_Pos)
4603#define REG_PTP_TS_STAT_CTRL_TS_EVT_OVERFLOW_Pos 16
4604#define REG_PTP_TS_STAT_CTRL_TS_EVT_OVERFLOW_Msk (0x1 << REG_PTP_TS_STAT_CTRL_TS_EVT_OVERFLOW_Pos)
4605#define REG_PTP_TS_STAT_CTRL_TS_EVT_OVERFLOW_ENABLED (0x1 << REG_PTP_TS_STAT_CTRL_TS_EVT_OVERFLOW_Pos)
4606#define REG_PTP_TS_STAT_CTRL_TS_EVT_OVERFLOW_DISABLED (0x0 << REG_PTP_TS_STAT_CTRL_TS_EVT_OVERFLOW_Pos)
4607#define REG_PTP_TS_STAT_CTRL_TS_EVT_CNT_Pos 17
4608#define REG_PTP_TS_STAT_CTRL_TS_EVT_CNT_Msk (0xF << REG_PTP_TS_STAT_CTRL_TS_EVT_CNT_Pos)
4609
4610#define REG_PTP_TS_EVT_0_NANO 0x0554
4611#define REG_PTP_TS_EVT_0_NANO_size 4
4612#define REG_PTP_TS_EVT_0_NANO_NANOSEC_Pos 0
4613#define REG_PTP_TS_EVT_0_NANO_NANOSEC_Msk (0x3FFFFFFF << REG_PTP_TS_EVT_0_NANO_NANOSEC_Pos)
4614#define REG_PTP_TS_EVT_0_NANO_EVT_EDGE_Pos 30
4615#define REG_PTP_TS_EVT_0_NANO_EVT_EDGE_Msk (0x1 << REG_PTP_TS_EVT_0_NANO_EVT_EDGE_Pos)
4616#define REG_PTP_TS_EVT_0_NANO_EVT_EDGE_POS (0x1 << REG_PTP_TS_EVT_0_NANO_EVT_EDGE_Pos)
4617#define REG_PTP_TS_EVT_0_NANO_EVT_EDGE_NEG (0x1 << REG_PTP_TS_EVT_0_NANO_EVT_EDGE_Pos)
4618
4619#define REG_PTP_TS_EVT_0_SEC 0x0558
4620#define REG_PTP_TS_EVT_0_SEC_size 4
4621#define REG_PTP_TS_EVT_0_SEC_SEC_Pos 0
4622#define REG_PTP_TS_EVT_0_SEC_SEC_Msk (0xFFFFFFFF << REG_PTP_TS_EVT_0_SEC_SEC_Pos)
4623
4624#define REG_PTP_TS_EVT_0_PHASE 0x055C
4625#define REG_PTP_TS_EVT_0_PHASE_size 4
4626#define REG_PTP_TS_EVT_0_PHASE_PHASE_Pos 0
4627#define REG_PTP_TS_EVT_0_PHASE_PHASE_Msk (0x7 << REG_PTP_TS_EVT_0_PHASE_PHASE_Pos)
4628
4629#define REG_PTP_TS_EVT_1_NANO 0x0560
4630#define REG_PTP_TS_EVT_1_NANO_size 4
4631#define REG_PTP_TS_EVT_1_NANO_NANOSEC_Pos 0
4632#define REG_PTP_TS_EVT_1_NANO_NANOSEC_Msk (0x3FFFFFFF << REG_PTP_TS_EVT_1_NANO_NANOSEC_Pos)
4633#define REG_PTP_TS_EVT_1_NANO_EVT_EDGE_Pos 30
4634#define REG_PTP_TS_EVT_1_NANO_EVT_EDGE_Msk (0x1 << REG_PTP_TS_EVT_1_NANO_EVT_EDGE_Pos)
4635#define REG_PTP_TS_EVT_1_NANO_EVT_EDGE_POS (0x1 << REG_PTP_TS_EVT_1_NANO_EVT_EDGE_Pos)
4636#define REG_PTP_TS_EVT_1_NANO_EVT_EDGE_NEG (0x1 << REG_PTP_TS_EVT_1_NANO_EVT_EDGE_Pos)
4637
4638#define REG_PTP_TS_EVT_1_SEC 0x0564
4639#define REG_PTP_TS_EVT_1_SEC_size 4
4640#define REG_PTP_TS_EVT_1_SEC_SEC_Pos 0
4641#define REG_PTP_TS_EVT_1_SEC_SEC_Msk (0xFFFFFFFF << REG_PTP_TS_EVT_1_SEC_SEC_Pos)
4642
4643#define REG_PTP_TS_EVT_1_PHASE 0x0568
4644#define REG_PTP_TS_EVT_1_PHASE_size 4
4645#define REG_PTP_TS_EVT_1_PHASE_PHASE_Pos 0
4646#define REG_PTP_TS_EVT_1_PHASE_PHASE_Msk (0x7 << REG_PTP_TS_EVT_1_PHASE_PHASE_Pos)
4647
4648#define REG_PTP_TS_EVT_2_NANO 0x056C
4649#define REG_PTP_TS_EVT_2_NANO_size 4
4650#define REG_PTP_TS_EVT_2_NANO_NANOSEC_Pos 0
4651#define REG_PTP_TS_EVT_2_NANO_NANOSEC_Msk (0x3FFFFFFF << REG_PTP_TS_EVT_2_NANO_NANOSEC_Pos)
4652#define REG_PTP_TS_EVT_2_NANO_EVT_EDGE_Pos 30
4653#define REG_PTP_TS_EVT_2_NANO_EVT_EDGE_Msk (0x1 << REG_PTP_TS_EVT_2_NANO_EVT_EDGE_Pos)
4654#define REG_PTP_TS_EVT_2_NANO_EVT_EDGE_POS (0x1 << REG_PTP_TS_EVT_2_NANO_EVT_EDGE_Pos)
4655#define REG_PTP_TS_EVT_2_NANO_EVT_EDGE_NEG (0x1 << REG_PTP_TS_EVT_2_NANO_EVT_EDGE_Pos)
4656
4657#define REG_PTP_TS_EVT_2_SEC 0x0570
4658#define REG_PTP_TS_EVT_2_SEC_size 4
4659#define REG_PTP_TS_EVT_2_SEC_SEC_Pos 0
4660#define REG_PTP_TS_EVT_2_SEC_SEC_Msk (0xFFFFFFFF << REG_PTP_TS_EVT_2_SEC_SEC_Pos)
4661
4662#define REG_PTP_TS_EVT_2_PHASE 0x0574
4663#define REG_PTP_TS_EVT_2_PHASE_size 4
4664#define REG_PTP_TS_EVT_2_PHASE_PHASE_Pos 0
4665#define REG_PTP_TS_EVT_2_PHASE_PHASE_Msk (0x7 << REG_PTP_TS_EVT_2_PHASE_PHASE_Pos)
4666
4667#define REG_PTP_TS_EVT_3_NANO 0x0578
4668#define REG_PTP_TS_EVT_3_NANO_size 4
4669#define REG_PTP_TS_EVT_3_NANO_NANOSEC_Pos 0
4670#define REG_PTP_TS_EVT_3_NANO_NANOSEC_Msk (0x3FFFFFFF << REG_PTP_TS_EVT_3_NANO_NANOSEC_Pos)
4671#define REG_PTP_TS_EVT_3_NANO_EVT_EDGE_Pos 30
4672#define REG_PTP_TS_EVT_3_NANO_EVT_EDGE_Msk (0x1 << REG_PTP_TS_EVT_3_NANO_EVT_EDGE_Pos)
4673#define REG_PTP_TS_EVT_3_NANO_EVT_EDGE_POS (0x1 << REG_PTP_TS_EVT_3_NANO_EVT_EDGE_Pos)
4674#define REG_PTP_TS_EVT_3_NANO_EVT_EDGE_NEG (0x1 << REG_PTP_TS_EVT_3_NANO_EVT_EDGE_Pos)
4675
4676#define REG_PTP_TS_EVT_3_SEC 0x057C
4677#define REG_PTP_TS_EVT_3_SEC_size 4
4678#define REG_PTP_TS_EVT_3_SEC_SEC_Pos 0
4679#define REG_PTP_TS_EVT_3_SEC_SEC_Msk (0xFFFFFFFF << REG_PTP_TS_EVT_3_SEC_SEC_Pos)
4680
4681#define REG_PTP_TS_EVT_3_PHASE 0x0580
4682#define REG_PTP_TS_EVT_3_PHASE_size 4
4683#define REG_PTP_TS_EVT_3_PHASE_PHASE_Pos 0
4684#define REG_PTP_TS_EVT_3_PHASE_PHASE_Msk (0x7 << REG_PTP_TS_EVT_3_PHASE_PHASE_Pos)
4685
4686#define REG_PTP_TS_EVT_4_NANO 0x0584
4687#define REG_PTP_TS_EVT_4_NANO_size 4
4688#define REG_PTP_TS_EVT_4_NANO_NANOSEC_Pos 0
4689#define REG_PTP_TS_EVT_4_NANO_NANOSEC_Msk (0x3FFFFFFF << REG_PTP_TS_EVT_4_NANO_NANOSEC_Pos)
4690#define REG_PTP_TS_EVT_4_NANO_EVT_EDGE_Pos 30
4691#define REG_PTP_TS_EVT_4_NANO_EVT_EDGE_Msk (0x1 << REG_PTP_TS_EVT_4_NANO_EVT_EDGE_Pos)
4692#define REG_PTP_TS_EVT_4_NANO_EVT_EDGE_POS (0x1 << REG_PTP_TS_EVT_4_NANO_EVT_EDGE_Pos)
4693#define REG_PTP_TS_EVT_4_NANO_EVT_EDGE_NEG (0x1 << REG_PTP_TS_EVT_4_NANO_EVT_EDGE_Pos)
4694
4695#define REG_PTP_TS_EVT_4_SEC 0x0588
4696#define REG_PTP_TS_EVT_4_SEC_size 4
4697#define REG_PTP_TS_EVT_4_SEC_SEC_Pos 0
4698#define REG_PTP_TS_EVT_4_SEC_SEC_Msk (0xFFFFFFFF << REG_PTP_TS_EVT_4_SEC_SEC_Pos)
4699
4700#define REG_PTP_TS_EVT_4_PHASE 0x058C
4701#define REG_PTP_TS_EVT_4_PHASE_size 4
4702#define REG_PTP_TS_EVT_4_PHASE_PHASE_Pos 0
4703#define REG_PTP_TS_EVT_4_PHASE_PHASE_Msk (0x7 << REG_PTP_TS_EVT_4_PHASE_PHASE_Pos)
4704
4705#define REG_PTP_TS_EVT_5_NANO 0x0590
4706#define REG_PTP_TS_EVT_5_NANO_size 4
4707#define REG_PTP_TS_EVT_5_NANO_NANOSEC_Pos 0
4708#define REG_PTP_TS_EVT_5_NANO_NANOSEC_Msk (0x3FFFFFFF << REG_PTP_TS_EVT_5_NANO_NANOSEC_Pos)
4709#define REG_PTP_TS_EVT_5_NANO_EVT_EDGE_Pos 30
4710#define REG_PTP_TS_EVT_5_NANO_EVT_EDGE_Msk (0x1 << REG_PTP_TS_EVT_5_NANO_EVT_EDGE_Pos)
4711#define REG_PTP_TS_EVT_5_NANO_EVT_EDGE_POS (0x1 << REG_PTP_TS_EVT_5_NANO_EVT_EDGE_Pos)
4712#define REG_PTP_TS_EVT_5_NANO_EVT_EDGE_NEG (0x1 << REG_PTP_TS_EVT_5_NANO_EVT_EDGE_Pos)
4713
4714#define REG_PTP_TS_EVT_5_SEC 0x0594
4715#define REG_PTP_TS_EVT_5_SEC_size 4
4716#define REG_PTP_TS_EVT_5_SEC_SEC_Pos 0
4717#define REG_PTP_TS_EVT_5_SEC_SEC_Msk (0xFFFFFFFF << REG_PTP_TS_EVT_5_SEC_SEC_Pos)
4718
4719#define REG_PTP_TS_EVT_5_PHASE 0x0598
4720#define REG_PTP_TS_EVT_5_PHASE_size 4
4721#define REG_PTP_TS_EVT_5_PHASE_PHASE_Pos 0
4722#define REG_PTP_TS_EVT_5_PHASE_PHASE_Msk (0x7 << REG_PTP_TS_EVT_5_PHASE_PHASE_Pos)
4723
4724#define REG_PTP_TS_EVT_6_NANO 0x059C
4725#define REG_PTP_TS_EVT_6_NANO_size 4
4726#define REG_PTP_TS_EVT_6_NANO_NANOSEC_Pos 0
4727#define REG_PTP_TS_EVT_6_NANO_NANOSEC_Msk (0x3FFFFFFF << REG_PTP_TS_EVT_6_NANO_NANOSEC_Pos)
4728#define REG_PTP_TS_EVT_6_NANO_EVT_EDGE_Pos 30
4729#define REG_PTP_TS_EVT_6_NANO_EVT_EDGE_Msk (0x1 << REG_PTP_TS_EVT_6_NANO_EVT_EDGE_Pos)
4730#define REG_PTP_TS_EVT_6_NANO_EVT_EDGE_POS (0x1 << REG_PTP_TS_EVT_6_NANO_EVT_EDGE_Pos)
4731#define REG_PTP_TS_EVT_6_NANO_EVT_EDGE_NEG (0x1 << REG_PTP_TS_EVT_6_NANO_EVT_EDGE_Pos)
4732
4733#define REG_PTP_TS_EVT_6_SEC 0x05A0
4734#define REG_PTP_TS_EVT_6_SEC_size 4
4735#define REG_PTP_TS_EVT_6_SEC_SEC_Pos 0
4736#define REG_PTP_TS_EVT_6_SEC_SEC_Msk (0xFFFFFFFF << REG_PTP_TS_EVT_6_SEC_SEC_Pos)
4737
4738#define REG_PTP_TS_EVT_6_PHASE 0x05A4
4739#define REG_PTP_TS_EVT_6_PHASE_size 4
4740#define REG_PTP_TS_EVT_6_PHASE_PHASE_Pos 0
4741#define REG_PTP_TS_EVT_6_PHASE_PHASE_Msk (0x7 << REG_PTP_TS_EVT_6_PHASE_PHASE_Pos)
4742
4743#define REG_PTP_TS_EVT_7_NANO 0x05A8
4744#define REG_PTP_TS_EVT_7_NANO_size 4
4745#define REG_PTP_TS_EVT_7_NANO_NANOSEC_Pos 0
4746#define REG_PTP_TS_EVT_7_NANO_NANOSEC_Msk (0x3FFFFFFF << REG_PTP_TS_EVT_7_NANO_NANOSEC_Pos)
4747#define REG_PTP_TS_EVT_7_NANO_EVT_EDGE_Pos 30
4748#define REG_PTP_TS_EVT_7_NANO_EVT_EDGE_Msk (0x1 << REG_PTP_TS_EVT_7_NANO_EVT_EDGE_Pos)
4749#define REG_PTP_TS_EVT_7_NANO_EVT_EDGE_POS (0x1 << REG_PTP_TS_EVT_7_NANO_EVT_EDGE_Pos)
4750#define REG_PTP_TS_EVT_7_NANO_EVT_EDGE_NEG (0x1 << REG_PTP_TS_EVT_7_NANO_EVT_EDGE_Pos)
4751
4752#define REG_PTP_TS_EVT_7_SEC 0x05AC
4753#define REG_PTP_TS_EVT_7_SEC_size 4
4754#define REG_PTP_TS_EVT_7_SEC_SEC_Pos 0
4755#define REG_PTP_TS_EVT_7_SEC_SEC_Msk (0xFFFFFFFF << REG_PTP_TS_EVT_7_SEC_SEC_Pos)
4756
4757#define REG_PTP_TS_EVT_7_PHASE 0x05B0
4758#define REG_PTP_TS_EVT_7_PHASE_size 4
4759#define REG_PTP_TS_EVT_7_PHASE_PHASE_Pos 0
4760#define REG_PTP_TS_EVT_7_PHASE_PHASE_Msk (0x7 << REG_PTP_TS_EVT_7_PHASE_PHASE_Pos)
4761
4762#define REG_PORT_DEFAULT_VID 0x0000
4763#define REG_PORT_DEFAULT_VID_size 2
4764#define REG_PORT_DEFAULT_VID_VID_Pos 0
4765#define REG_PORT_DEFAULT_VID_VID_Msk (0xFFF << REG_PORT_DEFAULT_VID_VID_Pos)
4766#define REG_PORT_DEFAULT_VID_VID(_x) (((_x) << REG_PORT_DEFAULT_VID_VID_Pos) &REG_PORT_DEFAULT_VID_VID_Msk)
4767#define REG_PORT_DEFAULT_VID_DEI_Pos 12
4768#define REG_PORT_DEFAULT_VID_DEI_Msk (0x1 << REG_PORT_DEFAULT_VID_DEI_Pos)
4769#define REG_PORT_DEFAULT_VID_DEI(_x) (((_x) << REG_PORT_DEFAULT_VID_DEI_Pos) &REG_PORT_DEFAULT_VID_DEI_Msk)
4770#define REG_PORT_DEFAULT_VID_PCP_Pos 13
4771#define REG_PORT_DEFAULT_VID_PCP_Msk (0x7 << REG_PORT_DEFAULT_VID_PCP_Pos)
4772#define REG_PORT_DEFAULT_VID_PCP(_x) (((_x) << REG_PORT_DEFAULT_VID_PCP_Pos) &REG_PORT_DEFAULT_VID_PCP_Msk)
4773
4774#define REG_PORT_CUSTOM_VID 0x0002
4775#define REG_PORT_CUSTOM_VID_size 2
4776#define REG_PORT_CUSTOM_VID_VID_Pos 0
4777#define REG_PORT_CUSTOM_VID_VID_Msk (0xFFF << REG_PORT_CUSTOM_VID_VID_Pos)
4778#define REG_PORT_CUSTOM_VID_VID(_x) (((_x) << REG_PORT_CUSTOM_VID_VID_Pos) &REG_PORT_CUSTOM_VID_VID_Msk)
4779#define REG_PORT_CUSTOM_VID_DEI_Pos 12
4780#define REG_PORT_CUSTOM_VID_DEI_Msk (0x1 << REG_PORT_CUSTOM_VID_DEI_Pos)
4781#define REG_PORT_CUSTOM_VID_DEI(_x) (((_x) << REG_PORT_CUSTOM_VID_DEI_Pos) &REG_PORT_CUSTOM_VID_DEI_Msk)
4782#define REG_PORT_CUSTOM_VID_PCP_Pos 13
4783#define REG_PORT_CUSTOM_VID_PCP_Msk (0x7 << REG_PORT_CUSTOM_VID_PCP_Pos)
4784#define REG_PORT_CUSTOM_VID_PCP(_x) (((_x) << REG_PORT_CUSTOM_VID_PCP_Pos) &REG_PORT_CUSTOM_VID_PCP_Msk)
4785
4786#define REG_PORT_AVB_SR_1_VID 0x0004
4787#define REG_PORT_AVB_SR_1_VID_size 2
4788#define REG_PORT_AVB_SR_1_VID_VID_Pos 0
4789#define REG_PORT_AVB_SR_1_VID_VID_Msk (0xFFF << REG_PORT_AVB_SR_1_VID_VID_Pos)
4790#define REG_PORT_AVB_SR_1_VID_VID(_x) (((_x) << REG_PORT_AVB_SR_1_VID_VID_Pos) &REG_PORT_AVB_SR_1_VID_VID_Msk)
4791#define REG_PORT_AVB_SR_1_VID_CFI_Pos 12
4792#define REG_PORT_AVB_SR_1_VID_CFI_Msk (0x1 << REG_PORT_AVB_SR_1_VID_CFI_Pos)
4793#define REG_PORT_AVB_SR_1_VID_CFI(_x) (((_x) << REG_PORT_AVB_SR_1_VID_CFI_Pos) &REG_PORT_AVB_SR_1_VID_CFI_Msk)
4794#define REG_PORT_AVB_SR_1_VID_PRIO_Pos 13
4795#define REG_PORT_AVB_SR_1_VID_PRIO_Msk (0x7 << REG_PORT_AVB_SR_1_VID_PRIO_Pos)
4796#define REG_PORT_AVB_SR_1_VID_PRIO(_x) (((_x) << REG_PORT_AVB_SR_1_VID_PRIO_Pos) &REG_PORT_AVB_SR_1_VID_PRIO_Msk)
4797
4798#define REG_PORT_AVB_SR_2_VID 0x0006
4799#define REG_PORT_AVB_SR_2_VID_size 2
4800#define REG_PORT_AVB_SR_2_VID_VID_Pos 0
4801#define REG_PORT_AVB_SR_2_VID_VID_Msk (0xFFF << REG_PORT_AVB_SR_2_VID_VID_Pos)
4802#define REG_PORT_AVB_SR_2_VID_VID(_x) (((_x) << REG_PORT_AVB_SR_2_VID_VID_Pos) &REG_PORT_AVB_SR_2_VID_VID_Msk)
4803#define REG_PORT_AVB_SR_2_VID_CFI_Pos 12
4804#define REG_PORT_AVB_SR_2_VID_CFI_Msk (0x1 << REG_PORT_AVB_SR_2_VID_CFI_Pos)
4805#define REG_PORT_AVB_SR_2_VID_CFI(_x) (((_x) << REG_PORT_AVB_SR_2_VID_CFI_Pos) &REG_PORT_AVB_SR_2_VID_CFI_Msk)
4806#define REG_PORT_AVB_SR_2_VID_PRIO_Pos 13
4807#define REG_PORT_AVB_SR_2_VID_PRIO_Msk (0x7 << REG_PORT_AVB_SR_2_VID_PRIO_Pos)
4808#define REG_PORT_AVB_SR_2_VID_PRIO(_x) (((_x) << REG_PORT_AVB_SR_2_VID_PRIO_Pos) &REG_PORT_AVB_SR_2_VID_PRIO_Msk)
4809
4810#define REG_PORT_AVB_SR_1_TYPE 0x0008
4811#define REG_PORT_AVB_SR_1_TYPE_size 2
4812#define REG_PORT_AVB_SR_2_TYPE 0x0008
4813#define REG_PORT_AVB_SR_2_TYPE_size 2
4814
4815#define REG_PORT_WOL_STATUS 0x0013
4816#define REG_PORT_WOL_STATUS_size 1
4817#define REG_PORT_WOL_STATUS_ENERGY_DETECTED_Pos 0
4818#define REG_PORT_WOL_STATUS_ENERGY_DETECTED_Msk (0x1 << REG_PORT_WOL_STATUS_ENERGY_DETECTED_Pos)
4819#define REG_PORT_WOL_STATUS_ENERGY_DETECTED (0x1 << REG_PORT_WOL_STATUS_ENERGY_DETECTED_Pos)
4820#define REG_PORT_WOL_STATUS_LINK_DETECTED_Pos 1
4821#define REG_PORT_WOL_STATUS_LINK_DETECTED_Msk (0x1 << REG_PORT_WOL_STATUS_LINK_DETECTED_Pos)
4822#define REG_PORT_WOL_STATUS_LINK_DETECTED (0x1 << REG_PORT_WOL_STATUS_LINK_DETECTED_Pos)
4823#define REG_PORT_WOL_STATUS_MAGIC_PKT_DETECTED_Pos 2
4824#define REG_PORT_WOL_STATUS_MAGIC_PKT_DETECTED_Msk (0x1 << REG_PORT_WOL_STATUS_MAGIC_PKT_DETECTED_Pos)
4825#define REG_PORT_WOL_STATUS_MAGIC_PKT_DETECTED (0x1 << REG_PORT_WOL_STATUS_MAGIC_PKT_DETECTED_Pos)
4826
4827#define REG_PORT_WOL_MASK 0x0017
4828#define REG_PORT_WOL_MASK_size 1
4829#define REG_PORT_WOL_MASK_ENERGY_Pos 0
4830#define REG_PORT_WOL_MASK_ENERGY_Msk (0x1 << REG_PORT_WOL_MASK_ENERGY_Pos)
4831#define REG_PORT_WOL_MASK_ENERGY_ENABLED (0x1 << REG_PORT_WOL_MASK_ENERGY_Pos)
4832#define REG_PORT_WOL_MASK_ENERGY_DISABLED (0x0 << REG_PORT_WOL_MASK_ENERGY_Pos)
4833#define REG_PORT_WOL_MASK_LINK_Pos 1
4834#define REG_PORT_WOL_MASK_LINK_Msk (0x1 << REG_PORT_WOL_MASK_LINK_Pos)
4835#define REG_PORT_WOL_MASK_LINK_ENABLED (0x1 << REG_PORT_WOL_MASK_LINK_Pos)
4836#define REG_PORT_WOL_MASK_LINK_DISABLED (0x0 << REG_PORT_WOL_MASK_LINK_Pos)
4837#define REG_PORT_WOL_MASK_MAGIC_PKT_Pos 2
4838#define REG_PORT_WOL_MASK_MAGIC_PKT_Msk (0x1 << REG_PORT_WOL_MASK_MAGIC_PKT_Pos)
4839#define REG_PORT_WOL_MASK_MAGIC_PKT_ENABLED (0x1 << REG_PORT_WOL_MASK_MAGIC_PKT_Pos)
4840#define REG_PORT_WOL_MASK_MAGIC_PKT_DISABLED (0x0 << REG_PORT_WOL_MASK_MAGIC_PKT_Pos)
4841
4842#define REG_PORT_INT_STATUS 0x001B
4843#define REG_PORT_INT_STATUS_size 1
4844#define REG_PORT_INT_STATUS_ACL_INT_Pos 0
4845#define REG_PORT_INT_STATUS_ACL_INT_Msk (0x1 << REG_PORT_INT_STATUS_ACL_INT_Pos)
4846#define REG_PORT_INT_STATUS_ACL_INT (0x1 << REG_PORT_INT_STATUS_ACL_INT_Pos)
4847#define REG_PORT_INT_STATUS_PHY_INT_Pos 1
4848#define REG_PORT_INT_STATUS_PHY_INT_Msk (0x1 << REG_PORT_INT_STATUS_PHY_INT_Pos)
4849#define REG_PORT_INT_STATUS_PHY_INT (0x1 << REG_PORT_INT_STATUS_PHY_INT_Pos)
4850#define REG_PORT_INT_STATUS_PTP_INT_Pos 2
4851#define REG_PORT_INT_STATUS_PTP_INT_Msk (0x1 << REG_PORT_INT_STATUS_PTP_INT_Pos)
4852#define REG_PORT_INT_STATUS_PTP_INT (0x1 << REG_PORT_INT_STATUS_PTP_INT_Pos)
4853#define REG_PORT_INT_STATUS_SGMII_INT_Pos 2
4854#define REG_PORT_INT_STATUS_SGMII_INT_Msk (0x1 << REG_PORT_INT_STATUS_SGMII_INT_Pos)
4855#define REG_PORT_INT_STATUS_SGMII_INT (0x1 << REG_PORT_INT_STATUS_SGMII_INT_Pos)
4856
4857#define REG_PORT_INT_MASK 0x001F
4858#define REG_PORT_INT_MASK_size 1
4859#define REG_PORT_INT_MASK_ACL_INT_Pos 0
4860#define REG_PORT_INT_MASK_ACL_INT_Msk (0x1 << REG_PORT_INT_MASK_ACL_INT_Pos)
4861#define REG_PORT_INT_MASK_ACL_INT_ENABLED (0x1 << REG_PORT_INT_MASK_ACL_INT_Pos)
4862#define REG_PORT_INT_MASK_ACL_INT_DISABLED (0x0 << REG_PORT_INT_MASK_ACL_INT_Pos)
4863#define REG_PORT_INT_MASK_PHY_INT_Pos 1
4864#define REG_PORT_INT_MASK_PHY_INT_Msk (0x1 << REG_PORT_INT_MASK_PHY_INT_Pos)
4865#define REG_PORT_INT_MASK_PHY_INT_ENABLED (0x1 << REG_PORT_INT_MASK_PHY_INT_Pos)
4866#define REG_PORT_INT_MASK_PHY_INT_DISABLED (0x0 << REG_PORT_INT_MASK_PHY_INT_Pos)
4867#define REG_PORT_INT_MASK_PTP_INT_Pos 2
4868#define REG_PORT_INT_MASK_PTP_INT_Msk (0x1 << REG_PORT_INT_MASK_PTP_INT_Pos)
4869#define REG_PORT_INT_MASK_PTP_INT_ENABLED (0x1 << REG_PORT_INT_MASK_PTP_INT_Pos)
4870#define REG_PORT_INT_MASK_PTP_INT_DISABLED (0x0 << REG_PORT_INT_MASK_PTP_INT_Pos)
4871#define REG_PORT_INT_MASK_SGMII_INT_Pos 2
4872#define REG_PORT_INT_MASK_SGMII_INT_Msk (0x1 << REG_PORT_INT_MASK_SGMII_INT_Pos)
4873#define REG_PORT_INT_MASK_SGMII_INT_ENABLED (0x1 << REG_PORT_INT_MASK_SGMII_INT_Pos)
4874#define REG_PORT_INT_MASK_SGMII_INT_DISABLED (0x0 << REG_PORT_INT_MASK_SGMII_INT_Pos)
4875
4876#define REG_PORT_CTRL 0x0020
4877#define REG_PORT_CTRL_size 4
4878#define REG_PORT_CTRL_SRP_ENABLE_Pos 16
4879#define REG_PORT_CTRL_SRP_ENABLE_Msk (0x3 << REG_PORT_CTRL_SRP_ENABLE_Pos)
4880#define REG_PORT_CTRL_SRP_ENABLE_NONE (0x0 << REG_PORT_CTRL_SRP_ENABLE_Pos)
4881#define REG_PORT_CTRL_SRP_ENABLE_SRP_1 (0x1 << REG_PORT_CTRL_SRP_ENABLE_Pos)
4882#define REG_PORT_CTRL_SRP_ENABLE_SRP_2 (0x2 << REG_PORT_CTRL_SRP_ENABLE_Pos)
4883#define REG_PORT_CTRL_QUEUE_SPLIT_Pos 24
4884#define REG_PORT_CTRL_QUEUE_SPLIT_Msk (0x3 << REG_PORT_CTRL_QUEUE_SPLIT_Pos)
4885#define REG_PORT_CTRL_QUEUE_SPLIT_SINGLE (0x0 << REG_PORT_CTRL_QUEUE_SPLIT_Pos)
4886#define REG_PORT_CTRL_QUEUE_SPLIT_DUAL (0x1 << REG_PORT_CTRL_QUEUE_SPLIT_Pos)
4887#define REG_PORT_CTRL_QUEUE_SPLIT_QUAD (0x2 << REG_PORT_CTRL_QUEUE_SPLIT_Pos)
4888#define REG_PORT_CTRL_TAIL_TAG_Pos 26
4889#define REG_PORT_CTRL_TAIL_TAG_Msk (0x3 << REG_PORT_CTRL_TAIL_TAG_Pos)
4890#define REG_PORT_CTRL_TAIL_TAG_DISABLED (0x0 << REG_PORT_CTRL_TAIL_TAG_Pos)
4891#define REG_PORT_CTRL_TAIL_TAG_ENABLED (0x1 << REG_PORT_CTRL_TAIL_TAG_Pos)
4892#define REG_PORT_CTRL_REMOTE_LOOPBACK_Pos 24
4893#define REG_PORT_CTRL_REMOTE_LOOPBACK_Msk (0x3 << REG_PORT_CTRL_REMOTE_LOOPBACK_Pos)
4894#define REG_PORT_CTRL_REMOTE_LOOPBACK_DISABLED (0x0 << REG_PORT_CTRL_REMOTE_LOOPBACK_Pos)
4895#define REG_PORT_CTRL_REMOTE_LOOPBACK_ENABLED (0x1 << REG_PORT_CTRL_REMOTE_LOOPBACK_Pos)
4896#define REG_PORT_CTRL_LOCAL_LOOPBACK_Pos 24
4897#define REG_PORT_CTRL_LOCAL_LOOPBACK_Msk (0x3 << REG_PORT_CTRL_LOCAL_LOOPBACK_Pos)
4898#define REG_PORT_CTRL_LOCAL_LOOPBACK_DISABLED (0x0 << REG_PORT_CTRL_LOCAL_LOOPBACK_Pos)
4899#define REG_PORT_CTRL_LOCAL_LOOPBACK_ENABLED (0x1 << REG_PORT_CTRL_LOCAL_LOOPBACK_Pos)
4900
4901#define REG_PORT_STATUS 0x0030
4902#define REG_PORT_STATUS_size 4
4903#define REG_PORT_STATUS_RX_FLOW_CTRL_Pos 24
4904#define REG_PORT_STATUS_RX_FLOW_CTRL_Msk (0x1 << REG_PORT_STATUS_RX_FLOW_CTRL_Pos)
4905#define REG_PORT_STATUS_RX_FLOW_CTRL_DISABLED (0x0 << REG_PORT_STATUS_RX_FLOW_CTRL_Pos)
4906#define REG_PORT_STATUS_RX_FLOW_CTRL_ENABLED (0x1 << REG_PORT_STATUS_RX_FLOW_CTRL_Pos)
4907#define REG_PORT_STATUS_TX_FLOW_CTRL_Pos 25
4908#define REG_PORT_STATUS_TX_FLOW_CTRL_Msk (0x3 << REG_PORT_STATUS_TX_FLOW_CTRL_Pos)
4909#define REG_PORT_STATUS_TX_FLOW_CTRL_DISABLED (0x0 << REG_PORT_STATUS_TX_FLOW_CTRL_Pos)
4910#define REG_PORT_STATUS_TX_FLOW_CTRL_ENABLED (0x1 << REG_PORT_STATUS_TX_FLOW_CTRL_Pos)
4911#define REG_PORT_STATUS_DUPLEX_Pos 26
4912#define REG_PORT_STATUS_DUPLEX_Msk (0x3 << REG_PORT_STATUS_DUPLEX_Pos)
4913#define REG_PORT_STATUS_DUPLEX_HALF (0x0 << REG_PORT_STATUS_DUPLEX_Pos)
4914#define REG_PORT_STATUS_DUPLEX_FULL (0x1 << REG_PORT_STATUS_DUPLEX_Pos)
4915#define REG_PORT_STATUS_SPEED_Pos 27
4916#define REG_PORT_STATUS_SPEED_Msk (0x3 << REG_PORT_STATUS_SPEED_Pos)
4917#define REG_PORT_STATUS_SPEED_10M (0x0 << REG_PORT_STATUS_SPEED_Pos)
4918#define REG_PORT_STATUS_SPEED_100M (0x1 << REG_PORT_STATUS_SPEED_Pos)
4919#define REG_PORT_STATUS_SPEED_1000M (0x2 << REG_PORT_STATUS_SPEED_Pos)
4920
4921#define REG_PHY_BASIC_CTL 0x0100
4922#define REG_PHY_BASIC_CTL_size 2
4923#define REG_PHY_BASIC_CTL_PHY_SPEED_100M_Pos 6
4924#define REG_PHY_BASIC_CTL_PHY_SPEED_100M_Msk (0x1 << REG_PHY_BASIC_CTL_PHY_SPEED_100M_Pos)
4925#define REG_PHY_BASIC_CTL_PHY_SPEED_100M_10M (0x0 << REG_PHY_BASIC_CTL_PHY_SPEED_100M_Pos)
4926#define REG_PHY_BASIC_CTL_PHY_SPEED_100M_100M (0x1 << REG_PHY_BASIC_CTL_PHY_SPEED_100M_Pos)
4927#define REG_PHY_BASIC_CTL_PHY_SPEED_100M_1000M (0x0 << REG_PHY_BASIC_CTL_PHY_SPEED_100M_Pos)
4928#define REG_PHY_BASIC_CTL_COL_TEST_Pos 7
4929#define REG_PHY_BASIC_CTL_COL_TEST_Msk (0x1 << REG_PHY_BASIC_CTL_COL_TEST_Pos)
4930#define REG_PHY_BASIC_CTL_COL_TEST_DISABLED (0x0 << REG_PHY_BASIC_CTL_COL_TEST_Pos)
4931#define REG_PHY_BASIC_CTL_COL_TEST_ENABLED (0x1 << REG_PHY_BASIC_CTL_COL_TEST_Pos)
4932#define REG_PHY_BASIC_CTL_DUPLEX_Pos 8
4933#define REG_PHY_BASIC_CTL_DUPLEX_Msk (0x1 << REG_PHY_BASIC_CTL_DUPLEX_Pos)
4934#define REG_PHY_BASIC_CTL_DUPLEX_HALF (0x0 << REG_PHY_BASIC_CTL_DUPLEX_Pos)
4935#define REG_PHY_BASIC_CTL_DUPLEX_FULl (0x1 << REG_PHY_BASIC_CTL_DUPLEX_Pos)
4936#define REG_PHY_BASIC_CTL_RESTART_AUTONEG_Pos 9
4937#define REG_PHY_BASIC_CTL_RESTART_AUTONEG_Msk (0x1 << REG_PHY_BASIC_CTL_RESTART_AUTONEG_Pos)
4938#define REG_PHY_BASIC_CTL_RESTART_AUTONEG (0x1 << REG_PHY_BASIC_CTL_RESTART_AUTONEG_Pos)
4939#define REG_PHY_BASIC_CTL_ISOLATE_Pos 10
4940#define REG_PHY_BASIC_CTL_ISOLATE_Msk (0x1 << REG_PHY_BASIC_CTL_ISOLATE_Pos)
4941#define REG_PHY_BASIC_CTL_ISOLATE_DISABLED (0x0 << REG_PHY_BASIC_CTL_ISOLATE_Pos)
4942#define REG_PHY_BASIC_CTL_ISOLATE_ENABLED (0x1 << REG_PHY_BASIC_CTL_ISOLATE_Pos)
4943#define REG_PHY_BASIC_CTL_POWER_DOWN_Pos 11
4944#define REG_PHY_BASIC_CTL_POWER_DOWN_Msk (0x1 << REG_PHY_BASIC_CTL_POWER_DOWN_Pos)
4945#define REG_PHY_BASIC_CTL_POWER_DOWN_DISABLED (0x0 << REG_PHY_BASIC_CTL_POWER_DOWN_Pos)
4946#define REG_PHY_BASIC_CTL_POWER_DOWN_ENABLED (0x1 << REG_PHY_BASIC_CTL_POWER_DOWN_Pos)
4947#define REG_PHY_BASIC_CTL_AUTONEG_Pos 12
4948#define REG_PHY_BASIC_CTL_AUTONEG_Msk (0x1 << REG_PHY_BASIC_CTL_AUTONEG_Pos)
4949#define REG_PHY_BASIC_CTL_AUTONEG_DISABLED (0x0 << REG_PHY_BASIC_CTL_AUTONEG_Pos)
4950#define REG_PHY_BASIC_CTL_AUTONEG_ENABLED (0x1 << REG_PHY_BASIC_CTL_AUTONEG_Pos)
4951#define REG_PHY_BASIC_CTL_PHY_SPEED_1000M_Pos 13
4952#define REG_PHY_BASIC_CTL_PHY_SPEED_1000M_Msk (0x1 << REG_PHY_BASIC_CTL_PHY_SPEED_1000M_Pos)
4953#define REG_PHY_BASIC_CTL_PHY_SPEED_1000M_10M (0x0 << REG_PHY_BASIC_CTL_PHY_SPEED_1000M_Pos)
4954#define REG_PHY_BASIC_CTL_PHY_SPEED_1000M_100M (0x0 << REG_PHY_BASIC_CTL_PHY_SPEED_1000M_Pos)
4955#define REG_PHY_BASIC_CTL_PHY_SPEED_1000M_1000M (0x1 << REG_PHY_BASIC_CTL_PHY_SPEED_1000M_Pos)
4956#define REG_PHY_BASIC_CTL_LOCAL_LOOPBACK_Pos 14
4957#define REG_PHY_BASIC_CTL_LOCAL_LOOPBACK_Msk (0x1 << REG_PHY_BASIC_CTL_LOCAL_LOOPBACK_Pos)
4958#define REG_PHY_BASIC_CTL_LOCAL_LOOPBACK_DISABLED (0x0 << REG_PHY_BASIC_CTL_LOCAL_LOOPBACK_Pos)
4959#define REG_PHY_BASIC_CTL_LOCAL_LOOPBACK_ENABLED (0x1 << REG_PHY_BASIC_CTL_LOCAL_LOOPBACK_Pos)
4960#define REG_PHY_BASIC_CTL_PHY_RESET_Pos 15
4961#define REG_PHY_BASIC_CTL_PHY_RESET_Msk (0x1 << REG_PHY_BASIC_CTL_PHY_RESET_Pos)
4962#define REG_PHY_BASIC_CTL_PHY_RESET (0x1 << REG_PHY_BASIC_CTL_PHY_RESET_Pos)
4963
4964#define REG_PHY_BASIC_ST 0x0102
4965#define REG_PHY_BASIC_ST_size 2
4966#define REG_PHY_BASIC_ST_CAPABILITY_Pos 0
4967#define REG_PHY_BASIC_ST_CAPABILITY_Msk (0x1 << REG_PHY_BASIC_ST_CAPABILITY_Pos)
4968#define REG_PHY_BASIC_ST_CAPABILITY_BASIC (0x0 << REG_PHY_BASIC_ST_CAPABILITY_Pos)
4969#define REG_PHY_BASIC_ST_CAPABILITY_EXTENDED (0x1 << REG_PHY_BASIC_ST_CAPABILITY_Pos)
4970#define REG_PHY_BASIC_ST_JABBER_Pos 1
4971#define REG_PHY_BASIC_ST_JABBER_Msk (0x1 << REG_PHY_BASIC_ST_JABBER_Pos)
4972#define REG_PHY_BASIC_ST_JABBER_NONE (0x0 << REG_PHY_BASIC_ST_JABBER_Pos)
4973#define REG_PHY_BASIC_ST_JABBER_DETECTED (0x1 << REG_PHY_BASIC_ST_JABBER_Pos)
4974#define REG_PHY_BASIC_ST_LINK_STATUS_Pos 2
4975#define REG_PHY_BASIC_ST_LINK_STATUS_Msk (0x1 << REG_PHY_BASIC_ST_LINK_STATUS_Pos)
4976#define REG_PHY_BASIC_ST_LINK_STATUS_DOWN (0x0 << REG_PHY_BASIC_ST_LINK_STATUS_Pos)
4977#define REG_PHY_BASIC_ST_LINK_STATUS_UP (0x1 << REG_PHY_BASIC_ST_LINK_STATUS_Pos)
4978#define REG_PHY_BASIC_ST_AUTONEG_CAPABLE_Pos 3
4979#define REG_PHY_BASIC_ST_AUTONEG_CAPABLE_Msk (0x1 << REG_PHY_BASIC_ST_AUTONEG_CAPABLE_Pos)
4980#define REG_PHY_BASIC_ST_AUTONEG_CAPABLE_NOT_CAPABLE (0x0 << REG_PHY_BASIC_ST_AUTONEG_CAPABLE_Pos)
4981#define REG_PHY_BASIC_ST_AUTONEG_CAPABLE_CAPABLE (0x1 << REG_PHY_BASIC_ST_AUTONEG_CAPABLE_Pos)
4982#define REG_PHY_BASIC_ST_REMOTE_FAULT_Pos 4
4983#define REG_PHY_BASIC_ST_REMOTE_FAULT_Msk (0x1 << REG_PHY_BASIC_ST_REMOTE_FAULT_Pos)
4984#define REG_PHY_BASIC_ST_REMOTE_FAULT_NONE (0x0 << REG_PHY_BASIC_ST_REMOTE_FAULT_Pos)
4985#define REG_PHY_BASIC_ST_REMOTE_FAULT_DETECTED (0x1 << REG_PHY_BASIC_ST_REMOTE_FAULT_Pos)
4986#define REG_PHY_BASIC_ST_AUTONEG_STATUS_Pos 5
4987#define REG_PHY_BASIC_ST_AUTONEG_STATUS_Msk (0x1 << REG_PHY_BASIC_ST_AUTONEG_STATUS_Pos)
4988#define REG_PHY_BASIC_ST_AUTONEG_STATUS_NOT_COMPLETE (0x0 << REG_PHY_BASIC_ST_AUTONEG_STATUS_Pos)
4989#define REG_PHY_BASIC_ST_AUTONEG_STATUS_COMPLETE (0x1 << REG_PHY_BASIC_ST_AUTONEG_STATUS_Pos)
4990#define REG_PHY_BASIC_ST_MF_PREAMBLE_SUPRESS_Pos 6
4991#define REG_PHY_BASIC_ST_MF_PREAMBLE_SUPRESS_Msk (0x1 << REG_PHY_BASIC_ST_MF_PREAMBLE_SUPRESS_Pos)
4992#define REG_PHY_BASIC_ST_MF_PREAMBLE_SUPRESS_NOT_SUPPORTED (0x0 << REG_PHY_BASIC_ST_MF_PREAMBLE_SUPRESS_Pos)
4993#define REG_PHY_BASIC_ST_MF_PREAMBLE_SUPRESS_SUPPORTED (0x1 << REG_PHY_BASIC_ST_MF_PREAMBLE_SUPRESS_Pos)
4994#define REG_PHY_BASIC_ST_EXT_STATUS_Pos 8
4995#define REG_PHY_BASIC_ST_EXT_STATUS_Msk (0x1 << REG_PHY_BASIC_ST_EXT_STATUS_Pos)
4996#define REG_PHY_BASIC_ST_EXT_STATUS_NOT_PRESENT (0x0 << REG_PHY_BASIC_ST_EXT_STATUS_Pos)
4997#define REG_PHY_BASIC_ST_EXT_STATUS_PRESENT (0x1 << REG_PHY_BASIC_ST_EXT_STATUS_Pos)
4998#define REG_PHY_BASIC_ST_100BT_HD_Pos 11
4999#define REG_PHY_BASIC_ST_100BT_HD_Msk (0x1 << REG_PHY_BASIC_ST_100BT_HD_Pos)
5000#define REG_PHY_BASIC_ST_100BT_HD_NOT_SUPPORTED (0x0 << REG_PHY_BASIC_ST_100BT_HD_Pos)
5001#define REG_PHY_BASIC_ST_100BT_HD_SUPPORTED (0x1 << REG_PHY_BASIC_ST_100BT_HD_Pos)
5002#define REG_PHY_BASIC_ST_10BT_FD_Pos 12
5003#define REG_PHY_BASIC_ST_10BT_FD_Msk (0x1 << REG_PHY_BASIC_ST_10BT_FD_Pos)
5004#define REG_PHY_BASIC_ST_10BT_FD_NOT_SUPPORTED (0x0 << REG_PHY_BASIC_ST_10BT_FD_Pos)
5005#define REG_PHY_BASIC_ST_10BT_FD_SUPPORTED (0x1 << REG_PHY_BASIC_ST_10BT_FD_Pos)
5006#define REG_PHY_BASIC_ST_100BTX_HD_Pos 13
5007#define REG_PHY_BASIC_ST_100BTX_HD_Msk (0x1 << REG_PHY_BASIC_ST_100BTX_HD_Pos)
5008#define REG_PHY_BASIC_ST_100BTX_HD_NOT_SUPPORTED (0x0 << REG_PHY_BASIC_ST_100BTX_HD_Pos)
5009#define REG_PHY_BASIC_ST_100BTX_HD_SUPPORTED (0x1 << REG_PHY_BASIC_ST_100BTX_HD_Pos)
5010#define REG_PHY_BASIC_ST_100BTX_FD_Pos 14
5011#define REG_PHY_BASIC_ST_100BTX_FD_Msk (0x1 << REG_PHY_BASIC_ST_100BTX_FD_Pos)
5012#define REG_PHY_BASIC_ST_100BTX_FD_NOT_SUPPORTED (0x0 << REG_PHY_BASIC_ST_100BTX_FD_Pos)
5013#define REG_PHY_BASIC_ST_100BTX_FD_SUPPORTED (0x1 << REG_PHY_BASIC_ST_100BTX_FD_Pos)
5014#define REG_PHY_BASIC_ST_100BT4_Pos 15
5015#define REG_PHY_BASIC_ST_100BT4_Msk (0x1 << REG_PHY_BASIC_ST_100BT4_Pos)
5016#define REG_PHY_BASIC_ST_100BT4_NOT_SUPPORTED (0x0 << REG_PHY_BASIC_ST_100BT4_Pos)
5017#define REG_PHY_BASIC_ST_100BT4_SUPPORTED (0x1 << REG_PHY_BASIC_ST_100BT4_Pos)
5018
5019#define REG_PHY_ID_1 0x0104
5020#define REG_PHY_ID_1_size 2
5021#define REG_PHY_ID_2 0x0106
5022#define REG_PHY_ID_2_size 2
5023
5024#define REG_PHY_A_NEG_ADVERT 0x0108
5025#define REG_PHY_A_NEG_ADVERT_size 2
5026#define REG_PHY_A_NEG_ADVERT_SELECTOR_Pos 0
5027#define REG_PHY_A_NEG_ADVERT_SELECTOR_Msk (0x1F << REG_PHY_A_NEG_ADVERT_SELECTOR_Pos)
5028#define REG_PHY_A_NEG_ADVERT_SELECTOR(_x) (((_x) << REG_PHY_A_NEG_ADVERT_SELECTOR_Pos) &REG_PHY_A_NEG_ADVERT_SELECTOR_Msk)
5029#define REG_PHY_A_NEG_ADVERT_10BT_HD_Pos 5
5030#define REG_PHY_A_NEG_ADVERT_10BT_HD_Msk (0x1 << REG_PHY_A_NEG_ADVERT_10BT_HD_Pos)
5031#define REG_PHY_A_NEG_ADVERT_10BT_HD_NOT_ALLOWED (0x0 << REG_PHY_A_NEG_ADVERT_10BT_HD_Pos)
5032#define REG_PHY_A_NEG_ADVERT_10BT_HD_ALLOWED (0x1 << REG_PHY_A_NEG_ADVERT_10BT_HD_Pos)
5033#define REG_PHY_A_NEG_ADVERT_10BT_FD_Pos 6
5034#define REG_PHY_A_NEG_ADVERT_10BT_FD_Msk (0x1 << REG_PHY_A_NEG_ADVERT_10BT_FD_Pos)
5035#define REG_PHY_A_NEG_ADVERT_10BT_FD_NOT_ALLOWED (0x0 << REG_PHY_A_NEG_ADVERT_10BT_FD_Pos)
5036#define REG_PHY_A_NEG_ADVERT_10BT_FD_ALLOWED (0x1 << REG_PHY_A_NEG_ADVERT_10BT_FD_Pos)
5037#define REG_PHY_A_NEG_ADVERT_100BTX_HD_Pos 7
5038#define REG_PHY_A_NEG_ADVERT_100BTX_HD_Msk (0x1 << REG_PHY_A_NEG_ADVERT_100BTX_HD_Pos)
5039#define REG_PHY_A_NEG_ADVERT_100BTX_HD_NOT_ALLOWED (0x0 << REG_PHY_A_NEG_ADVERT_100BTX_HD_Pos)
5040#define REG_PHY_A_NEG_ADVERT_100BTX_HD_ALLOWED (0x1 << REG_PHY_A_NEG_ADVERT_100BTX_HD_Pos)
5041#define REG_PHY_A_NEG_ADVERT_100BTX_FD_Pos 8
5042#define REG_PHY_A_NEG_ADVERT_100BTX_FD_Msk (0x1 << REG_PHY_A_NEG_ADVERT_100BTX_FD_Pos)
5043#define REG_PHY_A_NEG_ADVERT_100BTX_FD_NOT_ALLOWED (0x0 << REG_PHY_A_NEG_ADVERT_100BTX_FD_Pos)
5044#define REG_PHY_A_NEG_ADVERT_100BTX_FD_ALLOWED (0x1 << REG_PHY_A_NEG_ADVERT_100BTX_FD_Pos)
5045#define REG_PHY_A_NEG_ADVERT_100BT4_Pos 9
5046#define REG_PHY_A_NEG_ADVERT_100BT4_Msk (0x1 << REG_PHY_A_NEG_ADVERT_100BT4_Pos)
5047#define REG_PHY_A_NEG_ADVERT_100BT4_NOT_ALLOWED (0x0 << REG_PHY_A_NEG_ADVERT_100BT4_Pos)
5048#define REG_PHY_A_NEG_ADVERT_100BT4_ALLOWED (0x1 << REG_PHY_A_NEG_ADVERT_100BT4_Pos)
5049#define REG_PHY_A_NEG_ADVERT_SYM_PAUSE_Pos 10
5050#define REG_PHY_A_NEG_ADVERT_SYM_PAUSE_Msk (0x1 << REG_PHY_A_NEG_ADVERT_SYM_PAUSE_Pos)
5051#define REG_PHY_A_NEG_ADVERT_SYM_PAUSE_NOT_ALLOWED (0x0 << REG_PHY_A_NEG_ADVERT_SYM_PAUSE_Pos)
5052#define REG_PHY_A_NEG_ADVERT_SYM_PAUSE_ALLOWED (0x1 << REG_PHY_A_NEG_ADVERT_SYM_PAUSE_Pos)
5053#define REG_PHY_A_NEG_ADVERT_ASYM_PAUSE_Pos 11
5054#define REG_PHY_A_NEG_ADVERT_ASYM_PAUSE_Msk (0x1 << REG_PHY_A_NEG_ADVERT_ASYM_PAUSE_Pos)
5055#define REG_PHY_A_NEG_ADVERT_ASYM_PAUSE_NOT_ALLOWED (0x0 << REG_PHY_A_NEG_ADVERT_ASYM_PAUSE_Pos)
5056#define REG_PHY_A_NEG_ADVERT_ASYM_PAUSE_ALLOWED (0x1 << REG_PHY_A_NEG_ADVERT_ASYM_PAUSE_Pos)
5057#define REG_PHY_A_NEG_ADVERT_REMOTE_FAULT_Pos 13
5058#define REG_PHY_A_NEG_ADVERT_REMOTE_FAULT_Msk (0x1 << REG_PHY_A_NEG_ADVERT_REMOTE_FAULT_Pos)
5059#define REG_PHY_A_NEG_ADVERT_REMOTE_FAULT_NOT_CAPABLE (0x0 << REG_PHY_A_NEG_ADVERT_REMOTE_FAULT_Pos)
5060#define REG_PHY_A_NEG_ADVERT_REMOTE_FAULT_CAPABLE (0x1 << REG_PHY_A_NEG_ADVERT_REMOTE_FAULT_Pos)
5061#define REG_PHY_A_NEG_ADVERT_NEXT_PAGE_Pos 15
5062#define REG_PHY_A_NEG_ADVERT_NEXT_PAGE_Msk (0x1 << REG_PHY_A_NEG_ADVERT_NEXT_PAGE_Pos)
5063#define REG_PHY_A_NEG_ADVERT_NEXT_PAGE_NOT_CAPABLE (0x0 << REG_PHY_A_NEG_ADVERT_NEXT_PAGE_Pos)
5064#define REG_PHY_A_NEG_ADVERT_NEXT_PAGE_CAPABLE (0x1 << REG_PHY_A_NEG_ADVERT_NEXT_PAGE_Pos)
5065
5066#define REG_PHY_A_NEG_LPA 0x010A
5067#define REG_PHY_A_NEG_LPA_size 2
5068#define REG_PHY_A_NEG_LPA_SELECTOR_Pos 0
5069#define REG_PHY_A_NEG_LPA_SELECTOR_Msk (0x1F << REG_PHY_A_NEG_LPA_SELECTOR_Pos)
5070#define REG_PHY_A_NEG_LPA_SELECTOR(_x) (((_x) << REG_PHY_A_NEG_LPA_SELECTOR_Pos) &REG_PHY_A_NEG_LPA_SELECTOR_Msk)
5071#define REG_PHY_A_NEG_LPA_10BT_HD_Pos 5
5072#define REG_PHY_A_NEG_LPA_10BT_HD_Msk (0x1 << REG_PHY_A_NEG_LPA_10BT_HD_Pos)
5073#define REG_PHY_A_NEG_LPA_10BT_HD_NOT_ALLOWED (0x0 << REG_PHY_A_NEG_LPA_10BT_HD_Pos)
5074#define REG_PHY_A_NEG_LPA_10BT_HD_ALLOWED (0x1 << REG_PHY_A_NEG_LPA_10BT_HD_Pos)
5075#define REG_PHY_A_NEG_LPA_10BT_FD_Pos 6
5076#define REG_PHY_A_NEG_LPA_10BT_FD_Msk (0x1 << REG_PHY_A_NEG_LPA_10BT_FD_Pos)
5077#define REG_PHY_A_NEG_LPA_10BT_FD_NOT_ALLOWED (0x0 << REG_PHY_A_NEG_LPA_10BT_FD_Pos)
5078#define REG_PHY_A_NEG_LPA_10BT_FD_ALLOWED (0x1 << REG_PHY_A_NEG_LPA_10BT_FD_Pos)
5079#define REG_PHY_A_NEG_LPA_100BTX_HD_Pos 7
5080#define REG_PHY_A_NEG_LPA_100BTX_HD_Msk (0x1 << REG_PHY_A_NEG_LPA_100BTX_HD_Pos)
5081#define REG_PHY_A_NEG_LPA_100BTX_HD_NOT_ALLOWED (0x0 << REG_PHY_A_NEG_LPA_100BTX_HD_Pos)
5082#define REG_PHY_A_NEG_LPA_100BTX_HD_ALLOWED (0x1 << REG_PHY_A_NEG_LPA_100BTX_HD_Pos)
5083#define REG_PHY_A_NEG_LPA_100BTX_FD_Pos 8
5084#define REG_PHY_A_NEG_LPA_100BTX_FD_Msk (0x1 << REG_PHY_A_NEG_LPA_100BTX_FD_Pos)
5085#define REG_PHY_A_NEG_LPA_100BTX_FD_NOT_ALLOWED (0x0 << REG_PHY_A_NEG_LPA_100BTX_FD_Pos)
5086#define REG_PHY_A_NEG_LPA_100BTX_FD_ALLOWED (0x1 << REG_PHY_A_NEG_LPA_100BTX_FD_Pos)
5087#define REG_PHY_A_NEG_LPA_100BT4_Pos 9
5088#define REG_PHY_A_NEG_LPA_100BT4_Msk (0x1 << REG_PHY_A_NEG_LPA_100BT4_Pos)
5089#define REG_PHY_A_NEG_LPA_100BT4_NOT_ALLOWED (0x0 << REG_PHY_A_NEG_LPA_100BT4_Pos)
5090#define REG_PHY_A_NEG_LPA_100BT4_ALLOWED (0x1 << REG_PHY_A_NEG_LPA_100BT4_Pos)
5091#define REG_PHY_A_NEG_LPA_SYM_PAUSE_Pos 10
5092#define REG_PHY_A_NEG_LPA_SYM_PAUSE_Msk (0x1 << REG_PHY_A_NEG_LPA_SYM_PAUSE_Pos)
5093#define REG_PHY_A_NEG_LPA_SYM_PAUSE_NOT_ALLOWED (0x0 << REG_PHY_A_NEG_LPA_SYM_PAUSE_Pos)
5094#define REG_PHY_A_NEG_LPA_SYM_PAUSE_ALLOWED (0x1 << REG_PHY_A_NEG_LPA_SYM_PAUSE_Pos)
5095#define REG_PHY_A_NEG_LPA_ASYM_PAUSE_Pos 11
5096#define REG_PHY_A_NEG_LPA_ASYM_PAUSE_Msk (0x1 << REG_PHY_A_NEG_LPA_ASYM_PAUSE_Pos)
5097#define REG_PHY_A_NEG_LPA_ASYM_PAUSE_NOT_ALLOWED (0x0 << REG_PHY_A_NEG_LPA_ASYM_PAUSE_Pos)
5098#define REG_PHY_A_NEG_LPA_ASYM_PAUSE_ALLOWED (0x1 << REG_PHY_A_NEG_LPA_ASYM_PAUSE_Pos)
5099#define REG_PHY_A_NEG_LPA_REMOTE_FAULT_Pos 13
5100#define REG_PHY_A_NEG_LPA_REMOTE_FAULT_Msk (0x1 << REG_PHY_A_NEG_LPA_REMOTE_FAULT_Pos)
5101#define REG_PHY_A_NEG_LPA_REMOTE_FAULT_NONE (0x0 << REG_PHY_A_NEG_LPA_REMOTE_FAULT_Pos)
5102#define REG_PHY_A_NEG_LPA_REMOTE_FAULT_DETECTED (0x1 << REG_PHY_A_NEG_LPA_REMOTE_FAULT_Pos)
5103#define REG_PHY_A_NEG_LPA_REMOTE_ACKNOWLEDGE_Pos 14
5104#define REG_PHY_A_NEG_LPA_REMOTE_ACKNOWLEDGE_Msk (0x1 << REG_PHY_A_NEG_LPA_REMOTE_FAULT_Pos)
5105#define REG_PHY_A_NEG_LPA_REMOTE_ACKNOWLEDGE_NONE (0x0 << REG_PHY_A_NEG_LPA_REMOTE_FAULT_Pos)
5106#define REG_PHY_A_NEG_LPA_REMOTE_ACKNOWLEDGE_ACKED (0x1 << REG_PHY_A_NEG_LPA_REMOTE_FAULT_Pos)
5107#define REG_PHY_A_NEG_LPA_NEXT_PAGE_Pos 15
5108#define REG_PHY_A_NEG_LPA_NEXT_PAGE_Msk (0x1F << REG_PHY_A_NEG_LPA_NEXT_PAGE_Pos)
5109#define REG_PHY_A_NEG_LPA_NEXT_PAGE_NOT_CAPABLE (0x0 << REG_PHY_A_NEG_LPA_NEXT_PAGE_Pos)
5110#define REG_PHY_A_NEG_LPA_NEXT_PAGE_CAPABLE (0x1 << REG_PHY_A_NEG_LPA_NEXT_PAGE_Pos)
5111
5112#define REG_PHY_A_NEG_EXP 0x010C
5113#define REG_PHY_A_NEG_EXP_size 2
5114#define REG_PHY_A_NEG_EXP_LP_A_NEG_Pos 0
5115#define REG_PHY_A_NEG_EXP_LP_A_NEG_Msk (0x1 << REG_PHY_A_NEG_EXP_LP_A_NEG_Pos)
5116#define REG_PHY_A_NEG_EXP_LP_A_NEG_NOT_CAPABLE (0x0 << REG_PHY_A_NEG_EXP_LP_A_NEG_Pos) &REG_PHY_A_NEG_EXP_LP_A_NEG_Msk
5117#define REG_PHY_A_NEG_EXP_LP_A_NEG_CAPABLE (0x1 << REG_PHY_A_NEG_EXP_LP_A_NEG_Pos) &REG_PHY_A_NEG_EXP_LP_A_NEG_Msk
5118#define REG_PHY_A_NEG_EXP_PAGE_RX_Pos 1
5119#define REG_PHY_A_NEG_EXP_PAGE_RX_Msk (0x1 << REG_PHY_A_NEG_EXP_PAGE_RX_Pos)
5120#define REG_PHY_A_NEG_EXP_PAGE_RX_WAITING (0x0 << REG_PHY_A_NEG_EXP_PAGE_RX_Pos) &REG_PHY_A_NEG_EXP_PAGE_RX_Msk
5121#define REG_PHY_A_NEG_EXP_PAGE_RX_RXED (0x1 << REG_PHY_A_NEG_EXP_PAGE_RX_Pos) &REG_PHY_A_NEG_EXP_PAGE_RX_Msk
5122#define REG_PHY_A_NEG_EXP_LOCAL_NEXT_PAGE_Pos 2
5123#define REG_PHY_A_NEG_EXP_LOCAL_NEXT_PAGE_Msk (0x1 << REG_PHY_A_NEG_EXP_LOCAL_NEXT_PAGE_Pos)
5124#define REG_PHY_A_NEG_EXP_LOCAL_NEXT_PAGE_NOT_CAPABLE (0x0 << REG_PHY_A_NEG_EXP_LOCAL_NEXT_PAGE_Pos) &REG_PHY_A_NEG_EXP_LOCAL_NEXT_PAGE_Msk
5125#define REG_PHY_A_NEG_EXP_LOCAL_NEXT_PAGE_CAPABLE (0x1 << REG_PHY_A_NEG_EXP_LOCAL_NEXT_PAGE_Pos) &REG_PHY_A_NEG_EXP_LOCAL_NEXT_PAGE_Msk
5126#define REG_PHY_A_NEG_EXP_LPA_NEXT_PAGE_Pos 3
5127#define REG_PHY_A_NEG_EXP_LPA_NEXT_PAGE_Msk (0x1 << REG_PHY_A_NEG_EXP_LPA_NEXT_PAGE_Pos)
5128#define REG_PHY_A_NEG_EXP_LPA_NEXT_PAGE_NOT_CAPABLE (0x0 << REG_PHY_A_NEG_EXP_LPA_NEXT_PAGE_Pos) &REG_PHY_A_NEG_EXP_LPA_NEXT_PAGE_Msk
5129#define REG_PHY_A_NEG_EXP_LPA_NEXT_PAGE_CAPABLE (0x1 << REG_PHY_A_NEG_EXP_LPA_NEXT_PAGE_Pos) &REG_PHY_A_NEG_EXP_LPA_NEXT_PAGE_Msk
5130#define REG_PHY_A_NEG_EXP_PARALLEL_FAULT_Pos 0
5131#define REG_PHY_A_NEG_EXP_PARALLEL_FAULT_Msk (0x1 << REG_PHY_A_NEG_EXP_PARALLEL_FAULT_Pos)
5132#define REG_PHY_A_NEG_EXP_PARALLEL_FAULT_NONE (0x0 << REG_PHY_A_NEG_EXP_PARALLEL_FAULT_Pos) &REG_PHY_A_NEG_EXP_PARALLEL_FAULT_Msk
5133#define REG_PHY_A_NEG_EXP_PARALLEL_FAULT_DETECTED (0x1 << REG_PHY_A_NEG_EXP_PARALLEL_FAULT_Pos) &REG_PHY_A_NEG_EXP_PARALLEL_FAULT_Msk
5134
5135#define REG_PHY_A_NEG_NEXT_PG 0x010E
5136#define REG_PHY_A_NEG_NEXT_PG_size 2
5137#define REG_PHY_A_NEG_NEXT_PG_MESSAGE_Pos 0
5138#define REG_PHY_A_NEG_NEXT_PG_MESSAGE_Msk (0x7FF << REG_PHY_A_NEG_NEXT_PG_MESSAGE_Pos)
5139#define REG_PHY_A_NEG_NEXT_PG_MESSAGE(_x) (((_x) << REG_PHY_A_NEG_NEXT_PG_MESSAGE_Pos) &REG_PHY_A_NEG_NEXT_PG_MESSAGE_Msk)
5140#define REG_PHY_A_NEG_NEXT_PG_TOGGLE_Pos 11
5141#define REG_PHY_A_NEG_NEXT_PG_TOGGLE_Msk (0x1 << REG_PHY_A_NEG_NEXT_PG_TOGGLE_Pos)
5142#define REG_PHY_A_NEG_NEXT_PG_TOGGLE(_x) (((_x) << REG_PHY_A_NEG_NEXT_PG_TOGGLE_Pos) &REG_PHY_A_NEG_NEXT_PG_TOGGLE_Msk)
5143#define REG_PHY_A_NEG_NEXT_PG_ACKNOWLEDGE2_Pos 12
5144#define REG_PHY_A_NEG_NEXT_PG_ACKNOWLEDGE2_Msk (0x1 << REG_PHY_A_NEG_NEXT_PG_ACKNOWLEDGE2_Pos)
5145#define REG_PHY_A_NEG_NEXT_PG_ACKNOWLEDGE2_NACK (0x0 << REG_PHY_A_NEG_NEXT_PG_ACKNOWLEDGE2_Pos)
5146#define REG_PHY_A_NEG_NEXT_PG_ACKNOWLEDGE2_ACK (0x1 << REG_PHY_A_NEG_NEXT_PG_ACKNOWLEDGE2_Pos)
5147#define REG_PHY_A_NEG_NEXT_PG_PAGE_TYPE_Pos 13
5148#define REG_PHY_A_NEG_NEXT_PG_PAGE_TYPE_Msk (0x1 << REG_PHY_A_NEG_NEXT_PG_PAGE_TYPE_Pos)
5149#define REG_PHY_A_NEG_NEXT_PG_PAGE_TYPE_UNFORMATTED (0x0 << REG_PHY_A_NEG_NEXT_PG_PAGE_TYPE_Pos)
5150#define REG_PHY_A_NEG_NEXT_PG_PAGE_TYPE_MESSAGE (0x1 << REG_PHY_A_NEG_NEXT_PG_PAGE_TYPE_Pos)
5151#define REG_PHY_A_NEG_NEXT_PG_NEXT_PAGE_Pos 15
5152#define REG_PHY_A_NEG_NEXT_PG_NEXT_PAGE_Msk (0x1 << REG_PHY_A_NEG_NEXT_PG_NEXT_PAGE_Pos)
5153#define REG_PHY_A_NEG_NEXT_PG_NEXT_PAGE_LAST (0x0 << REG_PHY_A_NEG_NEXT_PG_NEXT_PAGE_Pos)
5154#define REG_PHY_A_NEG_NEXT_PG_NEXT_PAGE_MORE_FOLLOW (0x1 << REG_PHY_A_NEG_NEXT_PG_NEXT_PAGE_Pos)
5155
5156#define REG_PHY_LP_NEXT_PG_ABIL 0x0110
5157#define REG_PHY_LP_NEXT_PG_ABIL_size 2
5158#define REG_PHY_LP_NEXT_PG_ABIL_MESSAGE_Pos 0
5159#define REG_PHY_LP_NEXT_PG_ABIL_MESSAGE_Msk (0x7FF << REG_PHY_LP_NEXT_PG_ABIL_MESSAGE_Pos)
5160#define REG_PHY_LP_NEXT_PG_ABIL_MESSAGE(_x) (((_x) << REG_PHY_LP_NEXT_PG_ABIL_MESSAGE_Pos) &REG_PHY_LP_NEXT_PG_ABIL_MESSAGE_Msk)
5161#define REG_PHY_LP_NEXT_PG_ABIL_TOGGLE_Pos 11
5162#define REG_PHY_LP_NEXT_PG_ABIL_TOGGLE_Msk (0x1 << REG_PHY_LP_NEXT_PG_ABIL_TOGGLE_Pos)
5163#define REG_PHY_LP_NEXT_PG_ABIL_TOGGLE(_x) (((_x) << REG_PHY_LP_NEXT_PG_ABIL_TOGGLE_Pos) &REG_PHY_LP_NEXT_PG_ABIL_TOGGLE_Msk)
5164#define REG_PHY_LP_NEXT_PG_ABIL_ACKNOWLEDGE2_Pos 12
5165#define REG_PHY_LP_NEXT_PG_ABIL_ACKNOWLEDGE2_Msk (0x1 << REG_PHY_LP_NEXT_PG_ABIL_ACKNOWLEDGE2_Pos)
5166#define REG_PHY_LP_NEXT_PG_ABIL_ACKNOWLEDGE2_NACK (0x0 << REG_PHY_LP_NEXT_PG_ABIL_ACKNOWLEDGE2_Pos)
5167#define REG_PHY_LP_NEXT_PG_ABIL_ACKNOWLEDGE2_ACK (0x1 << REG_PHY_LP_NEXT_PG_ABIL_ACKNOWLEDGE2_Pos)
5168#define REG_PHY_LP_NEXT_PG_ABIL_PAGE_TYPE_Pos 13
5169#define REG_PHY_LP_NEXT_PG_ABIL_PAGE_TYPE_Msk (0x1 << REG_PHY_LP_NEXT_PG_ABIL_PAGE_TYPE_Pos)
5170#define REG_PHY_LP_NEXT_PG_ABIL_PAGE_TYPE_UNFORMATTED (0x0 << REG_PHY_LP_NEXT_PG_ABIL_PAGE_TYPE_Pos)
5171#define REG_PHY_LP_NEXT_PG_ABIL_PAGE_TYPE_MESSAGE (0x1 << REG_PHY_LP_NEXT_PG_ABIL_PAGE_TYPE_Pos)
5172#define REG_PHY_LP_NEXT_PG_ABIL_ACKNOWLEDGE_Pos 14
5173#define REG_PHY_LP_NEXT_PG_ABIL_ACKNOWLEDGE_Msk (0x1 << REG_PHY_LP_NEXT_PG_ABIL_ACKNOWLEDGE_Pos)
5174#define REG_PHY_LP_NEXT_PG_ABIL_ACKNOWLEDGE_NACK (0x0 << REG_PHY_LP_NEXT_PG_ABIL_ACKNOWLEDGE_Pos)
5175#define REG_PHY_LP_NEXT_PG_ABIL_ACKNOWLEDGE_ACK (0x1 << REG_PHY_LP_NEXT_PG_ABIL_ACKNOWLEDGE_Pos)
5176#define REG_PHY_LP_NEXT_PG_ABIL_NEXT_PAGE_Pos 15
5177#define REG_PHY_LP_NEXT_PG_ABIL_NEXT_PAGE_Msk (0x1 << REG_PHY_LP_NEXT_PG_ABIL_NEXT_PAGE_Pos)
5178#define REG_PHY_LP_NEXT_PG_ABIL_NEXT_PAGE_LAST (0x0 << REG_PHY_LP_NEXT_PG_ABIL_NEXT_PAGE_Pos)
5179#define REG_PHY_LP_NEXT_PG_ABIL_NEXT_PAGE_MORE_FOLLOW (0x1 << REG_PHY_LP_NEXT_PG_ABIL_NEXT_PAGE_Pos)
5180
5181#define REG_PHY_GBCR 0x0112
5182#define REG_PHY_GBCR_size 2
5183#define REG_PHY_GBCR_1000BT_HD_Pos 8
5184#define REG_PHY_GBCR_1000BT_HD_Msk (0x1 << REG_PHY_GBCR_1000BT_HD_Pos)
5185#define REG_PHY_GBCR_1000BT_HD_NOT_CAPABLE (0x0 << REG_PHY_GBCR_1000BT_HD_Pos)
5186#define REG_PHY_GBCR_1000BT_HD_CAPABLE (0x1 << REG_PHY_GBCR_1000BT_HD_Pos)
5187#define REG_PHY_GBCR_1000BT_FD_Pos 9
5188#define REG_PHY_GBCR_1000BT_FD_Msk (0x1 << REG_PHY_GBCR_1000BT_FD_Pos)
5189#define REG_PHY_GBCR_1000BT_FD_NOT_CAPABLE (0x0 << REG_PHY_GBCR_1000BT_FD_Pos)
5190#define REG_PHY_GBCR_1000BT_FD_CAPABLE (0x1 << REG_PHY_GBCR_1000BT_FD_Pos)
5191#define REG_PHY_GBCR_DEVICE_TYPE_Pos 10
5192#define REG_PHY_GBCR_DEVICE_TYPE_Msk (0x1 << REG_PHY_GBCR_DEVICE_TYPE_Pos)
5193#define REG_PHY_GBCR_DEVICE_TYPE_SINGLE_PORT (0x0 << REG_PHY_GBCR_DEVICE_TYPE_Pos)
5194#define REG_PHY_GBCR_DEVICE_TYPE_MULTI_PORT (0x1 << REG_PHY_GBCR_DEVICE_TYPE_Pos)
5195#define REG_PHY_GBCR_MANUAL_ROLE_CFG_Pos 11
5196#define REG_PHY_GBCR_MANUAL_ROLE_CFG_Msk (0x1 << REG_PHY_GBCR_MANUAL_ROLE_CFG_Pos)
5197#define REG_PHY_GBCR_MANUAL_ROLE_CFG_SLAVE (0x0 << REG_PHY_GBCR_MANUAL_ROLE_CFG_Pos)
5198#define REG_PHY_GBCR_MANUAL_ROLE_CFG_MASTER (0x1 << REG_PHY_GBCR_MANUAL_ROLE_CFG_Pos)
5199#define REG_PHY_GBCR_MANUAL_ROLE_Pos 12
5200#define REG_PHY_GBCR_MANUAL_ROLE_Msk (0x1 << REG_PHY_GBCR_MANUAL_ROLE_Pos)
5201#define REG_PHY_GBCR_MANUAL_ROLE_DISABLED (0x0 << REG_PHY_GBCR_MANUAL_ROLE_Pos)
5202#define REG_PHY_GBCR_MANUAL_ROLE_ENABLED (0x1 << REG_PHY_GBCR_MANUAL_ROLE_Pos)
5203#define REG_PHY_GBCR_TX_TEST_MODE_Pos 13
5204#define REG_PHY_GBCR_TX_TEST_MODE_Msk (0x7 << REG_PHY_GBCR_TX_TEST_MODE_Pos)
5205#define REG_PHY_GBCR_TX_TEST_MODE_NORMAL_OPS (0x0 << REG_PHY_GBCR_TX_TEST_MODE_Pos)
5206#define REG_PHY_GBCR_TX_TEST_MODE_MODE_1_WAVE (0x1 << REG_PHY_GBCR_TX_TEST_MODE_Pos)
5207#define REG_PHY_GBCR_TX_TEST_MODE_MODE_2_JITTER_MASTER (0x2 << REG_PHY_GBCR_TX_TEST_MODE_Pos)
5208#define REG_PHY_GBCR_TX_TEST_MODE_MODE_3_JITTER_SLAVE (0x3 << REG_PHY_GBCR_TX_TEST_MODE_Pos)
5209#define REG_PHY_GBCR_TX_TEST_MODE_MODE_4_DISTORTION (0x4 << REG_PHY_GBCR_TX_TEST_MODE_Pos)
5210
5211#define REG_PHY_GBSR 0x0114
5212#define REG_PHY_GBSR_size 2
5213#define REG_PHY_GBSR_IDLE_ERR_CNT_Pos 0
5214#define REG_PHY_GBSR_IDLE_ERR_CNT_Msk (0xFF << REG_PHY_GBSR_IDLE_ERR_CNT_Pos)
5215#define REG_PHY_GBSR_LP_1000BT_HD_Pos 10
5216#define REG_PHY_GBSR_LP_1000BT_HD_Msk (0x1 << REG_PHY_GBSR_LP_1000BT_HD_Pos)
5217#define REG_PHY_GBSR_LP_1000BT_HD_NOT_CAPABLE (0x0 << REG_PHY_GBSR_LP_1000BT_HD_Pos)
5218#define REG_PHY_GBSR_LP_1000BT_HD_CAPABLE (0x1 << REG_PHY_GBSR_LP_1000BT_HD_Pos)
5219#define REG_PHY_GBSR_LP_1000BT_FD_Pos 11
5220#define REG_PHY_GBSR_LP_1000BT_FD_Msk (0x1 << REG_PHY_GBSR_LP_1000BT_FD_Pos)
5221#define REG_PHY_GBSR_LP_1000BT_FD_NOT_CAPABLE (0x0 << REG_PHY_GBSR_LP_1000BT_FD_Pos)
5222#define REG_PHY_GBSR_LP_1000BT_FD_CAPABLE (0x1 << REG_PHY_GBSR_LP_1000BT_FD_Pos)
5223#define REG_PHY_GBSR_REMOTE_RX_STAT_Pos 12
5224#define REG_PHY_GBSR_REMOTE_RX_STAT_Msk (0x1 << REG_PHY_GBSR_REMOTE_RX_STAT_Pos)
5225#define REG_PHY_GBSR_REMOTE_RX_STAT_NOT_OK (0x0 << REG_PHY_GBSR_REMOTE_RX_STAT_Pos)
5226#define REG_PHY_GBSR_REMOTE_RX_STAT_OK (0x1 << REG_PHY_GBSR_REMOTE_RX_STAT_Pos)
5227#define REG_PHY_GBSR_LOCAL_RX_STAT_Pos 13
5228#define REG_PHY_GBSR_LOCAL_RX_STAT_Msk (0x1 << REG_PHY_GBSR_LOCAL_RX_STAT_Pos)
5229#define REG_PHY_GBSR_LOCAL_RX_STAT_NOT_OK (0x0 << REG_PHY_GBSR_LOCAL_RX_STAT_Pos)
5230#define REG_PHY_GBSR_LOCAL_RX_STAT_OK (0x1 << REG_PHY_GBSR_LOCAL_RX_STAT_Pos)
5231#define REG_PHY_GBSR_LOCAL_ROLE_Pos 14
5232#define REG_PHY_GBSR_LOCAL_ROLE_Msk (0x1 << REG_PHY_GBSR_LOCAL_ROLE_Pos)
5233#define REG_PHY_GBSR_LOCAL_ROLE_SLAVE (0x0 << REG_PHY_GBSR_LOCAL_ROLE_Pos)
5234#define REG_PHY_GBSR_LOCAL_ROLE_MASTER (0x1 << REG_PHY_GBSR_LOCAL_ROLE_Pos)
5235#define REG_PHY_GBSR_ROLE_FAULT_Pos 15
5236#define REG_PHY_GBSR_ROLE_FAULT_Msk (0x1 << REG_PHY_GBSR_ROLE_FAULT_Pos)
5237#define REG_PHY_GBSR_ROLE_FAULT_NONE (0x0 << REG_PHY_GBSR_ROLE_FAULT_Pos)
5238#define REG_PHY_GBSR_ROLE_FAULT_DETECTED (0x1 << REG_PHY_GBSR_ROLE_FAULT_Pos)
5239
5240#define REG_PHY_MMD_SETUP 0x011A
5241#define REG_PHY_MMD_SETUP_size 2
5242#define REG_PHY_MMD_SETUP_DEV_ADDR_Pos 0
5243#define REG_PHY_MMD_SETUP_DEV_ADDR_Msk (0x1F << REG_PHY_MMD_SETUP_DEV_ADDR_Pos)
5244#define REG_PHY_MMD_SETUP_DEV_ADDR(_x) (((_x) << REG_PHY_MMD_SETUP_DEV_ADDR_Pos) &REG_PHY_MMD_SETUP_DEV_ADDR_Pos)
5245#define REG_PHY_MMD_SETUP_OP_MODE_Pos 14
5246#define REG_PHY_MMD_SETUP_OP_MODE_Msk (0x3 << REG_PHY_MMD_SETUP_OP_MODE_Pos)
5247#define REG_PHY_MMD_SETUP_OP_MODE(_x) (((_x) << REG_PHY_MMD_SETUP_OP_MODE_Pos) &REG_PHY_MMD_SETUP_OP_MODE_Pos)
5248#define REG_PHY_MMD_SETUP_OP_MODE_REGISTER (0x00 << REG_PHY_MMD_SETUP_OP_MODE_Pos)
5249#define REG_PHY_MMD_SETUP_OP_MODE_DATA (0x01 << REG_PHY_MMD_SETUP_OP_MODE_Pos)
5250#define REG_PHY_MMD_SETUP_OP_MODE_DATA_INCR (0x02 << REG_PHY_MMD_SETUP_OP_MODE_Pos)
5251#define REG_PHY_MMD_SETUP_OP_MODE_DATA_INCR_WRITE (0x03 << REG_PHY_MMD_SETUP_OP_MODE_Pos)
5252
5253
5254#define REG_PHY_MMD_DATA 0x011C
5255#define REG_PHY_MMD_DATA_size 2
5256
5257#define MMD_DEVICE_ID_DSP 1
5258
5259#define MMD_DSP_SQI_CHAN_A 0xAC
5260#define MMD_DSP_SQI_CHAN_B 0xAD
5261#define MMD_DSP_SQI_CHAN_C 0xAE
5262#define MMD_DSP_SQI_CHAN_D 0xAF
5263
5264#define DSP_SQI_ERR_DETECTED (1 << 15)
5265#define DSP_SQI_AVG_ERR 0x7FFF
5266
5267#define MMD_DEVICE_ID_COMMON 2
5268
5269#define MMD_DEVICE_ID_EEE_ADV 7
5270
5271#define MMD_EEE_ADV 0x3C
5272#define EEE_ADV_100MBIT (1 << 1)
5273#define EEE_ADV_1GBIT (1 << 2)
5274
5275#define MMD_EEE_LP_ADV 0x3D
5276#define MMD_EEE_MSG_CODE 0x3F
5277
5278#define MMD_DEVICE_ID_AFED 0x1C
5279
5280#define REG_PORT_PHY_EXTENDED_STATUS 0x011E
5281
5282#define PORT_100BTX_FD_ABLE (1 << 15)
5283#define PORT_100BTX_ABLE (1 << 14)
5284#define PORT_10BT_FD_ABLE (1 << 13)
5285#define PORT_10BT_ABLE (1 << 12)
5286
5287#define REG_PORT_SGMII_ADDR__4 0x0200
5288#define PORT_SGMII_AUTO_INCR (1 << 23)
5289#define PORT_SGMII_DEVICE_ID_M 0x1F
5290#define PORT_SGMII_DEVICE_ID_S 16
5291#define PORT_SGMII_ADDR_M ((1 << 21) - 1)
5292
5293#define REG_PORT_SGMII_DATA__4 0x0204
5294#define PORT_SGMII_DATA_M ((1 << 16) - 1)
5295
5296#define MMD_DEVICE_ID_PMA 0x01
5297#define MMD_DEVICE_ID_PCS 0x03
5298#define MMD_DEVICE_ID_PHY_XS 0x04
5299#define MMD_DEVICE_ID_DTE_XS 0x05
5300#define MMD_DEVICE_ID_AN 0x07
5301#define MMD_DEVICE_ID_VENDOR_CTRL 0x1E
5302#define MMD_DEVICE_ID_VENDOR_MII 0x1F
5303
5304
5305#define REG_PHY_EXT_STATUS 0x011E
5306#define REG_PHY_EXT_STATUS_size 2
5307#define REG_PHY_EXT_STATUS_1000BT_HD_Pos 12
5308#define REG_PHY_EXT_STATUS_1000BT_HD_Msk (0x1 << REG_PHY_EXT_STATUS_1000BT_HD_Pos)
5309#define REG_PHY_EXT_STATUS_1000BT_HD_NOT_CAPABLE (0x0 << REG_PHY_EXT_STATUS_1000BT_HD_Pos)
5310#define REG_PHY_EXT_STATUS_1000BT_HD_CAPABLE (0x1 << REG_PHY_EXT_STATUS_1000BT_HD_Pos)
5311#define REG_PHY_EXT_STATUS_1000BT_FD_Pos 13
5312#define REG_PHY_EXT_STATUS_1000BT_FD_Msk (0x1 << REG_PHY_EXT_STATUS_1000BT_FD_Pos)
5313#define REG_PHY_EXT_STATUS_1000BT_FD_NOT_CAPABLE (0x0 << REG_PHY_EXT_STATUS_1000BT_FD_Pos)
5314#define REG_PHY_EXT_STATUS_1000BT_FD_CAPABLE (0x1 << REG_PHY_EXT_STATUS_1000BT_FD_Pos)
5315#define REG_PHY_EXT_STATUS_1000BX_HD_Pos 14
5316#define REG_PHY_EXT_STATUS_1000BX_HD_Msk (0x1 << REG_PHY_EXT_STATUS_1000BX_HD_Pos)
5317#define REG_PHY_EXT_STATUS_1000BX_HD_NOT_CAPABLE (0x0 << REG_PHY_EXT_STATUS_1000BX_HD_Pos)
5318#define REG_PHY_EXT_STATUS_1000BX_HD_CAPABLE (0x1 << REG_PHY_EXT_STATUS_1000BX_HD_Pos)
5319#define REG_PHY_EXT_STATUS_1000BX_FD_Pos 15
5320#define REG_PHY_EXT_STATUS_1000BX_FD_Msk (0x1 << REG_PHY_EXT_STATUS_1000BX_FD_Pos)
5321#define REG_PHY_EXT_STATUS_1000BX_FD_NOT_CAPABLE (0x0 << REG_PHY_EXT_STATUS_1000BX_FD_Pos)
5322#define REG_PHY_EXT_STATUS_1000BX_FD_CAPABLE (0x1 << REG_PHY_EXT_STATUS_1000BX_FD_Pos)
5323
5324#define REG_PHY_REMOTE_LOOPBACK 0x0122
5325#define REG_PHY_REMOTE_LOOPBACK_size 2
5326#define REG_PHY_REMOTE_LOOPBACK_LINK_MD_PASS_Pos 0
5327#define REG_PHY_REMOTE_LOOPBACK_LINK_MD_PASS_Msk (0x1 << REG_PHY_REMOTE_LOOPBACK_LINK_MD_PASS_Pos)
5328#define REG_PHY_REMOTE_LOOPBACK_LINK_MD_PASS_DISABLED (0x0 << REG_PHY_REMOTE_LOOPBACK_LINK_MD_PASS_Pos)
5329#define REG_PHY_REMOTE_LOOPBACK_LINK_MD_PASS_ENABLED (0x1 << REG_PHY_REMOTE_LOOPBACK_LINK_MD_PASS_Pos)
5330#define REG_PHY_REMOTE_LOOPBACK_LINK_MD_10BT_Pos 1
5331#define REG_PHY_REMOTE_LOOPBACK_LINK_MD_10BT_Msk (0x1 << REG_PHY_REMOTE_LOOPBACK_LINK_MD_10BT_Pos)
5332#define REG_PHY_REMOTE_LOOPBACK_LINK_MD_10BT_DISABLED (0x0 << REG_PHY_REMOTE_LOOPBACK_LINK_MD_10BT_Pos)
5333#define REG_PHY_REMOTE_LOOPBACK_LINK_MD_10BT_ENABLED (0x1 << REG_PHY_REMOTE_LOOPBACK_LINK_MD_10BT_Pos)
5334#define REG_PHY_REMOTE_LOOPBACK_10BT_PREAMBLE_Pos 2
5335#define REG_PHY_REMOTE_LOOPBACK_10BT_PREAMBLE_Msk (0x1 << REG_PHY_REMOTE_LOOPBACK_10BT_PREAMBLE_Pos)
5336#define REG_PHY_REMOTE_LOOPBACK_10BT_PREAMBLE_DISABLED (0x0 << REG_PHY_REMOTE_LOOPBACK_10BT_PREAMBLE_Pos)
5337#define REG_PHY_REMOTE_LOOPBACK_10BT_PREAMBLE_ENABLED (0x1 << REG_PHY_REMOTE_LOOPBACK_10BT_PREAMBLE_Pos)
5338#define REG_PHY_REMOTE_LOOPBACK_LED_CTRL_TEST_Pos 3
5339#define REG_PHY_REMOTE_LOOPBACK_LED_CTRL_TEST_Msk (0x1 << REG_PHY_REMOTE_LOOPBACK_LED_CTRL_TEST_Pos)
5340#define REG_PHY_REMOTE_LOOPBACK_LED_CTRL_TEST_DISABLED (0x0 << REG_PHY_REMOTE_LOOPBACK_LED_CTRL_TEST_Pos)
5341#define REG_PHY_REMOTE_LOOPBACK_LED_CTRL_TEST_ENABLED (0x1 << REG_PHY_REMOTE_LOOPBACK_LED_CTRL_TEST_Pos)
5342#define REG_PHY_REMOTE_LOOPBACK_LED_CTRL_Pos 4
5343#define REG_PHY_REMOTE_LOOPBACK_LED_CTRL_Msk (0x1 << REG_PHY_REMOTE_LOOPBACK_LED_CTRL_Pos)
5344#define REG_PHY_REMOTE_LOOPBACK_LED_CTRL_DISABLED (0x0 << REG_PHY_REMOTE_LOOPBACK_LED_CTRL_Pos)
5345#define REG_PHY_REMOTE_LOOPBACK_LED_CTRL_ENABLED (0x1 << REG_PHY_REMOTE_LOOPBACK_LED_CTRL_Pos)
5346#define REG_PHY_REMOTE_LOOPBACK_LED_SEL_Pos 6
5347#define REG_PHY_REMOTE_LOOPBACK_LED_SEL_Msk (0x1 << REG_PHY_REMOTE_LOOPBACK_LED_SEL_Pos)
5348#define REG_PHY_REMOTE_LOOPBACK_LED_SEL_DISABLED (0x0 << REG_PHY_REMOTE_LOOPBACK_LED_SEL_Pos)
5349#define REG_PHY_REMOTE_LOOPBACK_LED_SEL_ENABLED (0x1 << REG_PHY_REMOTE_LOOPBACK_LED_SEL_Pos)
5350#define REG_PHY_REMOTE_LOOPBACK_REMOTE_LOOPBACK_Pos 8
5351#define REG_PHY_REMOTE_LOOPBACK_REMOTE_LOOPBACK_Msk (0x1 << REG_PHY_REMOTE_LOOPBACK_REMOTE_LOOPBACK_Pos)
5352#define REG_PHY_REMOTE_LOOPBACK_REMOTE_LOOPBACK_DISABLED (0x0 << REG_PHY_REMOTE_LOOPBACK_REMOTE_LOOPBACK_Pos)
5353#define REG_PHY_REMOTE_LOOPBACK_REMOTE_LOOPBACK_ENABLED (0x1 << REG_PHY_REMOTE_LOOPBACK_REMOTE_LOOPBACK_Pos)
5354
5355#define REG_PHY_LINK_MD 0x0124
5356#define REG_PHY_LINK_MD_size 2
5357#define REG_PHY_LINK_MD_CABLE_STATUS_Pos 8
5358#define REG_PHY_LINK_MD_CABLE_STATUS_Msk (0x3 << REG_PHY_LINK_MD_CABLE_STATUS_Pos)
5359#define REG_PHY_LINK_MD_CABLE_STATUS_NORMAL (0x0 << REG_PHY_LINK_MD_CABLE_STATUS_Pos)
5360#define REG_PHY_LINK_MD_CABLE_STATUS_OPEN (0x1 << REG_PHY_LINK_MD_CABLE_STATUS_Pos)
5361#define REG_PHY_LINK_MD_CABLE_STATUS_SHORT (0x2 << REG_PHY_LINK_MD_CABLE_STATUS_Pos)
5362#define REG_PHY_LINK_MD_TEST_PAIR_Pos 12
5363#define REG_PHY_LINK_MD_TEST_PAIR_Msk (0x3 << REG_PHY_LINK_MD_TEST_PAIR_Pos)
5364#define REG_PHY_LINK_MD_TEST_PAIR_A (0x0 << REG_PHY_LINK_MD_TEST_PAIR_Pos)
5365#define REG_PHY_LINK_MD_TEST_PAIR_B (0x1 << REG_PHY_LINK_MD_TEST_PAIR_Pos)
5366#define REG_PHY_LINK_MD_TEST_PAIR_C (0x2 << REG_PHY_LINK_MD_TEST_PAIR_Pos)
5367#define REG_PHY_LINK_MD_TEST_PAIR_D (0x3 << REG_PHY_LINK_MD_TEST_PAIR_Pos)
5368#define REG_PHY_LINK_MD_LINX_TX_Pos 14
5369#define REG_PHY_LINK_MD_LINX_TX_Msk (0x1 << REG_PHY_LINK_MD_LINX_TX_Pos)
5370#define REG_PHY_LINK_MD_LINX_TX_ENABLED (0x0 << REG_PHY_LINK_MD_LINX_TX_Pos)
5371#define REG_PHY_LINK_MD_LINX_TX_DISABLED (0x1 << REG_PHY_LINK_MD_LINX_TX_Pos)
5372#define REG_PHY_LINK_MD_CABLE_TEST_Pos 15
5373#define REG_PHY_LINK_MD_CABLE_TEST_Msk (0x1 << REG_PHY_LINK_MD_CABLE_TEST_Pos)
5374#define REG_PHY_LINK_MD_CABLE_TEST_DONE (0x0 << REG_PHY_LINK_MD_CABLE_TEST_Pos)
5375#define REG_PHY_LINK_MD_CABLE_TEST_DISABLED (0x0 << REG_PHY_LINK_MD_CABLE_TEST_Pos)
5376#define REG_PHY_LINK_MD_CABLE_TEST_ENABLED (0x1 << REG_PHY_LINK_MD_CABLE_TEST_Pos)
5377#define REG_PHY_LINK_MD_CABLE_TEST_IN_PROGRESS (0x1 << REG_PHY_LINK_MD_CABLE_TEST_Pos)
5378
5379#define REG_PHY_PMA_STATUS 0x0126
5380#define REG_PHY_PMA_STATUS_size 2
5381#define REG_PHY_PMA_STATUS_100BTX_LINK_STATUS_Pos 0
5382#define REG_PHY_PMA_STATUS_100BTX_LINK_STATUS_Msk (0x3 << REG_PHY_PMA_STATUS_100BTX_LINK_STATUS_Pos)
5383#define REG_PHY_PMA_STATUS_100BTX_LINK_STATUS_DOWN (0x0 << REG_PHY_PMA_STATUS_100BTX_LINK_STATUS_Pos)
5384#define REG_PHY_PMA_STATUS_100BTX_LINK_STATUS_UP (0x1 << REG_PHY_PMA_STATUS_100BTX_LINK_STATUS_Pos)
5385#define REG_PHY_PMA_STATUS_1000BT_LINK_STATUS_Pos 0
5386#define REG_PHY_PMA_STATUS_1000BT_LINK_STATUS_Msk (0x3 << REG_PHY_PMA_STATUS_1000BT_LINK_STATUS_Pos)
5387#define REG_PHY_PMA_STATUS_1000BT_LINK_STATUS_DOWN (0x0 << REG_PHY_PMA_STATUS_1000BT_LINK_STATUS_Pos)
5388#define REG_PHY_PMA_STATUS_1000BT_LINK_STATUS_UP (0x1 << REG_PHY_PMA_STATUS_1000BT_LINK_STATUS_Pos)
5389
5390#define REG_PHY_RXER_CNT 0x012A
5391#define REG_PHY_RXER_CNT_size 2
5392
5393#define REG_PHY_INT 0x0136
5394#define REG_PHY_INT_size 2
5395#define REG_PHY_INT_LINK_UP_IRQ_Pos 0
5396#define REG_PHY_INT_LINK_UP_IRQ_Msk (0x1 << REG_PHY_INT_LINK_UP_IRQ_Pos)
5397#define REG_PHY_INT_REMOTE_FAULT_IRQ_Pos 1
5398#define REG_PHY_INT_REMOTE_FAULT_IRQ_Msk (0x1 << REG_PHY_INT_REMOTE_FAULT_IRQ_Pos)
5399#define REG_PHY_INT_LINK_DOWN_IRQ_Pos 2
5400#define REG_PHY_INT_LINK_DOWN_IRQ_Msk (0x1 << REG_PHY_INT_LINK_DOWN_IRQ_Pos)
5401#define REG_PHY_INT_LP_ACK_IRQ_Pos 3
5402#define REG_PHY_INT_LP_ACK_IRQ_Msk (0x1 << REG_PHY_INT_LP_ACK_IRQ_Pos)
5403#define REG_PHY_INT_PARALLEL_FAULT_IRQ_Pos 4
5404#define REG_PHY_INT_PARALLEL_FAULT_IRQ_Msk (0x1 << REG_PHY_INT_PARALLEL_FAULT_IRQ_Pos)
5405#define REG_PHY_INT_PG_RX_IRQ_Pos 5
5406#define REG_PHY_INT_PG_RX_IRQ_Msk (0x1 << REG_PHY_INT_PG_RX_IRQ_Pos)
5407#define REG_PHY_INT_RX_ERR_IRQ_Pos 6
5408#define REG_PHY_INT_RX_ERR_IRQ_Msk (0x1 << REG_PHY_INT_RX_ERR_IRQ_Pos)
5409#define REG_PHY_INT_JABBER_IRQ_Pos 7
5410#define REG_PHY_INT_JABBER_IRQ_Msk (0x1 << REG_PHY_INT_JABBER_IRQ_Pos)
5411#define REG_PHY_INT_LINK_UP_Pos 8
5412#define REG_PHY_INT_LINK_UP_Msk (0x1 << REG_PHY_INT_LINK_UP_Pos)
5413#define REG_PHY_INT_LINK_UP_DISABLED (0x0 << REG_PHY_INT_LINK_UP_Pos)
5414#define REG_PHY_INT_LINK_UP_ENABLED (0x1 << REG_PHY_INT_LINK_UP_Pos)
5415#define REG_PHY_INT_REMOTE_FAULT_Pos 9
5416#define REG_PHY_INT_REMOTE_FAULT_Msk (0x1 << REG_PHY_INT_REMOTE_FAULT_Pos)
5417#define REG_PHY_INT_REMOTE_FAULT_DISABLED (0x0 << REG_PHY_INT_REMOTE_FAULT_Pos)
5418#define REG_PHY_INT_REMOTE_FAULT_ENABLED (0x1 << REG_PHY_INT_REMOTE_FAULT_Pos)
5419#define REG_PHY_INT_LINK_DOWN_Pos 10
5420#define REG_PHY_INT_LINK_DOWN_Msk (0x1 << REG_PHY_INT_LINK_DOWN_Pos)
5421#define REG_PHY_INT_LINK_DOWN_DISABLED (0x0 << REG_PHY_INT_LINK_DOWN_Pos)
5422#define REG_PHY_INT_LINK_DOWN_ENABLED (0x1 << REG_PHY_INT_LINK_DOWN_Pos)
5423#define REG_PHY_INT_PARALLEL_FAULT_Pos 11
5424#define REG_PHY_INT_PARALLEL_FAULT_Msk (0x1 << REG_PHY_INT_PARALLEL_FAULT_Pos)
5425#define REG_PHY_INT_PARALLEL_FAULT_DISABLED (0x0 << REG_PHY_INT_PARALLEL_FAULT_Pos)
5426#define REG_PHY_INT_PARALLEL_FAULT_ENABLED (0x1 << REG_PHY_INT_PARALLEL_FAULT_Pos)
5427#define REG_PHY_INT_PG_RX_Pos 12
5428#define REG_PHY_INT_PG_RX_Msk (0x1 << REG_PHY_INT_PG_RX_Pos)
5429#define REG_PHY_INT_PG_RX_DISABLED (0x0 << REG_PHY_INT_PG_RX_Pos)
5430#define REG_PHY_INT_PG_RX_ENABLED (0x1 << REG_PHY_INT_PG_RX_Pos)
5431#define REG_PHY_INT_RX_ERR_Pos 13
5432#define REG_PHY_INT_RX_ERR_Msk (0x1 << REG_PHY_INT_RX_ERR_Pos)
5433#define REG_PHY_INT_RX_ERR_DISABLED (0x0 << REG_PHY_INT_RX_ERR_Pos)
5434#define REG_PHY_INT_RX_ERR_ENABLED (0x1 << REG_PHY_INT_RX_ERR_Pos)
5435#define REG_PHY_INT_JABBER_Pos 14
5436#define REG_PHY_INT_JABBER_Msk (0x1 << REG_PHY_INT_JABBER_Pos)
5437#define REG_PHY_INT_JABBER_DISABLED (0x0 << REG_PHY_INT_JABBER_Pos)
5438#define REG_PHY_INT_JABBER_ENABLED (0x1 << REG_PHY_INT_JABBER_Pos)
5439#define REG_PHY_INT_100BTX_LINK_STATUS_Pos 15
5440#define REG_PHY_INT_100BTX_LINK_STATUS_Msk (0x1 << REG_PHY_INT_100BTX_LINK_STATUS_Pos)
5441#define REG_PHY_INT_100BTX_LINK_STATUS_DISABLED (0x0 << REG_PHY_INT_100BTX_LINK_STATUS_Pos)
5442#define REG_PHY_INT_100BTX_LINK_STATUS_ENABLED (0x1 << REG_PHY_INT_100BTX_LINK_STATUS_Pos)
5443
5444#define REG_PHY_AUTO_MDIX 0x0138
5445#define REG_PHY_AUTO_MDIX_size 2
5446#define REG_PHY_AUTO_MDIX_AUTO_MDIX_DISABLE_Pos 6
5447#define REG_PHY_AUTO_MDIX_AUTO_MDIX_DISABLE_Msk (0x1 << REG_PHY_AUTO_MDIX_AUTO_MDIX_DISABLE_Pos)
5448#define REG_PHY_AUTO_MDIX_AUTO_MDIX_DISABLE_DISABLED (0x1 << REG_PHY_AUTO_MDIX_AUTO_MDIX_DISABLE_Pos)
5449#define REG_PHY_AUTO_MDIX_AUTO_MDIX_DISABLE_ENABLED (0x0 << REG_PHY_AUTO_MDIX_AUTO_MDIX_DISABLE_Pos)
5450#define REG_PHY_AUTO_MDIX_MDI_MODE_Pos 7
5451#define REG_PHY_AUTO_MDIX_MDI_MODE_Msk (0x1 << REG_PHY_AUTO_MDIX_MDI_MODE_Pos)
5452#define REG_PHY_AUTO_MDIX_MDI_MODE_MDI (0x0 << REG_PHY_AUTO_MDIX_MDI_MODE_Pos)
5453#define REG_PHY_AUTO_MDIX_MDI_MODE_MDIX (0x1 << REG_PHY_AUTO_MDIX_MDI_MODE_Pos)
5454
5455#define REG_PHY_CTL_2 0x013E
5456#define REG_PHY_CTL_2_size 2
5457#define REG_PHY_CTL_2_1000BT_ROLE_Pos 2
5458#define REG_PHY_CTL_2_1000BT_ROLE_Msk (0x1 << REG_PHY_CTL_2_1000BT_ROLE_Pos)
5459#define REG_PHY_CTL_2_1000BT_ROLE_MASTER (0x1 << REG_PHY_CTL_2_1000BT_ROLE_Pos)
5460#define REG_PHY_CTL_2_1000BT_ROLE_SLAVE (0x0 << REG_PHY_CTL_2_1000BT_ROLE_Pos)
5461#define REG_PHY_CTL_2_DUPLEX_Pos 3
5462#define REG_PHY_CTL_2_DUPLEX_Msk (0x1 << REG_PHY_CTL_2_DUPLEX_Pos)
5463#define REG_PHY_CTL_2_DUPLEX_FULL (0x1 << REG_PHY_CTL_2_DUPLEX_Pos)
5464#define REG_PHY_CTL_2_DUPLEX_HALF (0x0 << REG_PHY_CTL_2_DUPLEX_Pos)
5465#define REG_PHY_CTL_2_SPEED_IS_10BT_Pos 4
5466#define REG_PHY_CTL_2_SPEED_IS_10BT_Msk (0x1 << REG_PHY_CTL_2_SPEED_IS_10BT_Pos)
5467#define REG_PHY_CTL_2_SPEED_IS_10BT_TRUE (0x1 << REG_PHY_CTL_2_SPEED_IS_10BT_Pos)
5468#define REG_PHY_CTL_2_SPEED_IS_10BT_FALSE (0x0 << REG_PHY_CTL_2_SPEED_IS_10BT_Pos)
5469#define REG_PHY_CTL_2_SPEED_IS_100BTX_Pos 5
5470#define REG_PHY_CTL_2_SPEED_IS_100BTX_Msk (0x1 << REG_PHY_CTL_2_SPEED_IS_100BTX_Pos)
5471#define REG_PHY_CTL_2_SPEED_IS_100BTX_TRUE (0x1 << REG_PHY_CTL_2_SPEED_IS_100BTX_Pos)
5472#define REG_PHY_CTL_2_SPEED_IS_100BTX_FALSE (0x0 << REG_PHY_CTL_2_SPEED_IS_100BTX_Pos)
5473#define REG_PHY_CTL_2_SPEED_IS_1000BT_Pos 6
5474#define REG_PHY_CTL_2_SPEED_IS_1000BT_Msk (0x1 << REG_PHY_CTL_2_SPEED_IS_1000BT_Pos)
5475#define REG_PHY_CTL_2_SPEED_IS_1000BT_TRUE (0x1 << REG_PHY_CTL_2_SPEED_IS_1000BT_Pos)
5476#define REG_PHY_CTL_2_SPEED_IS_1000BT_FALSE (0x0 << REG_PHY_CTL_2_SPEED_IS_1000BT_Pos)
5477#define REG_PHY_CTL_2_JABBER_COUNTER_Pos 9
5478#define REG_PHY_CTL_2_JABBER_COUNTER_Msk (0x1 << REG_PHY_CTL_2_JABBER_COUNTER_Pos)
5479#define REG_PHY_CTL_2_JABBER_COUNTER_DISABLED (0x0 << REG_PHY_CTL_2_JABBER_COUNTER_Pos)
5480#define REG_PHY_CTL_2_JABBER_COUNTER_ENABLED (0x1 << REG_PHY_CTL_2_JABBER_COUNTER_Pos)
5481
5482#define REG_PORT_XMII_CTRL 0x0300
5483#define REG_PORT_XMII_CTRL_size 4
5484#define REG_PORT_XMII_CTRL_RGMII_IBS_LINK_STATUS_Pos 0
5485#define REG_PORT_XMII_CTRL_RGMII_IBS_LINK_STATUS_Msk (0x1 << REG_PORT_XMII_CTRL_RGMII_IBS_LINK_STATUS_Pos)
5486#define REG_PORT_XMII_CTRL_RGMII_IBS_LINK_STATUS_UP (0x1 << REG_PORT_XMII_CTRL_RGMII_IBS_LINK_STATUS_Pos)
5487#define REG_PORT_XMII_CTRL_RGMII_IBS_LINK_STATUS_DOWN (0x0 << REG_PORT_XMII_CTRL_RGMII_IBS_LINK_STATUS_Pos)
5488#define REG_PORT_XMII_CTRL_RGMII_IBS_RCLK_SPD_Pos 1
5489#define REG_PORT_XMII_CTRL_RGMII_IBS_RCLK_SPD_Msk (0x3 << REG_PORT_XMII_CTRL_RGMII_IBS_RCLK_SPD_Pos)
5490#define REG_PORT_XMII_CTRL_RGMII_IBS_RCLK_SPD_2_5M (0x0 << REG_PORT_XMII_CTRL_RGMII_IBS_RCLK_SPD_Pos)
5491#define REG_PORT_XMII_CTRL_RGMII_IBS_RCLK_SPD_25M (0x1 << REG_PORT_XMII_CTRL_RGMII_IBS_RCLK_SPD_Pos)
5492#define REG_PORT_XMII_CTRL_RGMII_IBS_RCLK_SPD_125M (0x2 << REG_PORT_XMII_CTRL_RGMII_IBS_RCLK_SPD_Pos)
5493#define REG_PORT_XMII_CTRL_RGMII_IBS_DUPLEX_Pos 3
5494#define REG_PORT_XMII_CTRL_RGMII_IBS_DUPLEX_Msk (0x1 << REG_PORT_XMII_CTRL_RGMII_IBS_DUPLEX_Pos)
5495#define REG_PORT_XMII_CTRL_RGMII_IBS_DUPLEX_FULL (0x1 << REG_PORT_XMII_CTRL_RGMII_IBS_DUPLEX_Pos)
5496#define REG_PORT_XMII_CTRL_RGMII_IBS_DUPLEX_HALF (0x0 << REG_PORT_XMII_CTRL_RGMII_IBS_DUPLEX_Pos)
5497#define REG_PORT_XMII_CTRL_MII_MODE_Pos 16
5498#define REG_PORT_XMII_CTRL_MII_MODE_Msk (0x3 << REG_PORT_XMII_CTRL_MII_MODE_Pos)
5499#define REG_PORT_XMII_CTRL_MII_MODE_MII (0x0 << REG_PORT_XMII_CTRL_MII_MODE_Pos)
5500#define REG_PORT_XMII_CTRL_MII_MODE_RMII (0x1 << REG_PORT_XMII_CTRL_MII_MODE_Pos)
5501#define REG_PORT_XMII_CTRL_MII_MODE_GMII (0x2 << REG_PORT_XMII_CTRL_MII_MODE_Pos)
5502#define REG_PORT_XMII_CTRL_MII_MODE_RGMII (0x3 << REG_PORT_XMII_CTRL_MII_MODE_Pos)
5503#define REG_PORT_XMII_CTRL_MII_CFG_Pos 18
5504#define REG_PORT_XMII_CTRL_MII_CFG_Msk (0x1 << REG_PORT_XMII_CTRL_MII_CFG_Pos)
5505#define REG_PORT_XMII_CTRL_MII_CFG_MII_PHY (0x0 << REG_PORT_XMII_CTRL_MII_CFG_Pos)
5506#define REG_PORT_XMII_CTRL_MII_CFG_MII_MAC (0x1 << REG_PORT_XMII_CTRL_MII_CFG_Pos)
5507#define REG_PORT_XMII_CTRL_MII_CFG_RMII_CLK_IN (0x0 << REG_PORT_XMII_CTRL_MII_CFG_Pos)
5508#define REG_PORT_XMII_CTRL_MII_CFG_RMII_CLK_OUT (0x1 << REG_PORT_XMII_CTRL_MII_CFG_Pos)
5509#define REG_PORT_XMII_CTRL_MII_CFG_RGMII_IBS_DISABLED (0x0 << REG_PORT_XMII_CTRL_MII_CFG_Pos)
5510#define REG_PORT_XMII_CTRL_MII_CFG_RGMII_IBS_ENABLED (0x1 << REG_PORT_XMII_CTRL_MII_CFG_Pos)
5511#define REG_PORT_XMII_CTRL_RGMII_EGRESS_DLY_Pos 19
5512#define REG_PORT_XMII_CTRL_RGMII_EGRESS_DLY_Msk (0x1 << REG_PORT_XMII_CTRL_RGMII_EGRESS_DLY_Pos)
5513#define REG_PORT_XMII_CTRL_RGMII_EGRESS_DLY_ENABLED (0x1 << REG_PORT_XMII_CTRL_RGMII_EGRESS_DLY_Pos)
5514#define REG_PORT_XMII_CTRL_RGMII_EGRESS_DLY_DISABLED (0x0 << REG_PORT_XMII_CTRL_RGMII_EGRESS_DLY_Pos)
5515#define REG_PORT_XMII_CTRL_RGMII_INGRESS_DLY_Pos 20
5516#define REG_PORT_XMII_CTRL_RGMII_INGRESS_DLY_Msk (0x1 << REG_PORT_XMII_CTRL_RGMII_INGRESS_DLY_Pos)
5517#define REG_PORT_XMII_CTRL_RGMII_INGRESS_DLY_ENABLED (0x1 << REG_PORT_XMII_CTRL_RGMII_INGRESS_DLY_Pos)
5518#define REG_PORT_XMII_CTRL_RGMII_INGRESS_DLY_DISABLED (0x0 << REG_PORT_XMII_CTRL_RGMII_INGRESS_DLY_Pos)
5519#define REG_PORT_XMII_CTRL_MII_SEL_EDGE_Pos 21
5520#define REG_PORT_XMII_CTRL_MII_SEL_EDGE_Msk (0x1 << REG_PORT_XMII_CTRL_MII_SEL_EDGE_Pos)
5521#define REG_PORT_XMII_CTRL_MII_SEL_EDGE_FALLINg (0x1 << REG_PORT_XMII_CTRL_MII_SEL_EDGE_Pos)
5522#define REG_PORT_XMII_CTRL_MII_SEL_EDGE_RISING (0x0 << REG_PORT_XMII_CTRL_MII_SEL_EDGE_Pos)
5523#define REG_PORT_XMII_CTRL_MII_1000M_Pos 22
5524#define REG_PORT_XMII_CTRL_MII_1000M_Msk (0x1 << REG_PORT_XMII_CTRL_MII_1000M_Pos)
5525#define REG_PORT_XMII_CTRL_MII_1000M_1000M (0x1 << REG_PORT_XMII_CTRL_MII_1000M_Pos)
5526#define REG_PORT_XMII_CTRL_MII_1000M_10_OR_100M (0x0 << REG_PORT_XMII_CTRL_MII_1000M_Pos)
5527#define REG_PORT_XMII_CTRL_MII_CLK_SEL_Pos 23
5528#define REG_PORT_XMII_CTRL_MII_CLK_SEL_Msk (0x1 << REG_PORT_XMII_CTRL_MII_CLK_SEL_Pos)
5529#define REG_PORT_XMII_CTRL_MII_CLK_SEL_MASTER (0x1 << REG_PORT_XMII_CTRL_MII_CLK_SEL_Pos)
5530#define REG_PORT_XMII_CTRL_MII_CLK_SEL_SLAVE (0x0 << REG_PORT_XMII_CTRL_MII_CLK_SEL_Pos)
5531#define REG_PORT_XMII_CTRL_GRXC_Pos 24
5532#define REG_PORT_XMII_CTRL_GRXC_Msk (0x1 << REG_PORT_XMII_CTRL_GRXC_Pos)
5533#define REG_PORT_XMII_CTRL_GRXC_ENABLED (0x1 << REG_PORT_XMII_CTRL_GRXC_Pos)
5534#define REG_PORT_XMII_CTRL_GRXC_DISABLED (0x0 << REG_PORT_XMII_CTRL_GRXC_Pos)
5535#define REG_PORT_XMII_CTRL_RX_FLOW_CTRL_Pos 27
5536#define REG_PORT_XMII_CTRL_RX_FLOW_CTRL_Msk (0x1 << REG_PORT_XMII_CTRL_RX_FLOW_CTRL_Pos)
5537#define REG_PORT_XMII_CTRL_RX_FLOW_CTRL_ENABLED (0x1 << REG_PORT_XMII_CTRL_RX_FLOW_CTRL_Pos)
5538#define REG_PORT_XMII_CTRL_RX_FLOW_CTRL_DISABLED (0x0 << REG_PORT_XMII_CTRL_RX_FLOW_CTRL_Pos)
5539#define REG_PORT_XMII_CTRL_MII_SPEED_Pos 28
5540#define REG_PORT_XMII_CTRL_MII_SPEED_Msk (0x1 << REG_PORT_XMII_CTRL_MII_SPEED_Pos)
5541#define REG_PORT_XMII_CTRL_MII_SPEED_100M (0x1 << REG_PORT_XMII_CTRL_MII_SPEED_Pos)
5542#define REG_PORT_XMII_CTRL_MII_SPEED_10M (0x0 << REG_PORT_XMII_CTRL_MII_SPEED_Pos)
5543#define REG_PORT_XMII_CTRL_TX_FLOW_CTRL_Pos 29
5544#define REG_PORT_XMII_CTRL_TX_FLOW_CTRL_Msk (0x1 << REG_PORT_XMII_CTRL_TX_FLOW_CTRL_Pos)
5545#define REG_PORT_XMII_CTRL_TX_FLOW_CTRL_ENABLED (0x1 << REG_PORT_XMII_CTRL_TX_FLOW_CTRL_Pos)
5546#define REG_PORT_XMII_CTRL_TX_FLOW_CTRL_DISABLED (0x0 << REG_PORT_XMII_CTRL_TX_FLOW_CTRL_Pos)
5547#define REG_PORT_XMII_CTRL_DUPLEX_Pos 30
5548#define REG_PORT_XMII_CTRL_DUPLEX_Msk (0x1 << REG_PORT_XMII_CTRL_DUPLEX_Pos)
5549#define REG_PORT_XMII_CTRL_DUPLEX_FULL (0x1 << REG_PORT_XMII_CTRL_DUPLEX_Pos)
5550#define REG_PORT_XMII_CTRL_DUPLEX_HALF (0x0 << REG_PORT_XMII_CTRL_DUPLEX_Pos)
5551#define REG_PORT_XMII_CTRL_SGMII_MODE_Pos 3
5552#define REG_PORT_XMII_CTRL_SGMII_MODE_Msk (0x1 << REG_PORT_XMII_CTRL_SGMII_MODE_Pos)
5553#define REG_PORT_XMII_CTRL_SGMII_MODE_ENABLED (0x1 << REG_PORT_XMII_CTRL_SGMII_MODE_Pos)
5554#define REG_PORT_XMII_CTRL_SGMII_MODE_DISABLED (0x0 << REG_PORT_XMII_CTRL_SGMII_MODE_Pos)
5555
5556#define REG_PORT_MAC_CTRL 0x0400
5557#define REG_PORT_MAC_CTRL_size 4
5558#define REG_PORT_MAC_CTRL_COUNT_PREAMBLE_Pos 0
5559#define REG_PORT_MAC_CTRL_COUNT_PREAMBLE_Msk (0x1 << REG_PORT_MAC_CTRL_COUNT_PREAMBLE_Pos)
5560#define REG_PORT_MAC_CTRL_COUNT_PREAMBLE_ENABLED (0x1 << REG_PORT_MAC_CTRL_COUNT_PREAMBLE_Pos)
5561#define REG_PORT_MAC_CTRL_COUNT_PREAMBLE_DISABLED (0x0 << REG_PORT_MAC_CTRL_COUNT_PREAMBLE_Pos)
5562#define REG_PORT_MAC_CTRL_COUNT_IFG_Pos 1
5563#define REG_PORT_MAC_CTRL_COUNT_IFG_Msk (0x1 << REG_PORT_MAC_CTRL_COUNT_IFG_Pos)
5564#define REG_PORT_MAC_CTRL_COUNT_IFG_ENABLED (0x1 << REG_PORT_MAC_CTRL_COUNT_IFG_Pos)
5565#define REG_PORT_MAC_CTRL_COUNT_IFG_DISABLED (0x0 << REG_PORT_MAC_CTRL_COUNT_IFG_Pos)
5566#define REG_PORT_MAC_CTRL_IN_LIMIT_MODE_Pos 2
5567#define REG_PORT_MAC_CTRL_IN_LIMIT_MODE_Msk (0x3 << REG_PORT_MAC_CTRL_IN_LIMIT_MODE_Pos)
5568#define REG_PORT_MAC_CTRL_IN_LIMIT_MODE_ALL (0x0 << REG_PORT_MAC_CTRL_IN_LIMIT_MODE_Pos)
5569#define REG_PORT_MAC_CTRL_IN_LIMIT_MODE_UCAST (0x1 << REG_PORT_MAC_CTRL_IN_LIMIT_MODE_Pos)
5570#define REG_PORT_MAC_CTRL_IN_LIMIT_MODE_MCAST (0x2 << REG_PORT_MAC_CTRL_IN_LIMIT_MODE_Pos)
5571#define REG_PORT_MAC_CTRL_IN_LIMIT_MODE_BCAST (0x3 << REG_PORT_MAC_CTRL_IN_LIMIT_MODE_Pos)
5572#define REG_PORT_MAC_CTRL_IN_FLOW_CTRL_Pos 4
5573#define REG_PORT_MAC_CTRL_IN_FLOW_CTRL_Msk (0x1 << REG_PORT_MAC_CTRL_IN_FLOW_CTRL_Pos)
5574#define REG_PORT_MAC_CTRL_IN_FLOW_CTRL_ENABLED (0x1 << REG_PORT_MAC_CTRL_IN_FLOW_CTRL_Pos)
5575#define REG_PORT_MAC_CTRL_IN_FLOW_CTRL_DISABLED (0x0 << REG_PORT_MAC_CTRL_IN_FLOW_CTRL_Pos)
5576#define REG_PORT_MAC_CTRL_IN_PKT_RATE_Pos 5
5577#define REG_PORT_MAC_CTRL_IN_PKT_RATE_Msk (0x1 << REG_PORT_MAC_CTRL_IN_PKT_RATE_Pos)
5578#define REG_PORT_MAC_CTRL_IN_PKT_RATE_ENABLED (0x1 << REG_PORT_MAC_CTRL_IN_PKT_RATE_Pos)
5579#define REG_PORT_MAC_CTRL_IN_PKT_RATE_DISABLED (0x0 << REG_PORT_MAC_CTRL_IN_PKT_RATE_Pos)
5580#define REG_PORT_MAC_CTRL_IN_RATE_Pos 6
5581#define REG_PORT_MAC_CTRL_IN_RATE_Msk (0x1 << REG_PORT_MAC_CTRL_IN_RATE_Pos)
5582#define REG_PORT_MAC_CTRL_IN_RATE_PORT (0x1 << REG_PORT_MAC_CTRL_IN_RATE_Pos)
5583#define REG_PORT_MAC_CTRL_IN_RATE_PRIO (0x0 << REG_PORT_MAC_CTRL_IN_RATE_Pos)
5584#define REG_PORT_MAC_CTRL_1000BT_EEE_Pos 14
5585#define REG_PORT_MAC_CTRL_1000BT_EEE_Msk (0x1 << REG_PORT_MAC_CTRL_1000BT_EEE_Pos)
5586#define REG_PORT_MAC_CTRL_1000BT_EEE_ENABLED (0x0 << REG_PORT_MAC_CTRL_1000BT_EEE_Pos)
5587#define REG_PORT_MAC_CTRL_1000BT_EEE_DISABLED (0x1 << REG_PORT_MAC_CTRL_1000BT_EEE_Pos)
5588#define REG_PORT_MAC_CTRL_100BTX_EEE_Pos 15
5589#define REG_PORT_MAC_CTRL_100BTX_EEE_Msk (0x1 << REG_PORT_MAC_CTRL_100BTX_EEE_Pos)
5590#define REG_PORT_MAC_CTRL_100BTX_EEE_ENABLED (0x0 << REG_PORT_MAC_CTRL_100BTX_EEE_Pos)
5591#define REG_PORT_MAC_CTRL_100BTX_EEE_DISABLED (0x1 << REG_PORT_MAC_CTRL_100BTX_EEE_Pos)
5592#define REG_PORT_MAC_CTRL_PASS_ALL_Pos 16
5593#define REG_PORT_MAC_CTRL_PASS_ALL_Msk (0x1 << REG_PORT_MAC_CTRL_PASS_ALL_Pos)
5594#define REG_PORT_MAC_CTRL_PASS_ALL_ENABLED (0x1 << REG_PORT_MAC_CTRL_PASS_ALL_Pos)
5595#define REG_PORT_MAC_CTRL_PASS_ALL_DISABLED (0x0 << REG_PORT_MAC_CTRL_PASS_ALL_Pos)
5596#define REG_PORT_MAC_CTRL_BACK_PRESSURE_Pos 17
5597#define REG_PORT_MAC_CTRL_BACK_PRESSURE_Msk (0x1 << REG_PORT_MAC_CTRL_BACK_PRESSURE_Pos)
5598#define REG_PORT_MAC_CTRL_BACK_PRESSURE_ENABLED (0x1 << REG_PORT_MAC_CTRL_BACK_PRESSURE_Pos)
5599#define REG_PORT_MAC_CTRL_BACK_PRESSURE_DISABLED (0x0 << REG_PORT_MAC_CTRL_BACK_PRESSURE_Pos)
5600#define REG_PORT_MAC_CTRL_JUMBO_FRAME_Pos 24
5601#define REG_PORT_MAC_CTRL_JUMBO_FRAME_Msk (0x1 << REG_PORT_MAC_CTRL_JUMBO_FRAME_Pos)
5602#define REG_PORT_MAC_CTRL_BCAST_STORM_PROT_Pos 25
5603#define REG_PORT_MAC_CTRL_BCAST_STORM_PROT_Msk (0x1 << REG_PORT_MAC_CTRL_BCAST_STORM_PROT_Pos)
5604#define REG_PORT_MAC_CTRL_BCAST_STORM_PROT_ENABLED (0x1 << REG_PORT_MAC_CTRL_BCAST_STORM_PROT_Pos)
5605#define REG_PORT_MAC_CTRL_BCAST_STORM_PROT_DISABLED (0x0 << REG_PORT_MAC_CTRL_BCAST_STORM_PROT_Pos)
5606
5607#define REG_PORT_IN_RATE_0 0x0410
5608#define REG_PORT_IN_RATE_0_size 1
5609#define REG_PORT_IN_RATE_0_RATE_LIMIT_Pos 0
5610#define REG_PORT_IN_RATE_0_RATE_LIMIT_Msk (0x7F << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5611#define REG_PORT_IN_RATE_0_RATE_LIMIT(_x) (((_x) << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos) &REG_PORT_IN_RATE_0_RATE_LIMIT_Msk)
5612#define REG_PORT_IN_RATE_0_RATE_LIMIT_640 (101 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5613#define REG_PORT_IN_RATE_0_RATE_LIMIT_1280 (102 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5614#define REG_PORT_IN_RATE_0_RATE_LIMIT_2560 (103 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5615#define REG_PORT_IN_RATE_0_RATE_LIMIT_3840 (104 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5616#define REG_PORT_IN_RATE_0_RATE_LIMIT_5120 (105 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5617#define REG_PORT_IN_RATE_0_RATE_LIMIT_6400 (106 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5618#define REG_PORT_IN_RATE_0_RATE_LIMIT_7680 (107 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5619#define REG_PORT_IN_RATE_0_RATE_LIMIT_8960 (108 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5620#define REG_PORT_IN_RATE_0_RATE_LIMIT_10240 (109 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5621#define REG_PORT_IN_RATE_0_RATE_LIMIT_11520 (110 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5622#define REG_PORT_IN_RATE_0_RATE_LIMIT_12800 (111 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5623#define REG_PORT_IN_RATE_0_RATE_LIMIT_14080 (112 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5624#define REG_PORT_IN_RATE_0_RATE_LIMIT_15360 (113 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5625#define REG_PORT_IN_RATE_0_RATE_LIMIT_16640 (114 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5626#define REG_PORT_IN_RATE_0_RATE_LIMIT_17920 (115 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5627
5628#define REG_PORT_IN_RATE_1 0x0411
5629#define REG_PORT_IN_RATE_1_size 1
5630#define REG_PORT_IN_RATE_1_RATE_LIMIT_Pos 0
5631#define REG_PORT_IN_RATE_1_RATE_LIMIT_Msk (0x7F << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5632#define REG_PORT_IN_RATE_1_RATE_LIMIT(_x) (((_x) << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos) &REG_PORT_IN_RATE_0_RATE_LIMIT_Msk)
5633#define REG_PORT_IN_RATE_1_RATE_LIMIT_640 (101 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5634#define REG_PORT_IN_RATE_1_RATE_LIMIT_1280 (102 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5635#define REG_PORT_IN_RATE_1_RATE_LIMIT_2560 (103 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5636#define REG_PORT_IN_RATE_1_RATE_LIMIT_3840 (104 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5637#define REG_PORT_IN_RATE_1_RATE_LIMIT_5120 (105 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5638#define REG_PORT_IN_RATE_1_RATE_LIMIT_6400 (106 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5639#define REG_PORT_IN_RATE_1_RATE_LIMIT_7680 (107 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5640#define REG_PORT_IN_RATE_1_RATE_LIMIT_8960 (108 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5641#define REG_PORT_IN_RATE_1_RATE_LIMIT_10240 (109 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5642#define REG_PORT_IN_RATE_1_RATE_LIMIT_11520 (110 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5643#define REG_PORT_IN_RATE_1_RATE_LIMIT_12800 (111 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5644#define REG_PORT_IN_RATE_1_RATE_LIMIT_14080 (112 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5645#define REG_PORT_IN_RATE_1_RATE_LIMIT_15360 (113 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5646#define REG_PORT_IN_RATE_1_RATE_LIMIT_16640 (114 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5647#define REG_PORT_IN_RATE_1_RATE_LIMIT_17920 (115 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5648
5649#define REG_PORT_IN_RATE_2 0x0412
5650#define REG_PORT_IN_RATE_2_size 1
5651#define REG_PORT_IN_RATE_2_RATE_LIMIT_Pos 0
5652#define REG_PORT_IN_RATE_2_RATE_LIMIT_Msk (0x7F << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5653#define REG_PORT_IN_RATE_2_RATE_LIMIT(_x) (((_x) << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos) &REG_PORT_IN_RATE_0_RATE_LIMIT_Msk)
5654#define REG_PORT_IN_RATE_2_RATE_LIMIT_640 (101 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5655#define REG_PORT_IN_RATE_2_RATE_LIMIT_1280 (102 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5656#define REG_PORT_IN_RATE_2_RATE_LIMIT_2560 (103 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5657#define REG_PORT_IN_RATE_2_RATE_LIMIT_3840 (104 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5658#define REG_PORT_IN_RATE_2_RATE_LIMIT_5120 (105 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5659#define REG_PORT_IN_RATE_2_RATE_LIMIT_6400 (106 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5660#define REG_PORT_IN_RATE_2_RATE_LIMIT_7680 (107 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5661#define REG_PORT_IN_RATE_2_RATE_LIMIT_8960 (108 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5662#define REG_PORT_IN_RATE_2_RATE_LIMIT_10240 (109 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5663#define REG_PORT_IN_RATE_2_RATE_LIMIT_11520 (110 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5664#define REG_PORT_IN_RATE_2_RATE_LIMIT_12800 (111 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5665#define REG_PORT_IN_RATE_2_RATE_LIMIT_14080 (112 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5666#define REG_PORT_IN_RATE_2_RATE_LIMIT_15360 (113 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5667#define REG_PORT_IN_RATE_2_RATE_LIMIT_16640 (114 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5668#define REG_PORT_IN_RATE_2_RATE_LIMIT_17920 (115 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5669
5670#define REG_PORT_IN_RATE_3 0x0413
5671#define REG_PORT_IN_RATE_3_size 1
5672#define REG_PORT_IN_RATE_3_RATE_LIMIT_Pos 0
5673#define REG_PORT_IN_RATE_3_RATE_LIMIT_Msk (0x7F << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5674#define REG_PORT_IN_RATE_3_RATE_LIMIT(_x) (((_x) << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos) &REG_PORT_IN_RATE_0_RATE_LIMIT_Msk)
5675#define REG_PORT_IN_RATE_3_RATE_LIMIT_640 (101 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5676#define REG_PORT_IN_RATE_3_RATE_LIMIT_1280 (102 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5677#define REG_PORT_IN_RATE_3_RATE_LIMIT_2560 (103 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5678#define REG_PORT_IN_RATE_3_RATE_LIMIT_3840 (104 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5679#define REG_PORT_IN_RATE_3_RATE_LIMIT_5120 (105 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5680#define REG_PORT_IN_RATE_3_RATE_LIMIT_6400 (106 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5681#define REG_PORT_IN_RATE_3_RATE_LIMIT_7680 (107 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5682#define REG_PORT_IN_RATE_3_RATE_LIMIT_8960 (108 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5683#define REG_PORT_IN_RATE_3_RATE_LIMIT_10240 (109 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5684#define REG_PORT_IN_RATE_3_RATE_LIMIT_11520 (110 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5685#define REG_PORT_IN_RATE_3_RATE_LIMIT_12800 (111 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5686#define REG_PORT_IN_RATE_3_RATE_LIMIT_14080 (112 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5687#define REG_PORT_IN_RATE_3_RATE_LIMIT_15360 (113 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5688#define REG_PORT_IN_RATE_3_RATE_LIMIT_16640 (114 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5689#define REG_PORT_IN_RATE_3_RATE_LIMIT_17920 (115 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5690
5691#define REG_PORT_IN_RATE_4 0x0414
5692#define REG_PORT_IN_RATE_4_size 1
5693#define REG_PORT_IN_RATE_4_RATE_LIMIT_Pos 0
5694#define REG_PORT_IN_RATE_4_RATE_LIMIT_Msk (0x7F << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5695#define REG_PORT_IN_RATE_4_RATE_LIMIT(_x) (((_x) << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos) &REG_PORT_IN_RATE_0_RATE_LIMIT_Msk)
5696#define REG_PORT_IN_RATE_4_RATE_LIMIT_640 (101 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5697#define REG_PORT_IN_RATE_4_RATE_LIMIT_1280 (102 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5698#define REG_PORT_IN_RATE_4_RATE_LIMIT_2560 (103 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5699#define REG_PORT_IN_RATE_4_RATE_LIMIT_3840 (104 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5700#define REG_PORT_IN_RATE_4_RATE_LIMIT_5120 (105 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5701#define REG_PORT_IN_RATE_4_RATE_LIMIT_6400 (106 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5702#define REG_PORT_IN_RATE_4_RATE_LIMIT_7680 (107 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5703#define REG_PORT_IN_RATE_4_RATE_LIMIT_8960 (108 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5704#define REG_PORT_IN_RATE_4_RATE_LIMIT_10240 (109 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5705#define REG_PORT_IN_RATE_4_RATE_LIMIT_11520 (110 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5706#define REG_PORT_IN_RATE_4_RATE_LIMIT_12800 (111 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5707#define REG_PORT_IN_RATE_4_RATE_LIMIT_14080 (112 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5708#define REG_PORT_IN_RATE_4_RATE_LIMIT_15360 (113 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5709#define REG_PORT_IN_RATE_4_RATE_LIMIT_16640 (114 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5710#define REG_PORT_IN_RATE_4_RATE_LIMIT_17920 (115 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5711
5712#define REG_PORT_IN_RATE_5 0x0415
5713#define REG_PORT_IN_RATE_5_size 1
5714#define REG_PORT_IN_RATE_5_RATE_LIMIT_Pos 0
5715#define REG_PORT_IN_RATE_5_RATE_LIMIT_Msk (0x7F << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5716#define REG_PORT_IN_RATE_5_RATE_LIMIT(_x) (((_x) << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos) &REG_PORT_IN_RATE_0_RATE_LIMIT_Msk)
5717#define REG_PORT_IN_RATE_5_RATE_LIMIT_640 (101 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5718#define REG_PORT_IN_RATE_5_RATE_LIMIT_1280 (102 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5719#define REG_PORT_IN_RATE_5_RATE_LIMIT_2560 (103 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5720#define REG_PORT_IN_RATE_5_RATE_LIMIT_3840 (104 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5721#define REG_PORT_IN_RATE_5_RATE_LIMIT_5120 (105 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5722#define REG_PORT_IN_RATE_5_RATE_LIMIT_6400 (106 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5723#define REG_PORT_IN_RATE_5_RATE_LIMIT_7680 (107 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5724#define REG_PORT_IN_RATE_5_RATE_LIMIT_8960 (108 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5725#define REG_PORT_IN_RATE_5_RATE_LIMIT_10240 (109 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5726#define REG_PORT_IN_RATE_5_RATE_LIMIT_11520 (110 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5727#define REG_PORT_IN_RATE_5_RATE_LIMIT_12800 (111 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5728#define REG_PORT_IN_RATE_5_RATE_LIMIT_14080 (112 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5729#define REG_PORT_IN_RATE_5_RATE_LIMIT_15360 (113 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5730#define REG_PORT_IN_RATE_5_RATE_LIMIT_16640 (114 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5731#define REG_PORT_IN_RATE_5_RATE_LIMIT_17920 (115 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5732
5733#define REG_PORT_IN_RATE_6 0x0416
5734#define REG_PORT_IN_RATE_6_size 1
5735#define REG_PORT_IN_RATE_6_RATE_LIMIT_Pos 0
5736#define REG_PORT_IN_RATE_6_RATE_LIMIT_Msk (0x7F << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5737#define REG_PORT_IN_RATE_6_RATE_LIMIT(_x) (((_x) << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos) &REG_PORT_IN_RATE_0_RATE_LIMIT_Msk)
5738#define REG_PORT_IN_RATE_6_RATE_LIMIT_640 (101 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5739#define REG_PORT_IN_RATE_6_RATE_LIMIT_1280 (102 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5740#define REG_PORT_IN_RATE_6_RATE_LIMIT_2560 (103 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5741#define REG_PORT_IN_RATE_6_RATE_LIMIT_3840 (104 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5742#define REG_PORT_IN_RATE_6_RATE_LIMIT_5120 (105 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5743#define REG_PORT_IN_RATE_6_RATE_LIMIT_6400 (106 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5744#define REG_PORT_IN_RATE_6_RATE_LIMIT_7680 (107 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5745#define REG_PORT_IN_RATE_6_RATE_LIMIT_8960 (108 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5746#define REG_PORT_IN_RATE_6_RATE_LIMIT_10240 (109 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5747#define REG_PORT_IN_RATE_6_RATE_LIMIT_11520 (110 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5748#define REG_PORT_IN_RATE_6_RATE_LIMIT_12800 (111 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5749#define REG_PORT_IN_RATE_6_RATE_LIMIT_14080 (112 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5750#define REG_PORT_IN_RATE_6_RATE_LIMIT_15360 (113 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5751#define REG_PORT_IN_RATE_6_RATE_LIMIT_16640 (114 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5752#define REG_PORT_IN_RATE_6_RATE_LIMIT_17920 (115 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5753
5754#define REG_PORT_IN_RATE_7 0x0417
5755#define REG_PORT_IN_RATE_7_size 1
5756#define REG_PORT_IN_RATE_7_RATE_LIMIT_Pos 0
5757#define REG_PORT_IN_RATE_7_RATE_LIMIT_Msk (0x7F << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5758#define REG_PORT_IN_RATE_7_RATE_LIMIT(_x) (((_x) << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos) &REG_PORT_IN_RATE_0_RATE_LIMIT_Msk)
5759#define REG_PORT_IN_RATE_7_RATE_LIMIT_640 (101 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5760#define REG_PORT_IN_RATE_7_RATE_LIMIT_1280 (102 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5761#define REG_PORT_IN_RATE_7_RATE_LIMIT_2560 (103 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5762#define REG_PORT_IN_RATE_7_RATE_LIMIT_3840 (104 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5763#define REG_PORT_IN_RATE_7_RATE_LIMIT_5120 (105 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5764#define REG_PORT_IN_RATE_7_RATE_LIMIT_6400 (106 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5765#define REG_PORT_IN_RATE_7_RATE_LIMIT_7680 (107 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5766#define REG_PORT_IN_RATE_7_RATE_LIMIT_8960 (108 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5767#define REG_PORT_IN_RATE_7_RATE_LIMIT_10240 (109 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5768#define REG_PORT_IN_RATE_7_RATE_LIMIT_11520 (110 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5769#define REG_PORT_IN_RATE_7_RATE_LIMIT_12800 (111 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5770#define REG_PORT_IN_RATE_7_RATE_LIMIT_14080 (112 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5771#define REG_PORT_IN_RATE_7_RATE_LIMIT_15360 (113 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5772#define REG_PORT_IN_RATE_7_RATE_LIMIT_16640 (114 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5773#define REG_PORT_IN_RATE_7_RATE_LIMIT_17920 (115 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5774
5775#define REG_PORT_OUT_RATE_0 0x0420
5776#define REG_PORT_OUT_RATE_0_size 1
5777#define REG_PORT_OUT_RATE_0_RATE_LIMIT_Pos 0
5778#define REG_PORT_OUT_RATE_0_RATE_LIMIT_Msk (0x7F << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5779#define REG_PORT_OUT_RATE_0_RATE_LIMIT(_x) (((_x) << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos) &REG_PORT_IN_RATE_0_RATE_LIMIT_Msk)
5780#define REG_PORT_OUT_RATE_0_RATE_LIMIT_640 (101 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5781#define REG_PORT_OUT_RATE_0_RATE_LIMIT_1280 (102 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5782#define REG_PORT_OUT_RATE_0_RATE_LIMIT_2560 (103 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5783#define REG_PORT_OUT_RATE_0_RATE_LIMIT_3840 (104 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5784#define REG_PORT_OUT_RATE_0_RATE_LIMIT_5120 (105 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5785#define REG_PORT_OUT_RATE_0_RATE_LIMIT_6400 (106 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5786#define REG_PORT_OUT_RATE_0_RATE_LIMIT_7680 (107 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5787#define REG_PORT_OUT_RATE_0_RATE_LIMIT_8960 (108 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5788#define REG_PORT_OUT_RATE_0_RATE_LIMIT_10240 (109 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5789#define REG_PORT_OUT_RATE_0_RATE_LIMIT_11520 (110 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5790#define REG_PORT_OUT_RATE_0_RATE_LIMIT_12800 (111 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5791#define REG_PORT_OUT_RATE_0_RATE_LIMIT_14080 (112 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5792#define REG_PORT_OUT_RATE_0_RATE_LIMIT_15360 (113 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5793#define REG_PORT_OUT_RATE_0_RATE_LIMIT_16640 (114 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5794#define REG_PORT_OUT_RATE_0_RATE_LIMIT_17920 (115 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5795
5796#define REG_PORT_OUT_RATE_1 0x0421
5797#define REG_PORT_OUT_RATE_1_size 1
5798#define REG_PORT_OUT_RATE_1_RATE_LIMIT_Pos 0
5799#define REG_PORT_OUT_RATE_1_RATE_LIMIT_Msk (0x7F << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5800#define REG_PORT_OUT_RATE_1_RATE_LIMIT(_x) (((_x) << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos) &REG_PORT_IN_RATE_0_RATE_LIMIT_Msk)
5801#define REG_PORT_OUT_RATE_1_RATE_LIMIT_640 (101 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5802#define REG_PORT_OUT_RATE_1_RATE_LIMIT_1280 (102 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5803#define REG_PORT_OUT_RATE_1_RATE_LIMIT_2560 (103 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5804#define REG_PORT_OUT_RATE_1_RATE_LIMIT_3840 (104 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5805#define REG_PORT_OUT_RATE_1_RATE_LIMIT_5120 (105 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5806#define REG_PORT_OUT_RATE_1_RATE_LIMIT_6400 (106 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5807#define REG_PORT_OUT_RATE_1_RATE_LIMIT_7680 (107 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5808#define REG_PORT_OUT_RATE_1_RATE_LIMIT_8960 (108 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5809#define REG_PORT_OUT_RATE_1_RATE_LIMIT_10240 (109 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5810#define REG_PORT_OUT_RATE_1_RATE_LIMIT_11520 (110 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5811#define REG_PORT_OUT_RATE_1_RATE_LIMIT_12800 (111 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5812#define REG_PORT_OUT_RATE_1_RATE_LIMIT_14080 (112 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5813#define REG_PORT_OUT_RATE_1_RATE_LIMIT_15360 (113 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5814#define REG_PORT_OUT_RATE_1_RATE_LIMIT_16640 (114 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5815#define REG_PORT_OUT_RATE_1_RATE_LIMIT_17920 (115 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5816
5817#define REG_PORT_OUT_RATE_2 0x0422
5818#define REG_PORT_OUT_RATE_2_size 1
5819#define REG_PORT_OUT_RATE_2_RATE_LIMIT_Pos 0
5820#define REG_PORT_OUT_RATE_2_RATE_LIMIT_Msk (0x7F << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5821#define REG_PORT_OUT_RATE_2_RATE_LIMIT(_x) (((_x) << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos) &REG_PORT_IN_RATE_0_RATE_LIMIT_Msk)
5822#define REG_PORT_OUT_RATE_2_RATE_LIMIT_640 (101 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5823#define REG_PORT_OUT_RATE_2_RATE_LIMIT_1280 (102 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5824#define REG_PORT_OUT_RATE_2_RATE_LIMIT_2560 (103 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5825#define REG_PORT_OUT_RATE_2_RATE_LIMIT_3840 (104 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5826#define REG_PORT_OUT_RATE_2_RATE_LIMIT_5120 (105 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5827#define REG_PORT_OUT_RATE_2_RATE_LIMIT_6400 (106 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5828#define REG_PORT_OUT_RATE_2_RATE_LIMIT_7680 (107 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5829#define REG_PORT_OUT_RATE_2_RATE_LIMIT_8960 (108 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5830#define REG_PORT_OUT_RATE_2_RATE_LIMIT_10240 (109 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5831#define REG_PORT_OUT_RATE_2_RATE_LIMIT_11520 (110 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5832#define REG_PORT_OUT_RATE_2_RATE_LIMIT_12800 (111 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5833#define REG_PORT_OUT_RATE_2_RATE_LIMIT_14080 (112 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5834#define REG_PORT_OUT_RATE_2_RATE_LIMIT_15360 (113 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5835#define REG_PORT_OUT_RATE_2_RATE_LIMIT_16640 (114 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5836#define REG_PORT_OUT_RATE_2_RATE_LIMIT_17920 (115 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5837
5838#define REG_PORT_OUT_RATE_3 0x0423
5839#define REG_PORT_OUT_RATE_3_size 1
5840#define REG_PORT_OUT_RATE_3_RATE_LIMIT_Pos 0
5841#define REG_PORT_OUT_RATE_3_RATE_LIMIT_Msk (0x7F << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5842#define REG_PORT_OUT_RATE_3_RATE_LIMIT(_x) (((_x) << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos) &REG_PORT_IN_RATE_0_RATE_LIMIT_Msk)
5843#define REG_PORT_OUT_RATE_3_RATE_LIMIT_640 (101 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5844#define REG_PORT_OUT_RATE_3_RATE_LIMIT_1280 (102 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5845#define REG_PORT_OUT_RATE_3_RATE_LIMIT_2560 (103 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5846#define REG_PORT_OUT_RATE_3_RATE_LIMIT_3840 (104 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5847#define REG_PORT_OUT_RATE_3_RATE_LIMIT_5120 (105 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5848#define REG_PORT_OUT_RATE_3_RATE_LIMIT_6400 (106 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5849#define REG_PORT_OUT_RATE_3_RATE_LIMIT_7680 (107 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5850#define REG_PORT_OUT_RATE_3_RATE_LIMIT_8960 (108 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5851#define REG_PORT_OUT_RATE_3_RATE_LIMIT_10240 (109 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5852#define REG_PORT_OUT_RATE_3_RATE_LIMIT_11520 (110 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5853#define REG_PORT_OUT_RATE_3_RATE_LIMIT_12800 (111 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5854#define REG_PORT_OUT_RATE_3_RATE_LIMIT_14080 (112 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5855#define REG_PORT_OUT_RATE_3_RATE_LIMIT_15360 (113 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5856#define REG_PORT_OUT_RATE_3_RATE_LIMIT_16640 (114 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5857#define REG_PORT_OUT_RATE_3_RATE_LIMIT_17920 (115 << REG_PORT_IN_RATE_0_RATE_LIMIT_Pos)
5858
5859#define REG_PORT_MIB_CTRL_STAT 0x0500
5860#define REG_PORT_MIB_CTRL_STAT_size 4
5861#define REG_PORT_MIB_CTRL_STAT_MIB_COUNTER_HI_Pos 0
5862#define REG_PORT_MIB_CTRL_STAT_MIB_COUNTER_HI_Msk (0xF << REG_PORT_IN_RATE_0_MIB_COUNTER_HI_Pos)
5863#define REG_PORT_MIB_CTRL_STAT_MIB_COUNTER_HI(_x) (((_x) << REG_PORT_IN_RATE_0_MIB_COUNTER_HI_Pos) &REG_PORT_IN_RATE_0_MIB_COUNTER_HI_Msk)
5864#define REG_PORT_MIB_CTRL_STAT_MIB_INDEX_Pos 16
5865#define REG_PORT_MIB_CTRL_STAT_MIB_INDEX_Msk (0xFF << REG_PORT_IN_RATE_0_MIB_INDEX_Pos)
5866#define REG_PORT_MIB_CTRL_STAT_MIB_INDEX(_x) (((_x) << REG_PORT_IN_RATE_0_MIB_INDEX_Pos) &REG_PORT_IN_RATE_0_MIB_INDEX_Msk)
5867#define REG_PORT_MIB_CTRL_STAT_FLUSH_AND_FREEZE_Pos 24
5868#define REG_PORT_MIB_CTRL_STAT_FLUSH_AND_FREEZE_Msk (0xF << REG_PORT_IN_RATE_0_FLUSH_AND_FREEZE_Pos)
5869#define REG_PORT_MIB_CTRL_STAT_FLUSH_AND_FREEZE_DISABLED (0x0 << REG_PORT_IN_RATE_0_FLUSH_AND_FREEZE_Pos)
5870#define REG_PORT_MIB_CTRL_STAT_FLUSH_AND_FREEZE_ENABLED (0x1 << REG_PORT_IN_RATE_0_FLUSH_AND_FREEZE_Pos)
5871#define REG_PORT_MIB_CTRL_STAT_COUNTER_OVERFLOW_Pos 31
5872#define REG_PORT_MIB_CTRL_STAT_COUNTER_OVERFLOW_Msk (0xF << REG_PORT_IN_RATE_0_COUNTER_OVERFLOW_Pos)
5873
5874#define REG_PORT_MIB_DATA 0x0504
5875#define REG_PORT_MIB_DATA_size 4