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cortex-m7/include/nbrtoscpu.h
1#ifndef __NBRTOS_CM7_H
2#define NB_NBRTOS_CPU_H
3#define __NBRTOS_CM7_H
4
5/*NB_REVISION*/
6
7/*NB_COPYRIGHT*/
8#include <basictypes.h>
9
10// Macros expectdy by core CM functions
11#ifndef __STATIC_INLINE
12#define __STATIC_INLINE static inline
13#endif
14#ifndef __INLINE
15#define __INLINE inline
16#endif
17#ifndef __ASM
18#define __ASM __asm
19#endif
20//#include <core_cmFunc.h>
21
22#define ARCH_STK_ALIGN_SIZ (8)
23#define ARCH_ALIGN_STK __attribute__((aligned(ARCH_STK_ALIGN_SIZ)))
24
25#define SCB_ICSR_REG (*((uint32_t *)0xE000ED04UL))
26#define SCB_ICSR_PENDSVSET_BIT (0x10000000);
27static __inline__ void *get_pc(void)
28{
29 void *pc;
30 asm("mov %0, pc" : "=r"(pc));
31 return pc;
32}
33/*#define NBRTOS_ENTER_CRITICAL() { register uint32_t pc, tmp_12=0; \
34 lockPC = (uint32_t)get_pc(); \
35 asm volatile ("add %2, pc, #4\n\t" \
36 "str %2, [%1]\n\t" \
37 "cpsid i" : "=r"(pc) : "r"(&lockPC), "r"(tmp_12)); }\
38 asm volatile ("cpsid i"); }*/
39
40extern volatile uint32_t critical_count;
41extern volatile uint32_t lockPC;
42extern volatile uint32_t OSISRLevel32;
43
44#ifndef _DEBUG
45// If NOT Debug, but we do reserve some IRQ levels to not be masked by the RTOS
46#if defined OS_MAX_IRQ_MASK && (OS_MAX_IRQ_MASK < CPU_MAX_IRQ)
47#define NBRTOS_ENTER_CRITICAL() \
48 { \
49 __set_BASEPRI((CPU_MAX_IRQ - OS_MAX_IRQ_MASK) << (8 - __NVIC_PRIO_BITS)); \
50 asm volatile("dsb" ::: "memory"); \
51 }
52#define NBRTOS_EXIT_CRITICAL() \
53 { \
54 if (critical_count <= 0) \
55 { \
56 __set_BASEPRI(OSISRLevel32 << (8 - __NVIC_PRIO_BITS)); \
57 asm volatile("dsb" ::: "memory"); \
58 } \
59 }
60
61#define USER_ENTER_CRITICAL() \
62 { \
63 __set_BASEPRI((CPU_MAX_IRQ - OS_MAX_IRQ_MASK) << (8 - __NVIC_PRIO_BITS)); \
64 asm volatile("dsb" ::: "memory"); \
65 critical_count++; \
66 }
67
68#define USER_EXIT_CRITICAL() \
69 { \
70 if (--critical_count <= 0) \
71 { \
72 __set_BASEPRI(OSISRLevel32 << (8 - __NVIC_PRIO_BITS)); \
73 asm volatile("dsb" ::: "memory"); \
74 } \
75 }
76
77#else /* -> #if OS_MAX_IRQ_MASK < CPU_MAX_IRQ */
78// If NOT Debug and no RTOS ISR blocking limitations, disable Interrupts for
79// RTOS Critical Sections
80#define NBRTOS_ENTER_CRITICAL() asm volatile("cpsid i\nisb");
81#define NBRTOS_EXIT_CRITICAL() \
82 { \
83 if (critical_count <= 0) { asm volatile("cpsie i"); } \
84 }
85
86#define USER_ENTER_CRITICAL() \
87 { \
88 asm volatile("cpsid i\nisb"); \
89 critical_count++; \
90 }
91
92#define USER_EXIT_CRITICAL() \
93 { \
94 if (--critical_count <= 0) { asm volatile("cpsie i"); } \
95 }
96#endif /* #if OS_MAX_IRQ_MASK < CPU_MAX_IRQ */
97#else /* #ifndef _DEBUG */
98
99extern volatile uint32_t dbgState;
100#define DBG_STATE_INT_MASK (0x2)
101#define DBG_CRITMASK_RTOS (0x4)
102#define DBG_CRITMASK_USER (0x8)
103#define DBG_CRITMASK_GDB (0x10)
104
105#define NBRTOS_ENTER_CRITICAL() \
106 { \
107 asm volatile("cpsid i\nisb"); \
108 __set_BASEPRI(1 << (8 - __NVIC_PRIO_BITS)); \
109 asm volatile("cpsie i"); \
110 dbgState |= DBG_CRITMASK_RTOS; \
111 }
112#define NBRTOS_EXIT_CRITICAL() \
113 { \
114 dbgState &= ~DBG_CRITMASK_RTOS; \
115 if ((critical_count <= 0) || (OSISRLevel32)) \
116 { \
117 if (!(dbgState & (DBG_STATE_INT_MASK | DBG_CRITMASK_GDB))) { __set_BASEPRI(OSISRLevel32 << (8 - __NVIC_PRIO_BITS)); } \
118 } \
119 }
120
121#define USER_ENTER_CRITICAL() \
122 { \
123 asm volatile("cpsid i\nisb"); \
124 __set_BASEPRI(1 << (8 - __NVIC_PRIO_BITS)); \
125 asm volatile("cpsie i"); \
126 critical_count++; \
127 dbgState |= DBG_CRITMASK_USER; \
128 }
129
130#define USER_EXIT_CRITICAL() \
131 { \
132 if (--critical_count <= 0) \
133 { \
134 dbgState &= ~DBG_CRITMASK_USER; \
135 if (!(dbgState & (DBG_STATE_INT_MASK | DBG_CRITMASK_GDB))) { __set_BASEPRI(OSISRLevel32 << (8 - __NVIC_PRIO_BITS)); } \
136 } \
137 }
138
139#endif /* #ifndef _DEBUG */
140
141#define OS_TASK_SW() \
142 { \
143 SCB_ICSR_REG = SCB_ICSR_PENDSVSET_BIT; \
144 NBRTOS_EXIT_CRITICAL(); \
145 asm(".global RTOSWAITS_HERE"); \
146 asm("RTOSWAITS_HERE:"); \
147 NBRTOS_ENTER_CRITICAL(); \
148 }
149
150#define OSIntCtxSw() \
151 { \
152 SCB_ICSR_REG = SCB_ICSR_PENDSVSET_BIT; \
153 }
154
155#define FORCE_TRAP() asm volatile("udf")
156
157#define OSInIrq() (__get_IPSR() != 0)
158
159extern "C"
160{
161 void NBRtosSetup();
162}
163void NBRtosBegin();
164
165void FlushCache_ByAddr(uint32_t *addr, uint32_t len);
166void InvalidateCache_ByAddr(uint32_t *addr, uint32_t len);
167
168void MPU_DumpRegions();
169void MPU_DumpRegion(int region);
170int MPU_GetRegionCount();
171
172enum TaskDlyState
173{
174 DLY_NO_PEND, // Pend callback is being called in a path that
175 // does not pend the task
176 DLY_PEND, // Callback is being called just prior to
177 // task suspension and switch
178 DLY_RESUME // Callback is being called just *after* task resumption
179};
180
181/*
182***********************************************************
183* uCOS TASK CONTROL BLOCK DATA STRUCTURE
184***********************************************************
185*/
186struct cpu_tcb
187{
188 uint32_t r4_r11[8]; // Storage for task registers when swapping
189 double d[16]; // Storage for FPU context, FPU is lazily restored
190 uint32_t fpscr;
191 void *OSTCBStkPtr;
192
193 long *OSTCBStkBot;
194 long *OSTCBStkTop;
195};
196
197// struct OS_TASK_DLY_OBJ
198// {
199// volatile uint32_t OSTbl[TASK_TABLE_SIZE];
200// volatile uint32_t backstop{0x80000000}; // this exists to run OSGetHighBit_Set
201// public:
202// OS_TASK_DLY_OBJ();
203// void Init();
204// void Wait(volatile OS_TCB &tcb, uint8_t StatReason, unsigned long timeout);
205// void ClearWaiting(uint8_t prio);
206// void Ready(uint8_t StatReason);
207// };
208
209
210enum {
211 MPU_MEMTYPE__STRONG_ORDER = 0x00,
212 MPU_MEMTYPE__DEV_SHARED = 0x01,
213 MPU_MEMTYPE__NORM_WR_THRU = 0x02,
214 MPU_MEMTYPE__NORM_NO_WR_ALLOC= 0x03,
215 MPU_MEMTYPE__NORM_NON_CACHE = 0x04,
216 MPU_MEMTYPE__NORM_WR_ALLOC = 0x07,
217 MPU_MEMTYPE__DEV_NON_SHARED = 0x08,
218};
219
220enum {
221 MPU_PERMS__PRIV_NONE_UNPRIV_NONE = 0x00,
222 MPU_PERMS__PRIV_RDWR_UNPRIV_NONE = 0x01,
223 MPU_PERMS__PRIV_RDWR_UNPRIV_READ = 0x02,
224 MPU_PERMS__PRIV_RDWR_UNPRIV_RDWR = 0x03,
225 MPU_PERMS__INVALID = 0x04,
226 MPU_PERMS__PRIV_READ_UNPRIV_NONE = 0x05,
227 MPU_PERMS__PRIV_READ_UNPRIV_READ = 0x06,
228 MPU_PERMS__PRIV_READ_UNPRIV_READ_ALSO = 0x07,
229};
230
231struct MPU_RegionCfg {
232 uint32_t size;
233 uint32_t baseAddr;
234 uint8_t subRegionDisable;
235 bool executeNever;
236 uint8_t permissions;
237 uint8_t memType;
238 bool shared;
239 bool valid;
240
241 MPU_RegionCfg();
242 MPU_RegionCfg(int region);
243 bool ContainsVal(uint32_t addr, uint32_t valLen);
244};
245
246int MPU_GetRegionCount();
247int MPU_GetRegionConfig(int region, MPU_RegionCfg *cfg);
248bool MPU_AddrContainedInRegion(int region, uint32_t addr, uint32_t size);
249int MPU_GetRegionPermissions(int region);
250void MPU_DumpRegion(int region);
251void MPU_DumpRegions();
252
253#endif /* ----- #ifndef __NBRTOS_CM7_H ----- */