coldfire/cpu/MCF5441X/include/cpu_pins.h

/*NB_REVISION*/
 
/*NB_COPYRIGHT*/
 
#ifndef _CPU_PINS_H_
#define _CPU_PINS_H_
 
#include <basictypes.h>
 
#define CPU_PINS
//namespace CPU_PINS
//{
class PinIO
{
 public:
 uint8_t port, pinnum;
 private:
 
 void funcA(int ft);
 void funcB(int ft);
 void funcC(int ft);
 void funcD(int ft);
 void funcE(int ft);
 void funcF(int ft);
 void funcG(int ft);
 void funcH(int ft);
 void funcI(int ft);
 void funcJ(int ft);
 void funcK(int ft);
 
 int getFuncA();
 int getFuncB();
 int getFuncC();
 int getFuncD();
 int getFuncE();
 int getFuncF();
 int getFuncG();
 int getFuncH();
 int getFuncI();
 int getFuncJ();
 int getFuncK();
 
 
 public:
 typedef enum {
 PIN_FN_0 = 0,
 PIN_FN_1 = 1,
 PIN_FN_2 = 2,
 PIN_FN_3 = 3,
 PIN_FN_IN = 4,
 PIN_FN_OUT = 6,
 } pin_fn_t;
 
 
 typedef enum {
 PULL_DOWN_WEAK = 0,
 PULL_UP_WEAK = 1,
 PULL_UP_MED = 2,
 PULL_UP_STRONG = 3,
 PULL_KEEP = 4,
 PULL_OFF = 5,
 } pull_t;
 
 
 PinIO(int j, int n)
 {
 port = j;
 pinnum = n;
 };
 PinIO(const PinIO &rhs) : port(rhs.port), pinnum(rhs.pinnum) {}
 PinIO() : port(0), pinnum(0){};
 
 void set(BOOL = TRUE); // Set output high
 BOOL toggle(); // Toggle the pin state
 void clr() { set(FALSE); }; // Set output low
 BOOL read(); // Read pin hi/low state
 void hiz() { read(); }; // Set output to tristate
 void drive(); // Turn output on (opposite of tristate)
 
 void setPull(pull_t pull);
 inline void PullUp() { setPull(PULL_UP_MED); }
 inline void PullDown() { setPull(PULL_DOWN_WEAK); }
 pull_t getPull();
 
 void setSlew(uint8_t slew);
 inline void setSpeed(uint8_t speed) { return; }
 inline void setStrength(uint8_t strength) { return; }
 void setOpenDrain(bool enable);
 inline void multidrv(bool enable) { return setOpenDrain(enable); }
 inline void setHyst(bool enable) { return; }
 
 uint8_t getSlew();
 inline uint8_t getSpeed() { return 0; }
 uint8_t getStrength() { return 0; }
 bool getOpenDrain() { return (port & 0x80) != 0; }
 bool getHyst();
 
 inline void setSchmidt(bool enable) { setHyst(enable); }
 inline bool getSchmidt() { return getHyst(); }
 inline void HystOn() { setHyst(true); }
 inline void HystOff() { setHyst(false); }
 inline void SchmidtOn() { setHyst(true); }
 inline void SchmidtOff(){ setHyst(false); }
 
 void function(int ft); // Set pin to special function
 void setFn(int ft) // Set pin to special function
 { function(ft); }
 int getFunction(); // Get the special function the pin is set to
 PinIO &operator=(BOOL b)
 {
 set(b);
 return *this;
 };
 PinIO &operator=(int i)
 {
 set(i);
 return *this;
 };
 PinIO &operator=(uint32_t i)
 {
 set(i);
 return *this;
 };
 operator int() { return read(); }; // Read and return int value
 operator BOOL() { return read(); }; // Read and return BOOL value
 operator bool() { return (read() != 0); }; // Read and return boolean value
 friend class PinIOPortAArray;
 friend class PinIOPortBArray;
 friend class PinIOPortCArray;
 friend class PinIOPortDArray;
 friend class PinIOPortEArray;
 friend class PinIOPortFArray;
 friend class PinIOPortGArray;
 friend class PinIOPortHArray;
 friend class PinIOPortIArray;
 friend class PinIOPortJArray;
 friend class PinIOPortKArray;
};
 
class PinIOPortAArray
{
 public:
 PinIO operator[](int n) { return PinIO(0, n); };
};
class PinIOPortBArray
{
 public:
 PinIO operator[](int n) { return PinIO(1, n); };
};
class PinIOPortCArray
{
 public:
 PinIO operator[](int n) { return PinIO(2, n); };
};
class PinIOPortDArray
{
 public:
 PinIO operator[](int n) { return PinIO(3, n); };
};
class PinIOPortEArray
{
 public:
 PinIO operator[](int n) { return PinIO(4, n); };
};
class PinIOPortFArray
{
 public:
 PinIO operator[](int n) { return PinIO(5, n); };
};
class PinIOPortGArray
{
 public:
 PinIO operator[](int n) { return PinIO(6, n); };
};
class PinIOPortHArray
{
 public:
 PinIO operator[](int n) { return PinIO(7, n); };
};
class PinIOPortIArray
{
 public:
 PinIO operator[](int n) { return PinIO(8, n); };
};
class PinIOPortJArray
{
 public:
 PinIO operator[](int n) { return PinIO(9, n); };
};
class PinIOPortKArray
{
 public:
 PinIO operator[](int n) { return PinIO(10, n); };
};
//} // namespace CPU_PINS
 
extern CPU_PINS::PinIOPortAArray PortA;
extern CPU_PINS::PinIOPortBArray PortB;
extern CPU_PINS::PinIOPortCArray PortC;
extern CPU_PINS::PinIOPortDArray PortD;
extern CPU_PINS::PinIOPortEArray PortE;
extern CPU_PINS::PinIOPortFArray PortF;
extern CPU_PINS::PinIOPortGArray PortG;
extern CPU_PINS::PinIOPortHArray PortH;
extern CPU_PINS::PinIOPortIArray PortI;
extern CPU_PINS::PinIOPortJArray PortJ;
extern CPU_PINS::PinIOPortKArray PortK;
 
#endif