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MIMXRT11xx/include/qtmr.h
1#ifndef __QTMR_H
2#define __QTMR_H
3/**************************************************************************/
33
34#include <predef.h>
35#include <stdint.h>
36#include <stddef.h>
37#include <sim.h>
38
39enum QTMR_Channel
40{
41 QTMR_CH_0 = 0u,
42 QTMR_CH_1 = 1u,
43 QTMR_CH_2 = 2u,
44 QTMR_CH_3 = 3u,
45};
46
47enum QTMR_Primary
48{
49 QTMR_PRI_IN_CNTR0 = 0u, /* Counter 0 input pin */
50 QTMR_PRI_IN_CNTR1 = 1u, /* Counter 1 input pin */
51 QTMR_PRI_IN_CNTR2 = 2u, /* Counter 2 input pin */
52 QTMR_PRI_IN_CNTR3 = 3u, /* Counter 3 input pin */
53 QTMR_PRI_OUT_CNTR0 = 4u, /* Counter 0 output */
54 QTMR_PRI_OUT_CNTR1 = 5u, /* Counter 1 output */
55 QTMR_PRI_OUT_CNTR2 = 6u, /* Counter 2 output */
56 QTMR_PRI_OUT_CNTR3 = 7u, /* Counter 3 output */
57 QTMR_PRI_CLK_DIV_1 = 8u, /* IP bus clock, divided by 1 */
58 QTMR_PRI_CLK_DIV_2 = 9u, /* IP bus clock, divided by 2 */
59 QTMR_PRI_CLK_DIV_4 = 10u,/* IP bus clock, divided by 4 */
60 QTMR_PRI_CLK_DIV_8 = 11u,/* IP bus clock, divided by 8 */
61 QTMR_PRI_CLK_DIV_16 = 12u,/* IP bus clock, divided by 16 */
62 QTMR_PRI_CLK_DIV_32 = 13u,/* IP bus clock, divided by 32 */
63 QTMR_PRI_CLK_DIV_64 = 14u,/* IP bus clock, divided by 64 */
64 QTMR_PRI_CLK_DIV_128= 15u,/* IP bus clock, divided by 128 */
65};
66
67enum QTMR_Input
68{
69 QTMR_IN_0 = 0u,
70 QTMR_IN_1 = 1u,
71 QTMR_IN_2 = 2u,
72 QTMR_IN_3 = 3u,
73};
74
75enum QTMR_DbgMode
76{
77 QTMR_DBG_NORMAL = 0u, /* Continue as normal */
78 QTMR_DBG_HALT = 1u, /* Halt the counter */
79 QTMR_FORCE_OUT_ZERO = 2u, /* Force output to logic 0 */
80 QTMR_DBG_HALT_FORCE_OUT_ZERO= 3u, /* Halt and force output to logic 0 */
81};
82
83enum QTMR_CapEdge
84{
85 QTMR_CAP_NONE = 0u,
86 QTMR_CAP_RISING = 1u,
87 QTMR_CAP_FALLING= 2u,
88 QTMR_CAP_BOTH = 3u,
89};
90
91enum QTMR_CountMode
92{
93 QTMR_COUNT_NONE = 0u, /* No counting */
94 QTMR_COUNT_PRIM_RISING = 1u, /* Count rising edges on primary source */
95 QTMR_COUNT_PRIM_BOTH = 2u, /* Count both edges on primary source */
96 QTMR_COUNT_PRIM_RISING_IN_HIGH = 3u, /* Count rising of pri src while sec input high*/
97 QTMR_COUNT_QUADRATURE = 4u, /* Quadrature mode using pri and sec */
98 QTMR_COUNT_PRIM_RISING_IN_DIR = 5u, /* Rising on primary, input sets dir (up/down) */
99 QTMR_COUNT_IN_EDGE = 6u, /* Count edge of sec until comparison met */
100 QTMR_COUNT_CASCADE = 7u, /* Cascaded count */
101};
102
103enum QTMR_Preload
104{
105 QTMR_PRELOAD_NEVER = 0u,
106 QTMR_PRELOAD_COMP1 = 1u,
107 QTMR_PRELOAD_COMP2 = 2u,
108};
109
110enum QTMR_OutMode
111{
112 QTMR_OUT_WHEN_ACTIVE = 0u, /* Assert OFLAG when counter is active */
113 QTMR_OUT_CMP_CLR = 1u, /* Clear OFLAG on compare */
114 QTMR_OUT_CMP_SET = 2u, /* Set OFLAG on compare */
115 QTMR_OUT_CMP_TGL = 3u, /* Toggle OFLAG on compare */
116 QTMR_OUT_CMP_TGL_ALT = 4u, /* Toggle OFLAG on alternating compare regs */
117 QTMR_OUT_CMP_SET_IN_CLR = 5u, /* Set OFLAG on compare, clear on sec Src edge */
118 QTMR_OUT_CMP_SET_ROLL_CLR = 6u, /* Set OFLAG on compare, clear on rollover */
119 QTMR_OUT_GATE_CLK = 7u, /* Gated clock output when counter is active */
120};
121
122enum QTMR_IRQFlag
123{
124 QTMR_IRQ_CMP = (TMR_SCTRL_TCFIE_MASK << 16),
125 QTMR_IRQ_OVERFLOW = (TMR_SCTRL_TOFIE_MASK << 16),
126 QTMR_IRQ_IN_EDGE = (TMR_SCTRL_IEFIE_MASK << 16),
127 QTMR_IRQ_CMP1 = (TMR_CSCTRL_TCF1EN_MASK),
128 QTMR_IRQ_CMP2 = (TMR_CSCTRL_TCF2EN_MASK),
129};
130
131enum QTMR_StatusFlag
132{
133 QTMR_STAT_CMP = (TMR_SCTRL_TCF_MASK << 16),
134 QTMR_STAT_OVERFLOW = (TMR_SCTRL_TOF_MASK << 16),
135 QTMR_STAT_IN_EDGE = (TMR_SCTRL_IEF_MASK << 16),
136 QTMR_STAT_CMP1 = (TMR_CSCTRL_TCF1_MASK),
137 QTMR_STAT_CMP2 = (TMR_CSCTRL_TCF2_MASK),
138};
139
140enum QTMR_DMAFlag
141{
142 QTMR_DMA_IN_EDGE = (TMR_DMA_IEFDE_MASK),
143 QTMR_DMA_PLD_CMP1 = (TMR_DMA_CMPLD1DE_MASK),
144 QTMR_DMA_PLD_CMP2 = (TMR_DMA_CMPLD2DE_MASK),
145};
146
147struct QTimer;
148struct QTimer_Channel;
149
150typedef void (*QTimer_CB)(QTimer *);
151typedef void (*QTimer_Channel_CB)(QTimer *, QTMR_Channel);
152
153struct QTimer_Channel : TMR_Channel_Type
154{
155private:
156 struct ctx_t
157 {
158 QTimer_Channel_CB irqCB;
159 uint32_t irqCount;
160 };
161
162 static ctx_t *sGetCtx(QTimer_Channel *ch);
163
164 QTimer_Channel();
165
166 void isr(QTimer * tmr, QTMR_Channel chNum);
167 friend struct QTimer;
168public:
169 void Init(QTMR_Primary priSrc, QTMR_Input secSrc,
170 bool masterMode, bool enExtForce,
171 uint8_t faultFiltCount, uint8_t faultFiltPer,
172 QTMR_DbgMode dbgMode);
173 bool SetupPwm(uint32_t pwmFreq, uint8_t dutyPcnt,
174 bool invertPolarity, uint32_t srcFreq);
175 void SetupCapture(QTMR_Input pin,
176 bool invertPolarity, bool reloadOnCapture,
177 QTMR_CapEdge edge);
178 void SetupCascade(uint16_t countVal);
179
180 inline void ConfigOutput(bool enabled, bool invertPolarity, QTMR_OutMode mode);
181 inline void ForceOutput(bool val);
182 void EnableIRQs(uint32_t mask); // SCTRL flags in upper 16 bits, CSCTRL flags in lower
183 void DisableIRQs(uint32_t mask);
184 uint32_t GetEnabledIRQs();
185 uint32_t GetStatus();
186 void ClearStatus(uint32_t mask);
187 void SetPeriod(uint16_t period);
188 inline uint16_t GetCurCount();
189 inline void Start(QTMR_CountMode mode);
190 inline QTMR_CountMode Stop();
191 inline QTMR_CountMode GetCurMode();
192 void EnableDMA(uint32_t mask);
193 void DisableDMA(uint32_t mask);
194
195 uint8_t GetChNum();
196 QTimer *GetTimer();
197
198 bool IRQReady();
199 QTimer_Channel_CB SetIRQFn(QTimer_Channel_CB fn);
200};
201
202struct QTimer : TMR_Type
203{
204private:
205 struct ctx_t
206 {
207 QTimer_CB irqCB;
208 uint32_t irqCount;
209 QTimer_Channel::ctx_t ch[4];
210 };
211
212 static ctx_t sCtxs[4];
213 static ctx_t *sGetCtx(QTimer *timer)
214 {
215 switch ((uint32_t)timer) {
216 case TMR1_BASE: return sCtxs + 0;
217 case TMR2_BASE: return sCtxs + 1;
218 case TMR3_BASE: return sCtxs + 2;
219 case TMR4_BASE: return sCtxs + 3;
220 }
221 return NULL;
222 }
223
224 QTimer();
225 void isr();
226
227 friend QTimer_Channel::ctx_t * QTimer_Channel::sGetCtx(QTimer_Channel *ch);
228 friend QTimer_Channel_CB QTimer_Channel::SetIRQFn(QTimer_Channel_CB fn);
229
230 friend void isr_qtimer0();
231 friend void isr_qtimer1();
232 friend void isr_qtimer2();
233 friend void isr_qtimer3();
234public:
235 inline QTimer_Channel &operator[](int i);
236
237 static inline QTimer *TMR(TMR_Type *tmr);
238
239 inline void Init(QTMR_Channel chNum, QTMR_Primary priSrc, QTMR_Input secSrc,
240 bool masterMode, bool enExtForce, uint8_t faultFiltCount,
241 uint8_t faultFiltPer, QTMR_DbgMode dbgMode);
242 inline bool SetupPwm(QTMR_Channel chNum, uint32_t pwmFreq, uint8_t dutyPcnt,
243 bool invertPolarity, uint32_t srcFreq);
244 inline void SetupCapture(QTMR_Channel chNum, QTMR_Input pin,
245 bool invertPolarity, bool reloadOnCapture,
246 QTMR_CapEdge edge);
247 inline void ConfigOutput(QTMR_Channel chNum, bool enabled, bool invertPolarity, QTMR_OutMode mode);
248 inline void ForceOutput(QTMR_Channel chNum, bool val);
249 inline void EnableIRQs(QTMR_Channel chNum, uint32_t mask);
250 inline void DisableIRQs(QTMR_Channel chNum, uint32_t mask);
251 inline uint32_t GetEnabledIRQs(QTMR_Channel chNum);
252 inline uint32_t GetStatus(QTMR_Channel chNum);
253 inline void ClearStatus(QTMR_Channel chNum, uint32_t mask);
254 inline void SetPeriod(QTMR_Channel chNum, uint16_t period);
255 inline uint16_t GetCurCount(QTMR_Channel chNum);
256 inline void Start(QTMR_Channel chNum, QTMR_CountMode mode);
257 inline QTMR_CountMode Stop(QTMR_Channel chNum);
258 inline QTMR_CountMode GetCurMode(QTMR_Channel chNum);
259 inline void EnableDMA(QTMR_Channel chNum, uint32_t mask);
260 inline void DisableDMA(QTMR_Channel chNum, uint32_t mask);
261 inline void EnableChannels(uint16_t mask);
262 inline void DisableChannels(uint16_t mask);
263
264 QTimer_CB SetIRQFn(QTimer_CB fn);
265 QTimer_Channel_CB SetChIRQFn(QTMR_Channel chNum, QTimer_Channel_CB fn);
266};
267
268inline void QTimer::
269Init(QTMR_Channel chNum, QTMR_Primary priSrc, QTMR_Input secSrc,
270 bool masterMode, bool enExtForce, uint8_t faultFiltCount,
271 uint8_t faultFiltPer, QTMR_DbgMode dbgMode)
272{
273 ((QTimer_Channel *)(CHANNEL+chNum))
274 ->Init(priSrc, secSrc, masterMode, enExtForce, faultFiltCount,
275 faultFiltPer, dbgMode);
276}
277
278inline bool QTimer::
279SetupPwm(QTMR_Channel chNum, uint32_t pwmFreq, uint8_t dutyPcnt,
280 bool invertPolarity, uint32_t srcFreq)
281{
282 return ((QTimer_Channel *)(CHANNEL+chNum))
283 ->SetupPwm(pwmFreq, dutyPcnt, invertPolarity, srcFreq);
284}
285
286
287inline void QTimer::
288SetupCapture(QTMR_Channel chNum, QTMR_Input pin, bool invertPolarity,
289 bool reloadOnCapture, QTMR_CapEdge edge)
290{
291 ((QTimer_Channel *)(CHANNEL+chNum))
292 ->SetupCapture(pin, invertPolarity, reloadOnCapture, edge);
293}
294
295inline void QTimer::
296ConfigOutput(QTMR_Channel chNum, bool enabled, bool invertPolarity, QTMR_OutMode mode)
297{
298 ((QTimer_Channel *)(CHANNEL+chNum))->ConfigOutput(enabled,invertPolarity,mode);
299}
300
301inline void QTimer::
302ForceOutput(QTMR_Channel chNum, bool val)
303{
304 ((QTimer_Channel *)(CHANNEL+chNum))->ForceOutput(val);
305}
306
307inline void QTimer::
308EnableIRQs(QTMR_Channel chNum, uint32_t mask)
309{
310 ((QTimer_Channel *)(CHANNEL+chNum))
311 ->EnableIRQs(mask);
312}
313
314inline void QTimer::
315DisableIRQs(QTMR_Channel chNum, uint32_t mask)
316{
317 ((QTimer_Channel *)(CHANNEL+chNum))
318 ->EnableIRQs(mask);
319}
320
321inline uint32_t QTimer::
322GetEnabledIRQs(QTMR_Channel chNum)
323{
324 return ((QTimer_Channel *)(CHANNEL+chNum))
325 ->GetEnabledIRQs();
326}
327
328inline uint32_t QTimer::
329GetStatus(QTMR_Channel chNum)
330{
331 return ((QTimer_Channel *)(CHANNEL+chNum))
332 ->GetStatus();
333}
334
335inline void QTimer::
336ClearStatus(QTMR_Channel chNum, uint32_t mask)
337{
338 ((QTimer_Channel *)(CHANNEL+chNum))
339 ->ClearStatus(mask);
340}
341
342inline void QTimer::
343SetPeriod(QTMR_Channel chNum, uint16_t period)
344{
345 ((QTimer_Channel *)(CHANNEL+chNum))
346 ->SetPeriod(period);
347}
348
349inline void QTimer::
350EnableDMA(QTMR_Channel chNum, uint32_t mask)
351{
352 ((QTimer_Channel *)(CHANNEL+chNum))
353 ->EnableDMA(mask);
354}
355
356inline void QTimer::
357DisableDMA(QTMR_Channel chNum, uint32_t mask)
358{
359 ((QTimer_Channel *)(CHANNEL+chNum))
360 ->DisableDMA(mask);
361}
362
363inline QTimer_Channel & QTimer::
364operator[](int i)
365{ return *(QTimer_Channel *)(CHANNEL+i); }
366
367inline QTimer *QTimer::
368TMR(TMR_Type *tmr)
369{ return (QTimer *)tmr; }
370
371inline uint16_t QTimer::
372GetCurCount(QTMR_Channel chNum)
373{ return CHANNEL[chNum].CNTR; }
374
375inline void QTimer::
376Start(QTMR_Channel chNum, QTMR_CountMode mode)
377{
378 CHANNEL[chNum].CTRL =
379 (CHANNEL[chNum].CTRL & (uint16_t)(~(TMR_CTRL_CM_MASK)))
380 | TMR_CTRL_CM(mode);
381}
382
383inline QTMR_CountMode QTimer::
384Stop(QTMR_Channel chNum)
385{
386 uint8_t mode = (CHANNEL[chNum].CTRL & TMR_CTRL_CM_MASK) >> TMR_CTRL_CM_SHIFT;
387 CHANNEL[chNum].CTRL &= (uint16_t)(~(TMR_CTRL_CM_MASK));
388 return (QTMR_CountMode)mode;
389}
390
391inline QTMR_CountMode QTimer::
392GetCurMode(QTMR_Channel chNum)
393{
394 uint8_t mode = (CHANNEL[chNum].CTRL & TMR_CTRL_CM_MASK) >> TMR_CTRL_CM_SHIFT;
395 return (QTMR_CountMode)mode;
396}
397
398inline void QTimer::
399EnableChannels(uint16_t mask)
400{
401 CHANNEL[0].ENBL |= mask;
402}
403
404
405
406inline void QTimer::
407DisableChannels(uint16_t mask)
408{
409 CHANNEL[0].ENBL &= ~mask;
410}
411
412inline uint16_t QTimer_Channel::
413GetCurCount()
414{ return CNTR; }
415
416inline void QTimer_Channel::
417Start(QTMR_CountMode mode)
418{
419 CTRL = (CTRL & (uint16_t)(~(TMR_CTRL_CM_MASK))) | TMR_CTRL_CM(mode);
420}
421
422inline QTMR_CountMode QTimer_Channel::
423Stop()
424{
425 uint8_t mode = (CTRL & TMR_CTRL_CM_MASK) >> TMR_CTRL_CM_SHIFT;
426 CTRL &= (uint16_t)(~(TMR_CTRL_CM_MASK));
427 return (QTMR_CountMode)mode;
428}
429
430inline QTMR_CountMode QTimer_Channel::
431GetCurMode()
432{
433 uint8_t mode = (CTRL & TMR_CTRL_CM_MASK) >> TMR_CTRL_CM_SHIFT;
434 return (QTMR_CountMode)mode;
435}
436
437inline void QTimer_Channel::
438ConfigOutput(bool enabled, bool invertPolarity, QTMR_OutMode mode)
439{
440 SCTRL = (SCTRL & ~(TMR_SCTRL_OPS_MASK | TMR_SCTRL_OEN_MASK))
441 | TMR_SCTRL_OPS(invertPolarity) | TMR_SCTRL_OEN(enabled);
442 CTRL = (CTRL & ~(TMR_CTRL_OUTMODE_MASK))
443 | TMR_CTRL_OUTMODE(mode);
444}
445
446inline void QTimer_Channel::
447ForceOutput(bool val)
448{
449 SCTRL = (SCTRL & ~(TMR_SCTRL_VAL_MASK))
450 | TMR_SCTRL_VAL(val) | TMR_SCTRL_FORCE(1);
451}
452
453
454
455#endif /* ----- #ifndef __QTMR_H ----- */