FlexcanInterruptTransfer/src/fsl_flexcan.h

#ifndef DOXYGEN_SHOULD_SKIP_THIS
 
/*
 * Copyright (c) 2015, Freescale Semiconductor, Inc.
 * Copyright 2016-2023 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
#ifndef FSL_FLEXCAN_H_
#define FSL_FLEXCAN_H_
 
#include "fsl_common.h"
#include <MIMXRT1061_features.h>
 
/******************************************************************************
 * Definitions
 *****************************************************************************/
 
#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 11, 6))
#if !(defined(FLEXCAN_WAIT_TIMEOUT) && FLEXCAN_WAIT_TIMEOUT)
/* Define to 1000 means keep waiting 1000 times until the flag is assert/deassert.  */
#define FLEXCAN_WAIT_TIMEOUT (1000U)
#endif
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
#define DLC_LENGTH_DECODE(dlc) (((dlc) <= 8U) ? (dlc) : (((dlc) <= 12U) ? (((dlc)-6U) * 4U) : (((dlc)-11U) * 16U)))
#endif
 
#define FLEXCAN_ID_STD(id) \
    (((uint32_t)(((uint32_t)(id)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) 
#define FLEXCAN_ID_EXT(id)                                \
    (((uint32_t)(((uint32_t)(id)) << CAN_ID_EXT_SHIFT)) & \
     (CAN_ID_EXT_MASK | CAN_ID_STD_MASK)) 
#define FLEXCAN_RX_MB_STD_MASK(id, rtr, ide)                                   \
    (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
     FLEXCAN_ID_STD(id)) 
#define FLEXCAN_RX_MB_EXT_MASK(id, rtr, ide)                                   \
    (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
     FLEXCAN_ID_EXT(id)) 
#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_A(id, rtr, ide)                          \
    (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
     (FLEXCAN_ID_STD(id) << 1)) 
#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH(id, rtr, ide)                     \
    (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
     (((uint32_t)(id)&0x7FF) << 19)) 
#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW(id, rtr, ide)                      \
    (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \
     (((uint32_t)(id)&0x7FF) << 3)) 
#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH(id) \
    (((uint32_t)(id)&0x7F8) << 21) 
#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH(id) \
    (((uint32_t)(id)&0x7F8) << 13) 
#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW(id) \
    (((uint32_t)(id)&0x7F8) << 5) 
#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(id) \
    (((uint32_t)(id)&0x7F8) >> 3) 
#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide)                          \
    (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
     (FLEXCAN_ID_EXT(id) << 1)) 
#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH(id, rtr, ide)                        \
    (                                                                             \
        ((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
        ((FLEXCAN_ID_EXT(id) & 0x1FFF8000)                                        \
         << 1)) 
#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(id, rtr, ide)                      \
    (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \
     ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) >>                                     \
      15)) 
#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH(id) \
    ((FLEXCAN_ID_EXT(id) & 0x1FE00000) << 3) 
#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH(id) \
    ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >>            \
     5) 
#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_LOW(id) \
    ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >>           \
     13) 
#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_LOW(id) \
    ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> 21) 
#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_A(id, rtr, ide) \
    FLEXCAN_RX_FIFO_STD_MASK_TYPE_A(id, rtr, ide) 
#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_HIGH(id, rtr, ide) \
    FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH(                    \
        id, rtr, ide) 
#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_LOW(id, rtr, ide) \
    FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW(                    \
        id, rtr, ide) 
#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_HIGH(id) \
    FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH(          \
        id) 
#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_HIGH(id) \
    FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH(          \
        id) 
#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_LOW(id) \
    FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW(          \
        id) 
#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id) \
    FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(          \
        id) 
#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_A(id, rtr, ide) \
    FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) 
#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_HIGH(id, rtr, ide) \
    FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH(                    \
        id, rtr, ide) 
#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_LOW(id, rtr, ide) \
    FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(                    \
        id, rtr, ide) 
#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id) \
    FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH(          \
        id) 
#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_HIGH(id) \
    FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH(          \
        id) 
#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_LOW(id) \
    FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_LOW(          \
        id) 
#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_LOW(id) \
    FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_LOW(id) 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
#define ENHANCED_RX_FIFO_FSCH(x) (((uint32_t)(((uint32_t)(x)) << 30)) & 0xC0000000U)
#define RTR_STD_HIGH(x)          (((uint32_t)(((uint32_t)(x)) << 27)) & 0x08000000U)
#define RTR_STD_LOW(x)           (((uint32_t)(((uint32_t)(x)) << 11)) & 0x00000800U)
#define RTR_EXT(x)               (((uint32_t)(((uint32_t)(x)) << 29)) & 0x40000000U)
#define ID_STD_LOW(id)           (((uint32_t)id) & 0x7FFU)
#define ID_STD_HIGH(id)          (((uint32_t)(((uint32_t)(id)) << 16)) & 0x07FF0000U)
#define ID_EXT(id)               (((uint32_t)id) & 0x1FFFFFFFU)
 
#define FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(id, rtr, id_mask, rtr_mask) \
    (ENHANCED_RX_FIFO_FSCH(0x0) | RTR_STD_HIGH(rtr) | ID_STD_HIGH(id) | RTR_STD_LOW(rtr_mask) | ID_STD_LOW(id_mask))
#define FLEXCAN_ENHANCED_RX_FIFO_STD_FILTER_WITH_RANGE(id_upper, rtr, id_lower, rtr_mask)             \
    (ENHANCED_RX_FIFO_FSCH(0x1) | RTR_STD_HIGH(rtr) | ID_STD_HIGH(id_upper) | RTR_STD_LOW(rtr_mask) | \
     ID_STD_LOW(id_lower))
#define FLEXCAN_ENHANCED_RX_FIFO_STD_TWO_FILTERS(id1, rtr1, id2, rtr2) \
    (ENHANCED_RX_FIFO_FSCH(0x2) | RTR_STD_HIGH(rtr1) | ID_STD_HIGH(id1) | RTR_STD_LOW(rtr2) | ID_STD_LOW(id2))
#define FLEXCAN_ENHANCED_RX_FIFO_EXT_MASK_AND_FILTER_LOW(id, rtr) \
    (ENHANCED_RX_FIFO_FSCH(0x0) | RTR_EXT(rtr) | ID_EXT(id))
#define FLEXCAN_ENHANCED_RX_FIFO_EXT_MASK_AND_FILTER_HIGH(id_mask, rtr_mask) \
    (ENHANCED_RX_FIFO_FSCH(0x0) | RTR_EXT(rtr_mask) | ID_EXT(id_mask))
#define FLEXCAN_ENHANCED_RX_FIFO_EXT_FILTER_WITH_RANGE_LOW(id_upper, rtr) \
    (ENHANCED_RX_FIFO_FSCH(0x1) | RTR_EXT(rtr) | ID_EXT(id_upper))
#define FLEXCAN_ENHANCED_RX_FIFO_EXT_FILTER_WITH_RANGE_HIGH(id_lower, rtr_mask) \
    (ENHANCED_RX_FIFO_FSCH(0x1) | RTR_EXT(rtr_mask) | ID_EXT(id_lower))
#define FLEXCAN_ENHANCED_RX_FIFO_EXT_TWO_FILTERS_LOW(id2, rtr2) \
    (ENHANCED_RX_FIFO_FSCH(0x2) | RTR_EXT(rtr2) | ID_EXT(id2))
#define FLEXCAN_ENHANCED_RX_FIFO_EXT_TWO_FILTERS_HIGH(id1, rtr1) \
    (ENHANCED_RX_FIFO_FSCH(0x2) | RTR_EXT(rtr1) | ID_EXT(id1))
#endif
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
#define FLEXCAN_PN_STD_MASK(id, rtr)                            \
    ((uint32_t)((uint32_t)(rtr) << CAN_FLT_ID1_FLT_RTR_SHIFT) | \
     FLEXCAN_ID_STD(id)) 
#define FLEXCAN_PN_EXT_MASK(id, rtr)                                                                 \
    ((uint32_t)CAN_FLT_ID1_FLT_IDE_MASK | (uint32_t)((uint32_t)(rtr) << CAN_FLT_ID1_FLT_RTR_SHIFT) | \
     FLEXCAN_ID_EXT(id)) 
#endif
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
#define FLEXCAN_PN_INT_MASK(x)      (((uint64_t)(((uint64_t)(x)) << 32)) & 0x3000000000000U)
#define FLEXCAN_PN_INT_UNMASK(x)    (((uint32_t)(((uint64_t)(x)) >> 32)) & 0x00030000U)
#define FLEXCAN_PN_STATUS_MASK(x)   (((uint64_t)(((uint64_t)(x)) << 16)) & 0x300000000U)
#define FLEXCAN_PN_STATUS_UNMASK(x) (((uint32_t)(((uint64_t)(x)) >> 16)) & 0x00030000U)
#endif
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
#define FLEXCAN_EFIFO_INT_MASK(x)      (((uint64_t)(((uint64_t)(x)) << 32)) & 0xF000000000000000U)
#define FLEXCAN_EFIFO_INT_UNMASK(x)    (((uint32_t)(((uint64_t)(x)) >> 32)) & 0xF0000000U)
#define FLEXCAN_EFIFO_STATUS_MASK(x)   (((uint64_t)(((uint64_t)(x)) << 32)) & 0xF003000000000000U)
#define FLEXCAN_EFIFO_STATUS_UNMASK(x) (((uint32_t)(((uint64_t)(x)) >> 32)) & 0xF0030000U)
#endif
#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
#define FLEXCAN_MECR_INT_MASK(x)      (((uint64_t)(((uint64_t)(x)) << 16)) & 0xD00000000U)
#define FLEXCAN_MECR_INT_UNMASK(x)    (((uint32_t)(((uint64_t)(x)) >> 16)) & 0x000D0000U)
#define FLEXCAN_MECR_STATUS_MASK(x)   (((uint64_t)(((uint64_t)(x)) << 34)) & 0x34003400000000U)
#define FLEXCAN_MECR_STATUS_UNMASK(x) (((uint32_t)(((uint64_t)(x)) >> 34)) & 0x000D000DU)
#endif
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
#define FLEXCAN_ERROR_AND_STATUS_INIT_FLAG                                                                            \
    ((uint32_t)kFLEXCAN_ErrorOverrunFlag | (uint32_t)kFLEXCAN_FDErrorIntFlag | (uint32_t)kFLEXCAN_BusoffDoneIntFlag | \
     (uint32_t)kFLEXCAN_TxWarningIntFlag | (uint32_t)kFLEXCAN_RxWarningIntFlag | (uint32_t)kFLEXCAN_BusOffIntFlag |   \
     (uint32_t)kFLEXCAN_ErrorIntFlag | FLEXCAN_MEMORY_ERROR_INIT_FLAG)
#else
#define FLEXCAN_ERROR_AND_STATUS_INIT_FLAG                                                                          \
    ((uint32_t)kFLEXCAN_TxWarningIntFlag | (uint32_t)kFLEXCAN_RxWarningIntFlag | (uint32_t)kFLEXCAN_BusOffIntFlag | \
     (uint32_t)kFLEXCAN_ErrorIntFlag | FLEXCAN_MEMORY_ERROR_INIT_FLAG)
#endif
#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
#define FLEXCAN_WAKE_UP_FLAG \
    ((uint32_t)kFLEXCAN_WakeUpIntFlag | (uint64_t)kFLEXCAN_PNMatchIntFlag | (uint64_t)kFLEXCAN_PNTimeoutIntFlag)
#else
#define FLEXCAN_WAKE_UP_FLAG ((uint32_t)kFLEXCAN_WakeUpIntFlag)
#endif
#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
#define FLEXCAN_MEMORY_ERROR_INIT_FLAG ((uint64_t)kFLEXCAN_AllMemoryErrorFlag)
#else
#define FLEXCAN_MEMORY_ERROR_INIT_FLAG (0U)
#endif
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
#define FLEXCAN_MEMORY_ENHANCED_RX_FIFO_INIT_FLAG                                             \
    ((uint64_t)kFLEXCAN_ERxFifoUnderflowIntFlag | (uint64_t)kFLEXCAN_ERxFifoOverflowIntFlag | \
     (uint64_t)kFLEXCAN_ERxFifoWatermarkIntFlag | (uint64_t)kFLEXCAN_ERxFifoDataAvlIntFlag)
#endif
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
#define E_RX_FIFO(base) ((uintptr_t)(base) + 0x2000U)
#else
#define FLEXCAN_MEMORY_ENHANCED_RX_FIFO_INIT_FLAG (0U)
#endif
enum
{
    kStatus_FLEXCAN_TxBusy       = MAKE_STATUS(kStatusGroup_FLEXCAN, 0), 
    kStatus_FLEXCAN_TxIdle       = MAKE_STATUS(kStatusGroup_FLEXCAN, 1), 
    kStatus_FLEXCAN_TxSwitchToRx = MAKE_STATUS(
        kStatusGroup_FLEXCAN, 2), 
    kStatus_FLEXCAN_RxBusy         = MAKE_STATUS(kStatusGroup_FLEXCAN, 3), 
    kStatus_FLEXCAN_RxIdle         = MAKE_STATUS(kStatusGroup_FLEXCAN, 4), 
    kStatus_FLEXCAN_RxOverflow     = MAKE_STATUS(kStatusGroup_FLEXCAN, 5), 
    kStatus_FLEXCAN_RxFifoBusy     = MAKE_STATUS(kStatusGroup_FLEXCAN, 6), 
    kStatus_FLEXCAN_RxFifoIdle     = MAKE_STATUS(kStatusGroup_FLEXCAN, 7), 
    kStatus_FLEXCAN_RxFifoOverflow = MAKE_STATUS(kStatusGroup_FLEXCAN, 8), 
    kStatus_FLEXCAN_RxFifoWarning  = MAKE_STATUS(kStatusGroup_FLEXCAN, 9), 
    kStatus_FLEXCAN_RxFifoDisabled =
        MAKE_STATUS(kStatusGroup_FLEXCAN, 10), 
    kStatus_FLEXCAN_ErrorStatus = MAKE_STATUS(kStatusGroup_FLEXCAN, 11), 
    kStatus_FLEXCAN_WakeUp      = MAKE_STATUS(kStatusGroup_FLEXCAN, 12), 
    kStatus_FLEXCAN_UnHandled   = MAKE_STATUS(kStatusGroup_FLEXCAN, 13), 
    kStatus_FLEXCAN_RxRemote    = MAKE_STATUS(kStatusGroup_FLEXCAN, 14), 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
    kStatus_FLEXCAN_RxFifoUnderflow =
        MAKE_STATUS(kStatusGroup_FLEXCAN, 15), 
#endif
};
 
typedef enum _flexcan_frame_format
{
    kFLEXCAN_FrameFormatStandard = 0x0U, 
    kFLEXCAN_FrameFormatExtend   = 0x1U, 
} flexcan_frame_format_t;
 
typedef enum _flexcan_frame_type
{
    kFLEXCAN_FrameTypeData   = 0x0U, 
    kFLEXCAN_FrameTypeRemote = 0x1U, 
} flexcan_frame_type_t;
 
typedef enum _flexcan_clock_source
{
    kFLEXCAN_ClkSrcOsc  = 0x0U, 
    kFLEXCAN_ClkSrcPeri = 0x1U, 
    kFLEXCAN_ClkSrc0    = 0x0U, 
    kFLEXCAN_ClkSrc1    = 0x1U, 
} flexcan_clock_source_t;
 
typedef enum _flexcan_wake_up_source
{
    kFLEXCAN_WakeupSrcUnfiltered = 0x0U, 
    kFLEXCAN_WakeupSrcFiltered   = 0x1U, 
} flexcan_wake_up_source_t;
 
typedef enum _flexcan_rx_fifo_filter_type
{
    kFLEXCAN_RxFifoFilterTypeA = 0x0U, 
    kFLEXCAN_RxFifoFilterTypeB =
        0x1U, 
    kFLEXCAN_RxFifoFilterTypeC =
        0x2U, 
    kFLEXCAN_RxFifoFilterTypeD = 0x3U, 
} flexcan_rx_fifo_filter_type_t;
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
typedef enum _flexcan_mb_size
{
    kFLEXCAN_8BperMB  = 0x0U, 
    kFLEXCAN_16BperMB = 0x1U, 
    kFLEXCAN_32BperMB = 0x2U, 
    kFLEXCAN_64BperMB = 0x3U, 
} flexcan_mb_size_t;
 
enum _flexcan_fd_frame_length
{
    kFLEXCAN_0BperFrame = 0x0U, 
    kFLEXCAN_1BperFrame,        
    kFLEXCAN_2BperFrame,        
    kFLEXCAN_3BperFrame,        
    kFLEXCAN_4BperFrame,        
    kFLEXCAN_5BperFrame,        
    kFLEXCAN_6BperFrame,        
    kFLEXCAN_7BperFrame,        
    kFLEXCAN_8BperFrame,        
    kFLEXCAN_12BperFrame,       
    kFLEXCAN_16BperFrame,       
    kFLEXCAN_20BperFrame,       
    kFLEXCAN_24BperFrame,       
    kFLEXCAN_32BperFrame,       
    kFLEXCAN_48BperFrame,       
    kFLEXCAN_64BperFrame,       
};
#endif
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
typedef enum _flexcan_efifo_dma_per_read_length
{
    kFLEXCAN_1WordPerRead = 0x0U, 
    kFLEXCAN_2WordPerRead,        
    kFLEXCAN_3WordPerRead,        
    kFLEXCAN_4WordPerRead,        
    kFLEXCAN_5WordPerRead,        
    kFLEXCAN_6WordPerRead,        
    kFLEXCAN_7WordPerRead,        
    kFLEXCAN_8WordPerRead,        
    kFLEXCAN_9WordPerRead,        
    kFLEXCAN_10WordPerRead,       
    kFLEXCAN_11WordPerRead,       
    kFLEXCAN_12WordPerRead,       
    kFLEXCAN_13WordPerRead,       
    kFLEXCAN_14WordPerRead,       
    kFLEXCAN_15WordPerRead,       
    kFLEXCAN_16WordPerRead,       
    kFLEXCAN_17WordPerRead,       
    kFLEXCAN_18WordPerRead,       
    kFLEXCAN_19WordPerRead        
} flexcan_efifo_dma_per_read_length_t;
#endif
 
typedef enum _flexcan_rx_fifo_priority
{
    kFLEXCAN_RxFifoPrioLow  = 0x0U, 
    kFLEXCAN_RxFifoPrioHigh = 0x1U, 
} flexcan_rx_fifo_priority_t;
 
enum _flexcan_interrupt_enable
{
    kFLEXCAN_BusOffInterruptEnable    = CAN_CTRL1_BOFFMSK_MASK, 
    kFLEXCAN_ErrorInterruptEnable     = CAN_CTRL1_ERRMSK_MASK,  
    kFLEXCAN_TxWarningInterruptEnable = CAN_CTRL1_TWRNMSK_MASK, 
    kFLEXCAN_RxWarningInterruptEnable = CAN_CTRL1_RWRNMSK_MASK, 
    kFLEXCAN_WakeUpInterruptEnable    = CAN_MCR_WAKMSK_MASK,    
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
    kFLEXCAN_FDErrorInterruptEnable = CAN_CTRL2_ERRMSK_FAST_MASK, 
#endif
#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
    kFLEXCAN_PNMatchWakeUpInterruptEnable = FLEXCAN_PN_INT_MASK(CAN_CTRL1_PN_WTOF_MSK_MASK),
    kFLEXCAN_PNTimeoutWakeUpInterruptEnable = FLEXCAN_PN_INT_MASK(CAN_CTRL1_PN_WUMF_MSK_MASK),
#endif
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
    kFLEXCAN_ERxFifoUnderflowInterruptEnable = FLEXCAN_EFIFO_INT_MASK(CAN_ERFIER_ERFUFWIE_MASK),
    kFLEXCAN_ERxFifoOverflowInterruptEnable = FLEXCAN_EFIFO_INT_MASK(CAN_ERFIER_ERFOVFIE_MASK),
    kFLEXCAN_ERxFifoWatermarkInterruptEnable = FLEXCAN_EFIFO_INT_MASK(CAN_ERFIER_ERFWMIIE_MASK),
    kFLEXCAN_ERxFifoDataAvlInterruptEnable = FLEXCAN_EFIFO_INT_MASK(CAN_ERFIER_ERFDAIE_MASK),
#endif
#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
    kFLEXCAN_HostAccessNCErrorInterruptEnable = FLEXCAN_MECR_INT_MASK(CAN_MECR_HANCEI_MSK_MASK),
    kFLEXCAN_FlexCanAccessNCErrorInterruptEnable = FLEXCAN_MECR_INT_MASK(CAN_MECR_FANCEI_MSK_MASK),
    kFLEXCAN_HostOrFlexCanCErrorInterruptEnable = FLEXCAN_MECR_INT_MASK(CAN_MECR_CEI_MSK_MASK),
#endif
};
 
enum _flexcan_flags
{
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
    kFLEXCAN_ErrorOverrunFlag  = CAN_ESR1_ERROVR_MASK,      
    kFLEXCAN_FDErrorIntFlag    = CAN_ESR1_ERRINT_FAST_MASK, 
    kFLEXCAN_BusoffDoneIntFlag = CAN_ESR1_BOFFDONEINT_MASK, 
#endif
    kFLEXCAN_SynchFlag            = CAN_ESR1_SYNCH_MASK,   
    kFLEXCAN_TxWarningIntFlag     = CAN_ESR1_TWRNINT_MASK, 
    kFLEXCAN_RxWarningIntFlag     = CAN_ESR1_RWRNINT_MASK, 
    kFLEXCAN_IdleFlag             = CAN_ESR1_IDLE_MASK,    
    kFLEXCAN_FaultConfinementFlag = CAN_ESR1_FLTCONF_MASK, 
    kFLEXCAN_TransmittingFlag     = CAN_ESR1_TX_MASK,      
    kFLEXCAN_ReceivingFlag        = CAN_ESR1_RX_MASK,      
    kFLEXCAN_BusOffIntFlag        = CAN_ESR1_BOFFINT_MASK, 
    kFLEXCAN_ErrorIntFlag         = CAN_ESR1_ERRINT_MASK,  
    kFLEXCAN_WakeUpIntFlag        = CAN_ESR1_WAKINT_MASK,  
    kFLEXCAN_ErrorFlag =
        (uint32_t)(
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
                   CAN_ESR1_STFERR_FAST_MASK | CAN_ESR1_FRMERR_FAST_MASK | CAN_ESR1_CRCERR_FAST_MASK |
                   CAN_ESR1_BIT0ERR_FAST_MASK | CAN_ESR1_BIT1ERR_FAST_MASK | CAN_ESR1_ERROVR_MASK |
#endif
                   CAN_ESR1_TXWRN_MASK | CAN_ESR1_RXWRN_MASK | CAN_ESR1_BIT1ERR_MASK | CAN_ESR1_BIT0ERR_MASK |
                   CAN_ESR1_ACKERR_MASK | CAN_ESR1_CRCERR_MASK | CAN_ESR1_FRMERR_MASK | CAN_ESR1_STFERR_MASK),
#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
    kFLEXCAN_PNMatchIntFlag   = FLEXCAN_PN_STATUS_MASK(CAN_WU_MTC_WUMF_MASK), 
    kFLEXCAN_PNTimeoutIntFlag = FLEXCAN_PN_STATUS_MASK(CAN_WU_MTC_WTOF_MASK), 
#endif
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
    kFLEXCAN_ERxFifoUnderflowIntFlag =
        FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFUFW_MASK), 
    kFLEXCAN_ERxFifoOverflowIntFlag =
        FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFOVF_MASK), 
    kFLEXCAN_ERxFifoWatermarkIntFlag =
        FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFWMI_MASK), 
    kFLEXCAN_ERxFifoDataAvlIntFlag =
        FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFDA_MASK), 
    kFLEXCAN_ERxFifoEmptyFlag = FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFE_MASK), 
    kFLEXCAN_ERxFifoFullFlag  = FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFF_MASK), 
#endif
#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
    kFLEXCAN_HostAccessNonCorrectableErrorIntFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_HANCEIF_MASK),
    kFLEXCAN_FlexCanAccessNonCorrectableErrorIntFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_FANCEIF_MASK),
    kFLEXCAN_CorrectableErrorIntFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_CEIF_MASK),
    kFLEXCAN_HostAccessNonCorrectableErrorOverrunFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_HANCEIOF_MASK),
    kFLEXCAN_FlexCanAccessNonCorrectableErrorOverrunFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_FANCEIOF_MASK),
    kFLEXCAN_CorrectableErrorOverrunFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_CEIOF_MASK),
    kFLEXCAN_AllMemoryErrorFlag =
        (kFLEXCAN_HostAccessNonCorrectableErrorIntFlag | kFLEXCAN_FlexCanAccessNonCorrectableErrorIntFlag |
         kFLEXCAN_CorrectableErrorIntFlag | kFLEXCAN_HostAccessNonCorrectableErrorOverrunFlag |
         kFLEXCAN_FlexCanAccessNonCorrectableErrorOverrunFlag | kFLEXCAN_CorrectableErrorOverrunFlag)
#endif
};
 
enum _flexcan_error_flags
{
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
    kFLEXCAN_FDStuffingError = CAN_ESR1_STFERR_FAST_MASK,       
    kFLEXCAN_FDFormError     = CAN_ESR1_FRMERR_FAST_MASK,       
    kFLEXCAN_FDCrcError      = CAN_ESR1_CRCERR_FAST_MASK,       
    kFLEXCAN_FDBit0Error     = CAN_ESR1_BIT0ERR_FAST_MASK,      
    kFLEXCAN_FDBit1Error     = (int)CAN_ESR1_BIT1ERR_FAST_MASK, 
#endif
    kFLEXCAN_TxErrorWarningFlag = CAN_ESR1_TXWRN_MASK,   
    kFLEXCAN_RxErrorWarningFlag = CAN_ESR1_RXWRN_MASK,   
    kFLEXCAN_StuffingError      = CAN_ESR1_STFERR_MASK,  
    kFLEXCAN_FormError          = CAN_ESR1_FRMERR_MASK,  
    kFLEXCAN_CrcError           = CAN_ESR1_CRCERR_MASK,  
    kFLEXCAN_AckError           = CAN_ESR1_ACKERR_MASK,  
    kFLEXCAN_Bit0Error          = CAN_ESR1_BIT0ERR_MASK, 
    kFLEXCAN_Bit1Error          = CAN_ESR1_BIT1ERR_MASK, 
};
 
enum
{
    kFLEXCAN_RxFifoOverflowFlag = CAN_IFLAG1_BUF7I_MASK, 
    kFLEXCAN_RxFifoWarningFlag  = CAN_IFLAG1_BUF6I_MASK, 
    kFLEXCAN_RxFifoFrameAvlFlag = CAN_IFLAG1_BUF5I_MASK, 
};
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
typedef enum _flexcan_memory_error_type
{
    kFLEXCAN_CorrectableError = 0U, 
    kFLEXCAN_NonCorrectableError    
} flexcan_memory_error_type_t;
 
typedef enum _flexcan_memory_access_type
{
    kFLEXCAN_MoveOutFlexCanAccess = 0U, 
    kFLEXCAN_MoveInAccess,              
    kFLEXCAN_TxArbitrationAccess,       
    kFLEXCAN_RxMatchingAccess,          
    kFLEXCAN_MoveOutHostAccess          
} flexcan_memory_access_type_t;
 
typedef enum _flexcan_byte_error_syndrome
{
    kFLEXCAN_NoError          = 0U,  
    kFLEXCAN_ParityBits0Error = 1U,  
    kFLEXCAN_ParityBits1Error = 2U,  
    kFLEXCAN_ParityBits2Error = 4U,  
    kFLEXCAN_ParityBits3Error = 8U,  
    kFLEXCAN_ParityBits4Error = 16U, 
    kFLEXCAN_DataBits0Error   = 28U, 
    kFLEXCAN_DataBits1Error   = 22U, 
    kFLEXCAN_DataBits2Error   = 19U, 
    kFLEXCAN_DataBits3Error   = 25U, 
    kFLEXCAN_DataBits4Error   = 26U, 
    kFLEXCAN_DataBits5Error   = 7U,  
    kFLEXCAN_DataBits6Error   = 21U, 
    kFLEXCAN_DataBits7Error   = 14U, 
    kFLEXCAN_AllZeroError     = 6U,  
    kFLEXCAN_AllOneError      = 31U, 
    kFLEXCAN_NonCorrectableErrors    
} flexcan_byte_error_syndrome_t;
 
typedef struct _flexcan_memory_error_report_status
{
    flexcan_memory_error_type_t errorType;   
    flexcan_memory_access_type_t accessType; 
    uint16_t accessAddress;                  
    uint32_t errorData;                      
    struct
    {
        bool byteIsRead; 
        flexcan_byte_error_syndrome_t bitAffected;
    } byteStatus[4];
} flexcan_memory_error_report_status_t;
#endif
 
#if defined(__CC_ARM)
#pragma anon_unions
#endif
typedef struct _flexcan_frame
{
    struct
    {
        uint32_t timestamp : 16; 
        uint32_t length : 4;     
        uint32_t type : 1;       
        uint32_t format : 1;     
        uint32_t : 1;            
        uint32_t idhit : 9;      
    };
    struct
    {
        uint32_t id : 29; 
        uint32_t : 3;     
    };
    union
    {
        struct
        {
            uint32_t dataWord0; 
            uint32_t dataWord1; 
        };
        struct
        {
            uint8_t dataByte3; 
            uint8_t dataByte2; 
            uint8_t dataByte1; 
            uint8_t dataByte0; 
            uint8_t dataByte7; 
            uint8_t dataByte6; 
            uint8_t dataByte5; 
            uint8_t dataByte4; 
        };
    };
} flexcan_frame_t;
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
typedef struct _flexcan_fd_frame
{
    struct
    {
        uint32_t timestamp : 16; 
        uint32_t length : 4; 
        uint32_t type : 1;   
        uint32_t format : 1; 
        uint32_t srr : 1;    
        uint32_t : 6;
        uint32_t esi : 1; 
        uint32_t brs : 1; 
        uint32_t edl : 1; 
    };
    struct
    {
        uint32_t id : 29; 
        uint32_t : 3;     
    };
    union
    {
        struct
        {
            uint32_t dataWord[16]; 
        };
        /* Note: the maximum databyte* below is actually 64, user can add them if needed,
           or just use dataWord[*] instead. */
        struct
        {
            uint8_t dataByte3; 
            uint8_t dataByte2; 
            uint8_t dataByte1; 
            uint8_t dataByte0; 
            uint8_t dataByte7; 
            uint8_t dataByte6; 
            uint8_t dataByte5; 
            uint8_t dataByte4; 
        };
    };
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
    uint32_t idhit; 
#endif
} flexcan_fd_frame_t;
#endif
 
typedef struct _flexcan_timing_config
{
    uint16_t preDivider; 
    uint8_t rJumpwidth;  
    uint8_t phaseSeg1;   
    uint8_t phaseSeg2;   
    uint8_t propSeg;     
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
    uint16_t fpreDivider; 
    uint8_t frJumpwidth;  
    uint8_t fphaseSeg1;   
    uint8_t fphaseSeg2;   
    uint8_t fpropSeg;     
#endif
} flexcan_timing_config_t;
 
typedef struct _flexcan_config
{
    union
    {
        struct
        {
            uint32_t baudRate; 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
            uint32_t baudRateFD; 
#endif
        };
        struct
        {
            uint32_t bitRate; 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
            uint32_t bitRateFD; 
#endif
        };
    };
    flexcan_clock_source_t clkSrc;      
    flexcan_wake_up_source_t wakeupSrc; 
    uint8_t maxMbNum;                   
    bool enableLoopBack;                
    bool enableTimerSync;               
    bool enableSelfWakeup;              
    bool enableIndividMask;             
    bool disableSelfReception;          
    bool enableListenOnlyMode;          
#if !(defined(FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT)
    bool enableSupervisorMode; 
#endif
#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT)
    bool enableDoze; 
#endif
#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
    bool enablePretendedeNetworking; 
#endif
#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
    bool enableMemoryErrorControl; 
    bool enableNonCorrectableErrorEnterFreeze; 
#endif
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG)
    bool enableTransceiverDelayMeasure; 
#endif
    flexcan_timing_config_t timingConfig; /* Protocol timing . */
} flexcan_config_t;
 
typedef struct _flexcan_rx_mb_config
{
    uint32_t id;                   
    flexcan_frame_format_t format; 
    flexcan_frame_type_t type;     
} flexcan_rx_mb_config_t;
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
typedef enum _flexcan_pn_match_source
{
    kFLEXCAN_PNMatSrcID = 0U,   
    kFLEXCAN_PNMatSrcIDAndData, 
} flexcan_pn_match_source_t;
 
typedef enum _flexcan_pn_match_mode
{
    kFLEXCAN_PNMatModeEqual = 0x0U, 
    kFLEXCAN_PNMatModeGreater, 
    kFLEXCAN_PNMatModeSmaller, 
    kFLEXCAN_PNMatModeRange,   
} flexcan_pn_match_mode_t;
 
typedef struct _flexcan_pn_config
{
    bool enableTimeout;    
    uint16_t timeoutValue; 
    bool enableMatch;      
    flexcan_pn_match_source_t matchSrc; 
    uint8_t matchNum; 
    flexcan_pn_match_mode_t idMatchMode;   
    flexcan_pn_match_mode_t dataMatchMode; 
    uint32_t idLower;    
    uint32_t idUpper;    
    uint8_t lengthLower; 
    uint8_t lengthUpper; 
    union
    {
        struct
        {
            uint32_t lowerWord0; 
            uint32_t lowerWord1; 
        };
        struct
        {
            uint8_t lowerByte3; 
            uint8_t lowerByte2; 
            uint8_t lowerByte1; 
            uint8_t lowerByte0; 
            uint8_t lowerByte7; 
            uint8_t lowerByte6; 
            uint8_t lowerByte5; 
            uint8_t lowerByte4; 
        };
    };
    union
    {
        struct
        {
            uint32_t upperWord0; 
            uint32_t upperWord1; 
        };
        struct
        {
            uint8_t upperByte3; 
            uint8_t upperByte2; 
            uint8_t upperByte1; 
            uint8_t upperByte0; 
            uint8_t upperByte7; 
            uint8_t upperByte6; 
            uint8_t upperByte5; 
            uint8_t upperByte4; 
        };
    };
} flexcan_pn_config_t;
#endif
 
typedef struct _flexcan_rx_fifo_config
{
    uint32_t *idFilterTable;                    
    uint8_t idFilterNum;                        
    flexcan_rx_fifo_filter_type_t idFilterType; 
    flexcan_rx_fifo_priority_t priority;        
} flexcan_rx_fifo_config_t;
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
typedef struct _flexcan_enhanced_rx_fifo_std_id_filter
{
    uint32_t filterType : 2; 
    uint32_t : 2;
    uint32_t rtr1 : 1;  
    uint32_t std1 : 11; 
    uint32_t : 4;
    uint32_t rtr2 : 1;  
    uint32_t std2 : 11; 
} flexcan_enhanced_rx_fifo_std_id_filter_t;
 
typedef struct _flexcan_enhanced_rx_fifo_ext_id_filter
{
    uint32_t filterType : 2; 
    uint32_t rtr1 : 1;       
    uint32_t std1 : 29;      
    uint32_t : 2;
    uint32_t rtr2 : 1;  
    uint32_t std2 : 29; 
} flexcan_enhanced_rx_fifo_ext_id_filter_t;
typedef struct _flexcan_enhanced_rx_fifo_config
{
    uint32_t *idFilterTable;   
    uint8_t idFilterPairNum;   
    uint8_t extendIdFilterNum; 
    uint8_t fifoWatermark; 
    flexcan_efifo_dma_per_read_length_t dmaPerReadLength; 
    flexcan_rx_fifo_priority_t priority;                  
} flexcan_enhanced_rx_fifo_config_t;
#endif
 
typedef struct _flexcan_mb_transfer
{
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
    flexcan_fd_frame_t *framefd;
#endif
    flexcan_frame_t *frame; 
    uint8_t mbIdx;          
} flexcan_mb_transfer_t;
 
typedef struct _flexcan_fifo_transfer
{
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
    flexcan_fd_frame_t *framefd; 
#endif
    flexcan_frame_t *frame; 
    size_t frameNum;        
} flexcan_fifo_transfer_t;
 
typedef struct _flexcan_handle flexcan_handle_t;
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) || \
    (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
#define FLEXCAN_CALLBACK(x) \
    void(x)(CAN_Type * base, flexcan_handle_t * handle, status_t status, uint64_t result, void *userData)
typedef void (*flexcan_transfer_callback_t)(
    CAN_Type *base, flexcan_handle_t *handle, status_t status, uint64_t result, void *userData);
#else
#define FLEXCAN_CALLBACK(x) \
    void(x)(CAN_Type * base, flexcan_handle_t * handle, status_t status, uint32_t result, void *userData)
typedef void (*flexcan_transfer_callback_t)(
    CAN_Type *base, flexcan_handle_t *handle, status_t status, uint32_t result, void *userData);
#endif
 
struct _flexcan_handle
{
    flexcan_transfer_callback_t callback; 
    void *userData;                       
    flexcan_frame_t
        *volatile mbFrameBuf[CAN_WORD1_COUNT]; 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
    flexcan_fd_frame_t
        *volatile mbFDFrameBuf[CAN_WORD1_COUNT]; 
#endif
    flexcan_frame_t *volatile rxFifoFrameBuf; 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
    flexcan_fd_frame_t *volatile rxFifoFDFrameBuf; 
#endif
    size_t rxFifoFrameNum; 
    size_t rxFifoTransferTotalNum; 
    volatile uint8_t mbState[CAN_WORD1_COUNT];    
    volatile uint8_t rxFifoState;                 
    volatile uint32_t timestamp[CAN_WORD1_COUNT]; 
};
 
/******************************************************************************
 * API
 *****************************************************************************/
 
#if defined(__cplusplus)
extern "C" {
#endif
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
bool FLEXCAN_IsInstanceHasFDMode(CAN_Type *base);
#endif
 
void FLEXCAN_EnterFreezeMode(CAN_Type *base);
 
void FLEXCAN_ExitFreezeMode(CAN_Type *base);
 
uint32_t FLEXCAN_GetInstance(CAN_Type *base);
 
bool FLEXCAN_CalculateImprovedTimingValues(CAN_Type *base,
                                           uint32_t bitRate,
                                           uint32_t sourceClock_Hz,
                                           flexcan_timing_config_t *pTimingConfig);
 
void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz);
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
bool FLEXCAN_FDCalculateImprovedTimingValues(CAN_Type *base,
                                             uint32_t bitRate,
                                             uint32_t bitRateFD,
                                             uint32_t sourceClock_Hz,
                                             flexcan_timing_config_t *pTimingConfig);
void FLEXCAN_FDInit(
    CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz, flexcan_mb_size_t dataSize, bool brs);
#endif
 
void FLEXCAN_Deinit(CAN_Type *base);
 
void FLEXCAN_GetDefaultConfig(flexcan_config_t *pConfig);
 
void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig);
 
status_t FLEXCAN_SetBitRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t bitRate_Bps);
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
void FLEXCAN_SetFDTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig);
 
status_t FLEXCAN_SetFDBitRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t bitRateN_Bps, uint32_t bitRateD_Bps);
#endif
 
void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask);
 
void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask);
 
void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask);
 
void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable);
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
void FLEXCAN_SetFDTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable);
#endif
 
void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConfig, bool enable);
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConfig, bool enable);
#endif
 
void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *pRxFifoConfig, bool enable);
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
void FLEXCAN_SetEnhancedRxFifoConfig(CAN_Type *base, const flexcan_enhanced_rx_fifo_config_t *pConfig, bool enable);
#endif
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
void FLEXCAN_SetPNConfig(CAN_Type *base, const flexcan_pn_config_t *pConfig);
#endif
#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) ||                   \
    (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) || \
    (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
static inline uint64_t FLEXCAN_GetStatusFlags(CAN_Type *base)
{
    uint64_t tempflag = (uint64_t)base->ESR1;
#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
    /* Get PN Wake Up status. */
    tempflag |= FLEXCAN_PN_STATUS_MASK(base->WU_MTC);
#endif
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
    /* Get Enhanced Rx FIFO status. */
    tempflag |= FLEXCAN_EFIFO_STATUS_MASK(base->ERFSR);
#endif
#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
    /* Get Memory Error status. */
    tempflag |= FLEXCAN_MECR_STATUS_MASK(base->ERRSR);
#endif
    return tempflag;
}
#else
static inline uint32_t FLEXCAN_GetStatusFlags(CAN_Type *base)
{
    return base->ESR1;
}
#endif
#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) ||                   \
    (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) || \
    (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint64_t mask)
{
#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
    /* Clear PN Wake Up status. */
    base->WU_MTC = FLEXCAN_PN_STATUS_UNMASK(mask);
#endif
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
    /* Clear Enhanced Rx FIFO status. */
    base->ERFSR = FLEXCAN_EFIFO_STATUS_UNMASK(mask);
#endif
#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
    /* Clear Memory Error status. */
    base->ERRSR = FLEXCAN_MECR_STATUS_UNMASK(mask);
#endif
    base->ESR1 = (uint32_t)(mask & 0xFFFFFFFFU);
}
#else
static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint32_t mask)
{
    /* Write 1 to clear status flag. */
    base->ESR1 = mask;
}
#endif
static inline void FLEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf)
{
    if (NULL != txErrBuf)
    {
        *txErrBuf = (uint8_t)((base->ECR & CAN_ECR_TXERRCNT_MASK) >> CAN_ECR_TXERRCNT_SHIFT);
    }
 
    if (NULL != rxErrBuf)
    {
        *rxErrBuf = (uint8_t)((base->ECR & CAN_ECR_RXERRCNT_MASK) >> CAN_ECR_RXERRCNT_SHIFT);
    }
}
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
static inline uint64_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint64_t mask)
#else
static inline uint32_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint32_t mask)
#endif
{
#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
    uint64_t tempflag = (uint64_t)base->IFLAG1;
    return (tempflag | (((uint64_t)base->IFLAG2) << 32)) & mask;
#else
    return (base->IFLAG1 & mask);
#endif
}
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB)
static inline uint64_t FLEXCAN_GetHigh64MbStatusFlags(CAN_Type *base, uint64_t mask)
{
    uint64_t tempflag = 0U;
#if defined(CAN_IFLAG3_BUF95TO64_MASK)
    tempflag |= (uint64_t)base->IFLAG3;
#endif
#if defined(CAN_IFLAG4_BUF127TO96_MASK)
    tempflag |= (uint64_t)base->IFLAG4;
#endif
    return (tempflag & mask);
}
#endif
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint64_t mask)
#else
static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint32_t mask)
#endif
{
#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
    base->IFLAG1 = (uint32_t)(mask & 0xFFFFFFFFU);
    base->IFLAG2 = (uint32_t)(mask >> 32);
#else
    base->IFLAG1 = mask;
#endif
}
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB)
static inline void FLEXCAN_ClearHigh64MbStatusFlags(CAN_Type *base, uint64_t mask)
{
#if defined(CAN_IFLAG3_BUF95TO64_MASK)
    base->IFLAG3 = (uint32_t)(mask & 0xFFFFFFFFU);
#endif
#if defined(CAN_IFLAG4_BUF127TO96_MASK)
    base->IFLAG4 = (uint32_t)(mask >> 32U);
#endif
}
#endif
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
void FLEXCAN_GetMemoryErrorReportStatus(CAN_Type *base, flexcan_memory_error_report_status_t *errorStatus);
#endif
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
static inline uint8_t FLEXCAN_GetPNMatchCount(CAN_Type *base)
{
    return (uint8_t)((base->WU_MTC & CAN_WU_MTC_MCOUNTER_MASK) >> CAN_WU_MTC_MCOUNTER_SHIFT);
}
#endif
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
static inline uint32_t FLEXCAN_GetEnhancedFifoDataCount(CAN_Type *base)
{
    return (base->ERFSR & CAN_ERFSR_ERFEL_MASK);
}
#endif
#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) ||                   \
    (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) || \
    (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint64_t mask)
#else
static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint32_t mask)
#endif
{
    uint32_t primask = DisableGlobalIRQ();
 
    /* Solve Self Wake Up interrupt. */
    base->MCR |= (uint32_t)(mask & (uint32_t)kFLEXCAN_WakeUpInterruptEnable);
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
    if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base))
    {
        /* Solve CAN FD frames data phase error interrupt. */
        base->CTRL2 |= (uint32_t)(mask & (uint32_t)kFLEXCAN_FDErrorInterruptEnable);
    }
#endif
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
    /* Solve PN Wake Up interrupt. */
    base->CTRL1_PN |= FLEXCAN_PN_INT_UNMASK(mask);
#endif
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
    /* Solve Enhanced Rx FIFO interrupt. */
    base->ERFIER |= FLEXCAN_EFIFO_INT_UNMASK(mask);
#endif
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
    /* Solve Memory Error interrupt. */
    base->MECR |= FLEXCAN_MECR_INT_UNMASK(mask);
#endif
 
    /* Solve interrupt enable bits in CTRL1 register. */
    base->CTRL1 |=
        (uint32_t)(mask & ((uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable |
                           (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable));
 
    EnableGlobalIRQ(primask);
}
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) || \
    (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint64_t mask)
#else
static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint32_t mask)
#endif
{
    uint32_t primask = DisableGlobalIRQ();
 
    /* Solve Wake Up Interrupt. */
    base->MCR &= ~(uint32_t)(mask & (uint32_t)kFLEXCAN_WakeUpInterruptEnable);
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
    if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base))
    {
        /* Solve CAN FD frames data phase error interrupt. */
        base->CTRL2 &= ~(uint32_t)(mask & (uint32_t)kFLEXCAN_FDErrorInterruptEnable);
    }
#endif
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
    /* Solve PN Wake Up Interrupt. */
    base->CTRL1_PN &= ~FLEXCAN_PN_STATUS_UNMASK(mask);
#endif
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
    /* Solve Enhanced Rx FIFO interrupt. */
    base->ERFIER &= ~FLEXCAN_EFIFO_INT_UNMASK(mask);
#endif
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
    /* Solve Memory Error Interrupt. */
    base->MECR &= ~FLEXCAN_MECR_STATUS_UNMASK(mask);
#endif
 
    /* Solve interrupt enable bits in CTRL1 register. */
    base->CTRL1 &=
        ~(uint32_t)(mask & ((uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable |
                            (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable));
 
    EnableGlobalIRQ(primask);
}
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint64_t mask)
#else
static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint32_t mask)
#endif
{
    uint32_t primask = DisableGlobalIRQ();
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
    base->IMASK1 |= (uint32_t)(mask & 0xFFFFFFFFU);
    base->IMASK2 |= (uint32_t)(mask >> 32);
#else
    base->IMASK1 |= mask;
#endif
    EnableGlobalIRQ(primask);
}
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB)
static inline void FLEXCAN_EnableHigh64MbInterrupts(CAN_Type *base, uint64_t mask)
{
    uint32_t primask = DisableGlobalIRQ();
 
#if defined(CAN_IMASK3_BUF95TO64M_MASK)
    base->IMASK3 |= (uint32_t)(mask & 0xFFFFFFFFU);
#endif
#if defined(CAN_IMASK4_BUF127TO96_MASK)
    base->IMASK4 |= (uint32_t)(mask >> 32U);
#endif
    EnableGlobalIRQ(primask);
}
#endif
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint64_t mask)
#else
static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint32_t mask)
#endif
{
    uint32_t primask = DisableGlobalIRQ();
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
    base->IMASK1 &= ~((uint32_t)(mask & 0xFFFFFFFFU));
    base->IMASK2 &= ~((uint32_t)(mask >> 32));
#else
    base->IMASK1 &= ~mask;
#endif
    EnableGlobalIRQ(primask);
}
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB)
static inline void FLEXCAN_DisableHigh64MbInterrupts(CAN_Type *base, uint64_t mask)
{
    uint32_t primask = DisableGlobalIRQ();
 
#if defined(CAN_IMASK3_BUF95TO64M_MASK)
    base->IMASK3 &= ~((uint32_t)(mask & 0xFFFFFFFFU));
#endif
#if defined(CAN_IMASK4_BUF127TO96_MASK)
    base->IMASK4 &= ~((uint32_t)(mask >> 32U));
#endif
    EnableGlobalIRQ(primask);
}
#endif
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA)
void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable);
 
static inline uintptr_t FLEXCAN_GetRxFifoHeadAddr(CAN_Type *base)
{
    return (uintptr_t) & (base->MB[0].CS);
}
 
#endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */
 
static inline void FLEXCAN_Enable(CAN_Type *base, bool enable)
{
    if (enable)
    {
        base->MCR &= ~CAN_MCR_MDIS_MASK;
 
        /* Wait FlexCAN exit from low-power mode. */
        while (0U != (base->MCR & CAN_MCR_LPMACK_MASK))
        {
        }
    }
    else
    {
        base->MCR |= CAN_MCR_MDIS_MASK;
 
        /* Wait FlexCAN enter low-power mode. */
        while (0U == (base->MCR & CAN_MCR_LPMACK_MASK))
        {
        }
    }
}
 
status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *pTxFrame);
 
status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame);
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_frame_t *pTxFrame);
 
status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame);
#endif
 
status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *pRxFrame);
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
status_t FLEXCAN_ReadEnhancedRxFifo(CAN_Type *base, flexcan_fd_frame_t *pRxFrame);
#endif
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
status_t FLEXCAN_ReadPNWakeUpMB(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame);
#endif
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pTxFrame);
 
status_t FLEXCAN_TransferFDReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame);
 
status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer);
 
status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer);
 
void FLEXCAN_TransferFDAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx);
 
void FLEXCAN_TransferFDAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx);
#endif
 
status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pTxFrame);
 
status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame);
 
status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *pRxFrame);
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
status_t FLEXCAN_TransferReceiveEnhancedFifoBlocking(CAN_Type *base, flexcan_fd_frame_t *pRxFrame);
#endif
 
void FLEXCAN_TransferCreateHandle(CAN_Type *base,
                                  flexcan_handle_t *handle,
                                  flexcan_transfer_callback_t callback,
                                  void *userData);
 
status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer);
 
status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer);
 
status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base,
                                                flexcan_handle_t *handle,
                                                flexcan_fifo_transfer_t *pFifoXfer);
 
status_t FLEXCAN_TransferGetReceiveFifoCount(CAN_Type *base, flexcan_handle_t *handle, size_t *count);
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
status_t FLEXCAN_TransferReceiveEnhancedFifoNonBlocking(CAN_Type *base,
                                                        flexcan_handle_t *handle,
                                                        flexcan_fifo_transfer_t *pFifoXfer);
 
static inline status_t FLEXCAN_TransferGetReceiveEnhancedFifoCount(CAN_Type *base,
                                                                   flexcan_handle_t *handle,
                                                                   size_t *count)
{
    return FLEXCAN_TransferGetReceiveFifoCount(base, handle, count);
}
#endif
 
uint32_t FLEXCAN_GetTimeStamp(flexcan_handle_t *handle, uint8_t mbIdx);
 
void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx);
 
void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx);
 
void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle);
 
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
void FLEXCAN_TransferAbortReceiveEnhancedFifo(CAN_Type *base, flexcan_handle_t *handle);
#endif
 
void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle);
 
#if defined(__cplusplus)
}
#endif
 
#endif /* FSL_FLEXCAN_H_ */
 
 
#endif // DOXYGEN_SHOULD_SKIP_THIS