Application Note: General Purpose I/O for the CFV2-40

The General Purpose I/O board is an example of how to add custom hardware to the NetBurner CFV2-40 using the 60-pin interface connector. The schematics and software drivers can be used freely in your application.

The General Purpose I/O board has the following features:

• 16 Digital Outputs (with output enable)
• 16 Digital Inputs
• A 12-bit A/D with 6 inputs
• A 10-bit D/A

Block Diagram

Schematics

Click here to view the schematics in PDF format.

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Operation Details

Chip Selects and Memory Map

Chip Select 1 (*CS1) from the ColdFire 5206e is fed into a 3-to-8 line decoder to create 8 individual chip selects:

• DIG_WR (Digital Output Write) to access the two 74HCT574 output latches
• DIG_RD (Digital Input Read) to accwss the two 74HCT573 input latches
• ADC_WR (ADC Write) to write commands to the A/D converter
• ADC_RD (ADC Read) to read A/D conversions
• DAC_WR (DAC Write) to write commands and values to the D/A converter
• DAC_LD (DAC Load) The MAX503 has an 8-bit interface, so two write are required to program all 10 bits. DAC_LD is used to transfer the 10 bits of data to the DAC output after the second read operation. Note that this is actually a read operation because the LSB of the 3-8 decoder is the R/W line.
• DO_EN_LO and DO_ENABLE_HI (Digital Output Enable Lower byte and upper byte). The 74HCT74 flip flops disable the 74HCT574 outputs on reset. Writing a "1" to the flip flops (there are 2) will enable the outputs.

The smallest block of memory that can be assigned with the ColdFire is 64kb, so *CS1 will address a 64kb block. The 3-8 line decoder uses R/W, A3, and A4 to further subdivide the 64kb memory into 8 byte segments. If we say the base address of *CS1 is defined as IO_BASE (e.g. #define IO_BASE 0x50000000), the individual chips would be mapped in memory as follows:

• IO_BASE: DIG_WR (R/W = write)
• IO_BASE: DIG_RD (R/W = read)
• IO_BASE + 0x08: ADC_WR (R/W = write)
• IO_BASE + 0x08: ADC_RD (R/W = read)
• IO_BASE + 0x10: DAC_WR_LM (R/W = write, low and middle nibbles)
• IO_BASE + 0x16: DAC_WR_H (R/W = write, high nibble) The 6 is not part of the chip select addressing; it accesses the high nibble in the MAX503.
• IO_BASE + 0x10: DAC_LD (R/W = read)
• IO_BASE + 0x18: DIG_WREN (R/W = write) Digital output latch *OE (output enable). D16 and D17 determine if the lower 8 (0x01), upper 8 (0x02), or all 16 (0x03) outputs are enabled.

A/D and D/A Operation

Please see the Maxim Semiconductor web site


Software Drivers

Click here to view example software drivers: View Drivers